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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 199 occurrences of 154 keywords
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Results
Found 896 publication records. Showing 896 according to the selection in the facets
| Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
| 1 | Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja |
Enhancement of Clock Delay Faults Testing.  |
ETS  |
2011 |
DBLP DOI BibTeX RDF |
Clock line, Test Generation, Delay faults |
| 1 | S. Saqib Khursheed, Sheng Yang 0003, Bashir M. Al-Hashimi, Xiaoyu Huang, David Flynn |
Improved DFT for Testing Power Switches. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
power switch, leakage power management, test time overhead, DFT, design for test, Sleep transistor |
| 1 | Ender Yilmaz, Sule Ozev |
Fast and Accurate DPPM Computation Using Model Based Filtering. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
DPPM, Analog/Mixed Signal, Simulation, Importance sampling, Test Quality |
| 1 | Jorge Luis Lagos-Benites, Michelangelo Grosso, Luca Sterpone, Matteo Sonza Reorda, G. Audisio, M. Pipponzi, Marco Sabatini |
A Low-Cost Emulation System for Fast Co-verification and Debug. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
FPGA, debug, System-on-Chip, co-verification |
| 1 | Dhiego Silva, Kleber Stangherlin, Letícia Maria Veiras Bolzani, Fabian Vargas 0001 |
A Hardware-Based Approach for Fault Detection in RTOS-Based Embedded Systems. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
Hardware-Based Approach, RTOS |
| 1 | Nuno Alves, Yiwen Shi, Nicholas Imbriglia, Jennifer Dworak, Kundan Nepal, R. Iris Bahar |
Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
on-chip diagnosis, test set selection, Logic Implications |
| 1 | Esa Korhonen, Juha Kostamovaara |
Memory Optimized Two-Stimuli INL Test Method for DAC-ADC Pairs. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
didital-analog conversion, algorithms, testing, histograms, linearity, analog-digital conversion |
| 1 | Alexandru Paler, Armin Alaghi, Ilia Polian, John P. Hayes |
Tomographic Testing and Validation of Probabilistic Circuits. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
Probabilistic testing, quantum computing |
| 1 | Hongxia Fang, Zhiyuan Wang, Xinli Gu, Krishnendu Chakrabarty |
Ranking of Suspect Faulty Blocks Using Dataflow Analysis and Dempster-Shafer Theory for the Diagnosis of Board-Level Functional Failures. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Mauro Scandiuzzo, Salvatore Cani, Luca Perugini, Simone Spolzino, Roberto Canegallo, Luca Perilli, Roberto Cardu, Eleonora Franchi, C. Gozzi, F. Maggioni |
Input/Output Pad for Direct Contact and Contactless Testing. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
wireless probing, I/O, SiP, capacitive coupling |
| 1 | Ioannis Voyiatzis, Costas Efstathiou, Hera Antonopoulou |
A Novel SRAM-Cell Based Input Vector Monitoring Concurrent BIST Architecture. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Afsaneh Nassery, Sule Ozev, Marian Verhelst, Mustapha Slamani |
Extraction of EVM from Transmitter System Parameters. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Zhaobo Zhang, Xrysovalantis Kavousianos, Yan Luo, Yiorgos Tsiatouhas, Krishnendu Chakrabarty |
Signature Analysis for Testing, Diagnosis, and Repair of Multi-mode Power Switches. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
Multi-Mode Power Switches, DFT for Multicore Chips, Static Power Management, Testing, Voltage-Control Oscillator |
| 1 | Yukiya Miura |
Dual Edge Triggered Flip-Flops for Noise Aware Design. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
data signal, dependable design, edge triggered flip-flop, noise, synchronous circuits |
| 1 | Min Li 0013, Michael S. Hsiao |
High-Performance Diagnostic Fault Simulation on GPUs. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
diagnostic faut simulation, general-purpose computing on graphics processing unit (GPGPU), parallel algorithm, compute unified device architecture (CUDA) |
| 1 | Brady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer |
Diagnosis of Failing Scan Cells through Orthogonal Response Compaction. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre |
Scan Attacks and Countermeasures in Presence of Scan Response Compactors. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
scan-based attack, security, testability, response compaction |
| 1 | Nicola Bombieri, Franco Fummi, Valerio Guarnieri |
Accelerating RTL Fault Simulation through RTL-to-TLM Abstraction. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
RTL fault simulation, fault simulation acceleration, RTL-to-TLM abstraction |
| 1 | Alexander Finder, André Sülflow, Görschwin Fey |
Latency Analysis for Sequential Circuits. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
Soft Error Analysis, f, Debugging, Sequential Circuits, Latency |
| 1 | Irith Pomeranz |
On Transition Fault Diagnosis Using Multicycle At-Speed Broadside Tests. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
Broadside tests, multicycle tests, fault diagnosis, transition faults |
| 1 | Xuan-Lun Huang, Ping-Ying Kang, Jiun-Lang Huang, Yung-Fa Chou, Yung-Pin Lee, Ding-Ming Kwai |
A Pre- and Post-bond Self-Testing and Calibration Methodology for SAR ADC Array in 3-D CMOS Imager. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
3-D IC testing, calibration-oriented testing, pre-, post-bond testing, SAR ADC, mixed-signal testing |
| 1 | Jaan Raik, Anna Rannaste, Maksim Jenihhin, Taavi Viilukas, Raimund Ubar, Hideo Fujiwara |
Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Sandra Irobi, Zaid Al-Ars, Said Hamdioui |
Memory Test Optimization for Parasitic Bit Line Coupling in SRAMs. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
Parasitic Bit Line coupling, SRAMs, Memory tests |
| 1 | Viacheslav Izosimov, Michele Lora, Graziano Pravadelli, Franco Fummi, Zebo Peng, Giuseppe Di Guglielmo, Masahiro Fujita |
Optimization of Assertion Placement in Time-Constrained Embedded Systems. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
time-constrained embedded systems, soft errors, executable assertions |
| 1 | Hai Yu, Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh |
Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
GRAAL, fault detection, DSP, soft error, SETs |
| 1 | Atefe Dalirsani, Stefan Holst, Melanie Elm, Hans-Joachim Wunderlich |
Structural Test for Graceful Degradation of NoC Switches. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
Logic Diagnosis, Performability, Network-on-Chip, Graceful Degradation |
| 1 | Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Ernesto Sánchez 0001, Mauricio de Carvalho, Matteo Sonza Reorda |
A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
At-speed delay fault testing, Power-aware Testing, Functional power |
| 1 | Stephen K. Sunter, Aubin Roy |
A Mixed-Signal Test Bus and Analog BIST with 'Unlimited' Time and Voltage Resolution. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
mixed-signal DFT, analog bus, mixed-signal BIST |
| 1 | Masoud Zamani, Navid Farazmand, Mehdi Baradaran Tahoori |
Fault Masking and Diagnosis in Reversible Circuits. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
Majority voter, Reversible logic, Fault masking |
| 1 | Sehun Kook, Aritra Banerjee, Abhijit Chatterjee |
Signature Testing and Diagnosis of High Precision S? ADC Dynamic Specifications Using Model Parameter Estimation. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael Nicolaidis, Vladimir Pasca, Lorena Anghel |
I-BIRAS: Interconnect Built-In Self-Repair and Adaptive Serialization in 3D Integrated Systems. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Ramachandran Venkatasubramanian, Doohwang Chang, Sule Ozev |
Analysis and Mitigation of Electromigration in RF Circuits: An LNA Case Study. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Stelios Neophytou, Kyriakos Christou, Maria K. Michael |
An Approach for Quantifying Path Correlation in Digital Circuits without any Path or Segment Enumeration. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
zero-supressed binary decision diagrams, digital circuits, path similarity |
| 1 | Uros Legat, Anton Biasizzo, Franc Novak |
FPGA Soft Error Recovery Mechanism with Small Hardware Overhead. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Massoud Mokhtarpour Ghahroodi, Mark Zwolinski, Rick Wong, Shi-Jie Wen |
Timing Vulnerability Factors of Ultra Deep-sub-micron CMOS. |
ETS |
2011 |
DBLP DOI BibTeX RDF |
|
| 1 | Peter Mrak, Anton Biasizzo, Franc Novak |
On measurement uncertainty of ADC nonlinearities in oscillation-based test. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Irith Pomeranz, Sudhakar M. Reddy |
Input test data volume reduction based on test vector chains. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Daniel Tille, Stephan Eggersglüß, Rene Krenz-Baath, Jürgen Schlöffel, Rolf Drechsler |
Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Lilia Zaourar, Jihane Alami Chentoufi, Yann Kieffer, Arnaud Wenzel, Frederic Grandvaux |
A shared BIST optimization methodology for memory test. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Gabriel de M. Borges, Luiz Fernando Gonçalves, Tiago R. Balen, Marcelo Lubaszewski |
Increasing reliability of programmable mixed-signal systems by applying design diversity redundancy. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | S. Fransi, G. L. Farre, L. Garcia-Deiros, Salvador Manich |
Design and implementation of Automatic Test Equipment IP module. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Adit D. Singh |
Modified T-Flip-Flop based scan cell for RAS. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Sobeeh Almukhaizim, Mohammad Gh. Mohammad, Mohammad Khajah |
Test power reduction in compression-based reconfigurable scan architectures. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Masaki Hashizume, Kazuya Nakaminami, Hiroyuki Yotsuyanagi, Yukinori Nakajima, Kozo Kinoshita |
Current-based testable design of level shifters in liquid crystal display drivers. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Cristiana Bolchini, Antonio Miele, Chiara Sandionigi, Niccolò Battezzati, Luca Sterpone, Massimo Violante |
An integrated flow for the design of hardened circuits on SRAM-based FPGAs. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Stefano Di Carlo, Andrea Miele, Paolo Prinetto, Antonio Trapanese |
Microprocessor fault-tolerance via on-the-fly partial reconfiguration. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Johannes Loinig, Christian Steger, Reinhold Weiss, Ernst Haselsteiner |
Fast simulation based testing of anti-tearing mechanisms for small embedded systems. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Chun-Chuan Chi, Cheng-Wen Wu, Jin-Fu Li 0001 |
A low-cost and scalable test architecture for multi-core chips. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Gaetan Canivet, P. Maistn, Régis Leveugle, Frédéric Valette, Jessy Clédière, Marc Renaudin |
Robustness evaluation and improvements under laser-based fault attacks of an AES crypto-processor implemented on a SRAM-based FPGA. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda |
An adaptive tester architecture for volume diagnosis. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Z. Xu, Andrew Richardson 0001, Lijie Li, Mark L. Begbie, D. Koltsov, C. H. Wang |
A multi-mode MEMS sensor design to support system test and health & usage monitoring applications. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine |
Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jose Luis Garcia-Gervacio, Víctor H. Champac |
Computing the detection of Small Delay Defects caused by resistive opens of nanometer ICs. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Peter C. Maxwell |
Adaptive test directions. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu Zhang, Vishwani D. Agrawal |
A diagnostic test generation system and a coverage metric. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine |
Setting test conditions for improving SRAM reliability. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Michael Campbell |
Plenary presentations: Keynote: The product complexity and test - How product complexity impacts test industry. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yu-Jen Huang, Che-Wei Chou, Jin-Fu Li 0001 |
A low-cost built-in self-test scheme for an array of memories. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Erik Larsson, Bart Vermeulen, Kees Goossens |
A distributed architecture to check global properties for post-silicon debug. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Vezio Malandruccolo, Mauro Ciappa, Wolfgang Fichtner, Hubert Rothleitner |
Novel built-in methodology for defect testing of capacitor oxide in SAR analog to digital converters for critical automotive applications. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ke Peng, Yu Huang 0005, Pinki Mallick, Wu-Tung Cheng, Mohammad Tehranipoor |
Full-circuit SPICE simulation based validation of dynamic delay estimation. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Hyunjin Kim, Jaeyong Chung, Jacob A. Abraham, Eonjo Byun, Cheol-Jong Woo |
A Built-In Self-Test scheme for high speed I/O using cycle-by-cycle edge control. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yang Jin, Hong Wang, Zhengliang Lv, Shiyuan Yang |
Pipelined parallel test structure for mixed-signal SoCs. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Shaji Krishnan, Hans G. Kerkhoff |
Multivariate model for test response analysis. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Kaouthar Bousselam, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre |
Evaluation of concurrent error detection techniques on the Advanced Encryption Standard. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Sachin Dileep Dasnurkar, Jacob A. Abraham |
Calibration-enabled scalable built-in current sensor compatible with very low cost ATE. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Ho Fai Ko, Nicola Nicolici |
Combining scan and trace buffers for enhancing real-time observability in post-silicon debugging. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jing Zeng, Ruifeng Guo, Wu-Tung Cheng, Michael Mateja, Jing Wang, Kun-Han Tsai, Ken Amstutz |
Scan based speed-path debug for a microprocessor. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Sezer Gören 0001, H. Fatih Ugurdag, Okan Palaz |
Defect-aware nanocrossbar logic mapping using Bipartite Subgraph Isomorphism & canonization. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Masoud Zamani, Mehdi Baradaran Tahoori |
A transient error tolerant self-timed asynchronous architecture. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Navid Farazmand, Mehdi Baradaran Tahoori |
Multiple fault diagnosis in crossbar nano-architectures. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Brady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer |
Diagnosis of failing scan cells through orthogonal response compaction. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiao Zhang 0002, Hans G. Kerkhoff, Bart Vermeulen |
New scan-based test strategy for a dependable many-core processor using a NoC as a Test Access Mechanism. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Michelangelo Grosso, Wilson J. Pérez H., Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda, Jaime Velasco-Medina |
A software-based self-test methodology for system peripherals. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Xiaoqin Sheng, Vincent Kerzerho, Hans G. Kerkhoff |
Predicting dynamic specifications of ADCs with a low-quality digital input signal. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Emil Gizdarski |
Constructing augmented time compactors. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Louay Abdallah, Haralampos-G. D. Stratigopoulos, Christophe Kelma, Salvador Mir |
Sensors for built-in alternate RF test. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | S. Behdad Hosseini, Ali Shahabi, Hasan Sohofi, Zainalabedin Navabi |
A reconfigurable online BIST for combinational hardware using digital neural networks. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Brandon Noia, Sandeep Kumar Goel, Krishnendu Chakrabarty, Erik Jan Marinissen, Jouke Verbree |
Test-architecture optimization for TSV-based 3D stacked ICs. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Román Mozuelos, Yolanda Lechuga, Mar Martínez, Salvador Bracho |
Test of embedded analog circuits based on a built-in current sensor. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Vladimir Pasca, Lorena Anghel, Claudia Rusu, Mounir Benabdenbi |
Configurable fault-tolerant link for inter-die communication in 3D on-chip networks. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Frank Poehl, Frank Demmerle, Juergen Alt, Hermann Obermeir |
Production test challenges for highly integrated mobile phone SOCs - A case study. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata, Hideo Fujiwara |
Test pattern selection to optimize delay test quality with a limited size of test set. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Abhijit Chatterjee |
Invited talk: Self-aware wireless communication and signal processing systems: Real-time adaptation for error resilience, low power and performance. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Sobeeh Almukhaizim, Sara Bunian, Ozgur Sinanoglu |
Reconfigurable Concurrent Error Detection adaptive to dynamicity of power constraints. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Elena I. Vatajelu, Georgios Panagopoulos, Kaushik Roy 0001, Joan Figueras |
Parametric failure analysis of embedded SRAMs using fast & accurate dynamic analysis. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Hideo Fujiwara |
Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Nader Alawadhi, Ozgur Sinanoglu, Mohammed Al-Mulla |
Add-on blocks and algorithms for improving stimulus compression. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Samed Maltabas, Osman Kubilay Ekekon, Martin Margala |
A new built-in IDDQ testing method using programmable BICS. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Jouke Verbree, Erik Jan Marinissen, Philippe Roussel, Dimitrios Velenis |
On the cost-effectiveness of matching repositories of pre-tested wafers for wafer-to-wafer 3D chip stacking. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Haralampos-G. D. Stratigopoulos, Salvador Mir, Erkan Acar, Sule Ozev |
Defect filter for alternate RF test. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Rosa Rodríguez-Montañés, Daniel Arumí, Joan Figueras, Stefan Eichenberger, Camelia Hora, Bram Kruseman |
Diagnosis of full open defects in interconnect lines with fan-out. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Claus Braun, Hans-Joachim Wunderlich |
Algorithm-based fault tolerance for many-core architectures. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Manuel J. Barragan Asian, Rafaella Fiorelli, Diego Vázquez, Adoración Rueda, José Luis Huertas |
Low-cost signature test of RF blocks based on envelope response analysis. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Paula Herber, Marcel Pockrandt, Sabine Glesner |
Automated conformance evaluation of SystemC designs using timed automata. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Yuki Yoshikawa, Tomomi Nuwa, Hideyuki Ichihara, Tomoo Inoue |
Hybrid test application in hybrid delay scan design. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | |
15th European Test Symposium, ETS 2010, Prague, Czech Republic, May 24-28, 2010 |
ETS |
2010 |
DBLP BibTeX RDF |
|
| 1 | Mitsumasa Noda, Seiji Kajihara, Yasuo Sato, Kohei Miyase, Xiaoqing Wen, Yukiya Miura |
On estimation of NBTI-Induced delay degradation. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez |
A two-layer SPICE model of the ATMEL TSTACTM eFlash memory technology for defect injection and faulty behavior prediction. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
|
| 1 | Nicolas Pous, Florence Azaïs, Laurent Latorre, Jochen Rivoir |
On the use of standard digital ATE for the analysis of RF signals. |
ETS |
2010 |
DBLP DOI BibTeX RDF |
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