Search results for "RTL"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
23	Vinoo Srinivasan, Ranga Vemuri	Task-Level Partitioning and RTL Design Space Exploration for Multi-FPGA Architectures.	FCCM	1999	DBLP DOI BibTeX RDF
23	Alessandro Bogliolo, Roberto Corgnati, Enrico Macii, Massimo Poncino	Parameterized RTL power models for combinational soft macros.	ICCAD	1999	DBLP DOI BibTeX RDF
23	Chien-Nan Jimmy Liu, Jing-Yang Jou	An Efficient Functional Coverage Test for HDL Descriptions at RTL.	ICCD	1999	DBLP DOI BibTeX RDF	verification, coverage, FSM, HDL
23	P. P. Jain	Cost-effective co-verification using RTL-accurate C models.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
23	Roberto Corgnati, Enrico Macii, Massimo Poncino	Clustered Table-Based Macromodels for RTL Power Estimation.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
23	Alessandro Bogliolo, Luca Benini	Robust RTL power macromodels.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
23	A. R. Naseer, M. Balakrishnan, Anshul Kumar	Direct mapping of RTL structures onto LUT-based FPGA's.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
23	Yiorgos Makris, Alex Orailoglu	DFT guidance through RTL test justification and propagation analysis.	ITC	1998	DBLP DOI BibTeX RDF
23	Min Xu, Fadi J. Kurdahi	RTL synthesis with physical and controller information.	ED&TC	1997	DBLP DOI BibTeX RDF
23	Kaushik Roy 0001, Jacob A. Abraham	A Novel Approach to Accurate Timing Verification Using RTL Descriptions.	DAC	1989	DBLP DOI BibTeX RDF
17	Per Karlström, Wenbiao Zhou, Dake Liu	Operation Classification for Control Path Synthetization with NoGAP.	ITNG	2010	DBLP DOI BibTeX RDF	Control path, CAD, Pipelining, ADL, ASIP, RTL
17	Ramsey Hourani, Ravi Jenkal, W. Rhett Davis, Winser E. Alexander	Automated Design Space Exploration for DSP Applications.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	VLSI, Synthesis, Throughput, DSP, RTL, FIR filter, Hardware design, Power dissipation, Area
17	David Slogsnat, Alexander Giese, Mondrian Nüssle, Ulrich Brüning 0001	An open-source HyperTransport core.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	HTX, HyperTransport, FPGA, prototyping, RTL
17	Vicente Galiano Ibarra, Héctor Migallón Gomis, David Pérez-Caparrós, Juan Alejandro Palomino Benito, Marcos Martínez	Speeding Up in Distributed SystemC Simulations.	DCAI	2008	DBLP DOI BibTeX RDF	MPI, SoC, Distributed Simulation, SystemC, RTL
17	David Slogsnat, Alexander Giese, Ulrich Brüning 0001	A versatile, low latency HyperTransport core.	FPGA	2007	DBLP DOI BibTeX RDF	HTX, HyperTransport, FPGA, prototyping, RTL
17	Anoosh Hosseini, Ashish Parikh, H. T. Chin, Pascal Urard, Emil F. Girczyc, S. Bloch	Building a standard ESL design and verification methodology: is it just a dream?	DAC	2006	DBLP DOI BibTeX RDF	modeling rapid hardware prototyping, design, verification, methodology, systemC, RTL, ESL, C/C++, systemVerilog
17	Chris Rowen, Steve Leibson	Flexible architectures for engineering successful SOCs.	DAC	2004	DBLP DOI BibTeX RDF	processor cores, MPSOC, RISC, RTL, SOC
17	Rachid Ben Abbou, Amine Benkiran, Jean-Pierre Courtiat	Formal Validation of a Multicast Transport Protocol.	ISCC	2001	DBLP DOI BibTeX RDF	SPRM protocol, Reliability, Formal methods, Multicast, RTL, LOTOS, RT-LOTOS, Protocol validation
16	Hong-Zu Chou, Kai-Hui Chang, Sy-Yen Kuo	Handling don't-care conditions in high-level synthesis and application for reducing initialized registers.	DAC	2009	DBLP DOI BibTeX RDF	RTL symbolic simulation, don't-care (DC), synthesis
16	Régis Leveugle	Early Analysis of Fault-based Attack Effects in Secure Circuits.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	RTL dependability evaluation, security validation, fault models, fault injection, fault attacks
16	Naghmeh Karimi, Shahrzad Mirkhani, Zainalabedin Navabi, Fabrizio Lombardi	RT level reliability enhancement by constructing dynamic TMRS.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	fault tolerant, reliability, TMR, RTL design
16	Cyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin 0001	A design methodology for space-time adapter.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	communication and interface synthesis, digital signal processing and multimedia applications, RTL design
16	Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose	Application-specific customization of soft processor microarchitecture.	FPGA	2006	DBLP DOI BibTeX RDF	Nios, RTL generation, SPREE, FPGA, customization, embedded processor, ASIP, microarchitecture, application specific, soft processor
16	Peter J. Osler	Placement driven synthesis case studies on two sets of two chips: hierarchical and flat.	ISPD	2004	DBLP DOI BibTeX RDF	synthesis, placement, application specific integrated circuit (ASIC), register transfer level (RTL), static timing analysis (STA), netlist
16	Michiko Inoue, Kazuhiro Suzuki, Hiroyuki Okamoto, Hideo Fujiwara	Test Synthesis for Datapaths Using Datapath-Controller Functions.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	hierarchical test generation, non-scan design, design-for-testability, at-speed testing, RTL circuit
16	Dipankar Sarkar 0001	Register Transfer Operation Analysis during Data Path Verification.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	Sequential Circuit Verification, Control Part - Data Path, Data Path Verification, RTL Behaviours
16	Alessandro Bogliolo, Luca Benini, Giovanni De Micheli	Characterization-Free Behavioral Power Modeling.	DATE	1998	DBLP DOI BibTeX RDF	Modeling, Power consumption, RTL Simulation
16	Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou	A power modeling and characterization method for macrocells using structure information.	ICCAD	1997	DBLP DOI BibTeX RDF	Power modeling for macrocells, RTL power estimations, State transition graph and Power characterization
16	X. Wendling, H. Chauvet, Lionel Revéret, Raphaël Rochet, Régis Leveugle	Automatic and Optimized Synthesis of Dataparts with Fault Detection or Tolerance Capabilities.	DFT	1997	DBLP DOI BibTeX RDF	RTL synthesis, dependable VLSI circuits, fault tolerance, fault detection, CAD tools
16	Harold Hoehne, Robert Piloty	Design Verification at the Register Transfer Language Level.	IEEE Trans. Computers	1975	DBLP DOI BibTeX RDF	Compiler-interpreter system, computer description language, hardware design automation, register transfer language (RTL), simulation, error detection, design verification
16	Kan Huang, Junlin Lu, Jiufeng Pang, Yansong Zheng, Hao Li, Dong Tong 0001, Xu Cheng 0001	FPGA prototyping of an amba-based windows-compatible SoC.	FPGA	2010	DBLP DOI BibTeX RDF	fpga, microsoft windows, amba, x86
16	Arnab Sinha, Pallab Dasgupta, Bhaskar Pal, Sayantan Das 0001, Prasenjit Basu, P. P. Chakrabarti 0001	Design intent coverage revisited.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Design Intent Coverage
16	Joachim Keinert, Martin Streubühr, Thomas Schlichter, Joachim Falk, Jens Gladigau, Christian Haubelt, Jürgen Teich, Michael Meredith	SystemCoDesigner - an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	System design, hardware/software codesign
16	Farhat Thabet, Philippe Coussy, Dominique Heller, Eric Martin 0001	Exploration and Rapid Prototyping of DSP Applications using SystemC Behavioral Simulation and High-level Synthesis.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Prototyping, Refinement, High-level synthesis, Design space exploration, System level design
16	Feng Ge, Pranjal Jain, Ken Choi	Ultra-low power and high speed design and implementation of AES and SHA1 hardware cores in 65 nanometer CMOS technology.	EIT	2009	DBLP DOI BibTeX RDF
16	Madhu Saravana Sibi Govindan, Stephen W. Keckler, Doug Burger	End-to-end validation of architectural power models.	ISLPED	2009	DBLP DOI BibTeX RDF	architectural power models, measurement, validation
16	Jason Cong, Bin Liu 0006, Zhiru Zhang	Behavior-level observability don't-cares and application to low-power behavioral synthesis.	ISLPED	2009	DBLP DOI BibTeX RDF	low power, observability, behavioral synthesis
16	Alon Gluska, Lior Libis	Shortening the verification cycle with synthesizable abstract models.	DAC	2009	DBLP DOI BibTeX RDF	verification, logic design, abstract modeling
16	Dave Whipp	Exploiting "architecture for verification" to streamline the verification process.	DAC	2009	DBLP DOI BibTeX RDF	verification, executable specification, ESL
16	Kingshuk Karuri, Anupam Chattopadhyay, Xiaolin Chen, David Kammler, Ling Hao, Rainer Leupers, Heinrich Meyr, Gerd Ascheid	A Design Flow for Architecture Exploration and Implementation of Partially Reconfigurable Processors.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
16	Nikolaos Kavvadias, Spiridon Nikolaidis 0001	Elimination of Overhead Operations in Complex Loop Structures for Embedded Microprocessors.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Optimization, Microprocessors, Hardware description languages, Real-time and embedded systems, Pipeline processors, Control design
16	Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aamodt, Jamison D. Collins, Perry H. Wang, Gautham N. Chinya, Ankur Khandelwal Groen, Hong Jiang, Hong Wang 0003	Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor.	PACT	2008	DBLP DOI BibTeX RDF	ia32, on-chip integration, chip multiprocessor, heterogeneous
16	Jörn W. Janneck, Ian D. Miller, David B. Parlour, Ghislain Roquier, Matthieu Wipliez, Mickaël Raulet	Synthesizing hardware from dataflow programs: An MPEG-4 simple profile decoder case study.	SiPS	2008	DBLP DOI BibTeX RDF
16	Sharad Malik	Hardware Verification: Techniques, Methodology and Solutions.	TACAS	2008	DBLP DOI BibTeX RDF
16	Ravi Surepeddi	System Verilog for Quality of Results (QoR).	ISQED	2008	DBLP DOI BibTeX RDF	System Verilog Design Quality Results
16	C. Richard Ho, Michael Theobald, Martin M. Deneroff, Ron O. Dror, Joseph Gagliardo, David E. Shaw	Early formal verification of conditional coverage points to identify intrinsically hard-to-verify logic.	DAC	2008	DBLP DOI BibTeX RDF	conditional coverage, inconclusive results, formal verification, code coverage, verifiability, coverage hole
16	Chung-Ho Chen, Chih-Kai Wei, Tai-Hua Lu, Hsun-Wei Gao	Software-Based Self-Testing With Multiple-Level Abstractions for Soft Processor Cores.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
16	Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee	An Overview of a Compiler for Mapping Software Binaries to Hardware.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
16	Yogesh S. Mahajan, Carven Chan, Ali Alphan Bayazit, Sharad Malik, Wei Qin	Verification Driven Formal Architecture and Microarchitecture Modeling.	MEMOCODE	2007	DBLP DOI BibTeX RDF
16	Panagiotis Manolios, Sudarshan K. Srinivasan, Daron Vroon 0001	BAT: The Bit-Level Analysis Tool.	CAV	2007	DBLP DOI BibTeX RDF
16	Mark H. Nodine	Automatic Testbench Generation for Rearchitected Designs.	MTV	2007	DBLP DOI BibTeX RDF
16	Alisson Vasconcelos de Brito, Matthias Kühnle, Michael Hübner 0001, Jürgen Becker 0001, Elmar U. K. Melcher	Modelling and Simulation of Dynamic and Partially Reconfigurable Systems using SystemC.	ISVLSI	2007	DBLP DOI BibTeX RDF
16	Yi Feng 0003, Zheng Zhou, Dong Tong 0001, Xu Cheng 0001	Clock domain crossing fault model and coverage metric for validation of SoC design.	DATE	2007	DBLP DOI BibTeX RDF
16	Jonathan A. Clarke, George A. Constantinides, Peter Y. K. Cheung	On the feasibility of early routing capacitance estimation for FPGAs.	FPL	2007	DBLP DOI BibTeX RDF
16	Gearoid Murphy, Conor Ryan	Seeding methods for run transferable libraries.	GECCO	2007	DBLP DOI BibTeX RDF	schema theory, module acquisition
16	Shin-Kai Chen, Bing-Shiun Wang, Tay-Jyi Lin, Chih-Wei Liu	Rapid C to FPGA Prototyping with Multithreaded Emulation Engine.	ISCAS	2007	DBLP DOI BibTeX RDF
16	Lilian Janin, Doug Edwards	CSP Transactors for Asynchronous Transaction Level Modeling and IP Reuse.	ICCSA (3)	2007	DBLP DOI BibTeX RDF
16	Yogesh S. Mahajan, Sharad Malik	Automating Hazard Checking in Transaction-Level Microarchitecture Models.	FMCAD	2007	DBLP DOI BibTeX RDF
16	Jacob A. Abraham, Daniel G. Saab	Tutorial T4A: Formal Verification Techniques and Tools for Complex Designs.	VLSI Design	2007	DBLP DOI BibTeX RDF
16	Shobha Vasudevan, Vinod Viswanath, Jacob A. Abraham	Efficient Microprocessor Verification using Antecedent Conditioned Slicing.	VLSI Design	2007	DBLP DOI BibTeX RDF
16	Behzad Akbarpour, Sofiène Tahar	An approach for the formal verification of DSP designs using Theorem proving.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
16	Hassan Al-Sukhni, David Lindberg, James Holt, Michele Reese	Workload Slicing for Characterizing New Features in High Performance Microprocessors.	MTV	2006	DBLP DOI BibTeX RDF
16	Ali Habibi, Sofiène Tahar, Amer Samarah, Donglin Li, Otmane Aït Mohamed	Efficient assertion based verification using TLM.	DATE	2006	DBLP DOI BibTeX RDF
16	Tomas Pecenka, Josef Strnadel, Zdenek Kotásek, Lukás Sekanina	Testability Estimation Based on Controllability and Observability Parameters.	DSD	2006	DBLP DOI BibTeX RDF
16	Jaan Raik, Raimund Ubar, Taavi Viilukas	High-Level Decision Diagram based Fault Models for Targeting FSMs.	DSD	2006	DBLP DOI BibTeX RDF
16	Ari Kulmala, Timo D. Hämäläinen, Marko Hännikäinen	Reliable GALS Implementation of MPEG-4 Encoder with Mixed Clock FIFO on Standard FPGA.	FPL	2006	DBLP DOI BibTeX RDF
16	Shujun Deng, Weimin Wu, Jinian Bian	Bounded Model Checking Combining Symbolic Trajectory Evaluation Abstraction with Hybrid Three-Valued SAT Solving.	CSCWD (Selected Papers)	2006	DBLP DOI BibTeX RDF
16	Shujun Deng, Weimin Wu, Jinian Bian	Cooperative Bounded Model Checking Using STE and Hybrid Three-Valued SAT Solving.	CSCWD	2006	DBLP DOI BibTeX RDF
16	Bita Gorjiara, Mehrdad Reshadi, Pramod Chandraiah, Daniel Gajski	Generic netlist representation for system and PE level design exploration.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	GNR, NISC, modeling, synthesis, system design, architecture description language, application-specific processor
16	Anna Slobodová	Challenges for Formal Verification in Industrial Setting.	FMICS/PDMC	2006	DBLP DOI BibTeX RDF
16	Stefan Andrei, Albert Mo Kim Cheng	Optimization of Real-Time Systems Timing Specifications.	RTCSA	2006	DBLP DOI BibTeX RDF	optimization, formal method, timing constraint
16	Donglin Li, Otmane Aït Mohamed	MDG-Based Verification of the Look-Aside Interface.	CCECE	2006	DBLP DOI BibTeX RDF
16	Namrata Shekhar, Priyank Kalla, M. Brandon Meredith, Florian Enescu	Simulation Bounds for Equivalence Verification of Arithmetic Datapaths with Finite Word-Length Operands.	FMCAD	2006	DBLP DOI BibTeX RDF
16	Loganathan Lingappan, Niraj K. Jha	Improving the Performance of Automatic Sequential Test Generation by Targeting Hard-to-Test Faults.	VLSI Design	2006	DBLP DOI BibTeX RDF
16	Philippe Georgelin, Venkat Krishnaswamy	Towards a C++-based design methodology facilitating sequential equivalence checking.	DAC	2006	DBLP DOI BibTeX RDF	modeling methodology, sequential equivalence checking
16	Guy Dupenloup, Thierry Lemeunier, Roland Mayr	Transistor abstraction for the functional verification of FPGAs.	DAC	2006	DBLP DOI BibTeX RDF	cone model, logic equivalence checking, transistor abstraction, FPGA, register transfer level, multiplexer, functional verification
16	Soha Hassoun, Murali Kudlugi, Duaine Pryor, Charles Selvidge	A transaction-based unified architecture for simulation and emulation.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
16	Chao Huang, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Generation of distributed logic-memory architectures through high-level synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
16	Patrick Schaumont, Sandeep K. Shukla, Ingrid Verbauwhede	Extended abstract: a race-free hardware modeling language.	MEMOCODE	2005	DBLP DOI BibTeX RDF
16	Diana Toma, Dominique Borrione	Formal Verification of a SHA-1 Circuit Core Using ACL2.	TPHOLs	2005	DBLP DOI BibTeX RDF
16	Tun Li, Yang Guo 0003, GongJie Liu, Sikun Li	Functional Vectors Generation for RT-Level Verilog Descriptions Based on Path Enumeration and Constraint Logic Programming.	DSD	2005	DBLP DOI BibTeX RDF
16	Ho Fai Ko, Qiang Xu 0001, Nicola Nicolici	Register-transfer level functional scan for hierarchical designs.	ASP-DAC	2005	DBLP DOI BibTeX RDF
16	K. Uday Bhaskar, M. Prasanth, V. Kamakoti 0001, Kailasnath Maneparambil	A Framework for Automatic Assembly Program Generator (A2PG) for Verification and Testing of Processor Cores.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
16	Nick Savoiu	MTP: A Petri Net-Based Framework for the Analysis and Transformation of SystemC Designs.	SCOPES	2005	DBLP DOI BibTeX RDF
16	John Sanguinetti	High level design: the future is now.	SBCCI	2005	DBLP DOI BibTeX RDF
16	Alexander B. Smirnov, Alexander Taubin, Ming Su, Mark G. Karpovsky	An Automated Fine-Grain Pipelining Using Domino Style Asynchronous Library.	ACSD	2005	DBLP DOI BibTeX RDF	asynchronous EDA, QDI, synthesis, ASIC, HDL
16	Adrian Chirila-Rus, Kristof Denolf, Bart Vanhoof, Paul R. Schumacher, Kees A. Vissers	Communication Primitives Driven Hardware Design and Test Methodology Applied on Complex Video Applications.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
16	Jorgen Peddersen, Seng Lin Shee, Andhi Janapsatya, Sri Parameswaran	Rapid Embedded Hardware/Software System Generation.	VLSI Design	2005	DBLP DOI BibTeX RDF
16	R. Gopalakrishnan, Rajat Moona	Variable Resizing for Area Improvement in Behavioral Synthesis.	VLSI Design	2005	DBLP DOI BibTeX RDF
16	Ivan Blunno, Luciano Lavagno	Designing an asynchronous microcontroller using Pipefitter.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
16	Ludovic Apvrille, Pierre de Saqui-Sannes, Patrick Sénac, Christophe Lohr	Verifying Service Continuity in a Dynamic Reconfiguration Procedure: Application to a Satellite System.	Autom. Softw. Eng.	2004	DBLP DOI BibTeX RDF	real-time UML, dynamic reconfiguration, satellite, formal validation, RT-LOTOS
16	Yunsi Fei, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	A hybrid energy-estimation technique for extensible processors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
16	Ganesh Lakshminarayana, Anand Raghunathan, Kamal S. Khouri, Niraj K. Jha, Sujit Dey	Common-case computation: a high-level energy and performance optimization technique.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
16	Stelian Alupoaei, Srinivas Katkoori	Net Clustering Based Constructive and Iterative Improvement Approaches for Macro-Cell Placement.	J. VLSI Signal Process.	2004	DBLP DOI BibTeX RDF	net clustering, macro-cell placement, cluster growth, wirelength optimization, simulated annealing
16	A. Bernstein, M. Burton, Frank Ghenassia	How to bridge the abstraction gap in system level modeling and design.	ICCAD	2004	DBLP DOI BibTeX RDF
16	Michele Favalli	Annotated Bit Flip Fault Model.	DFT	2004	DBLP DOI BibTeX RDF
16	Prabhat Mishra 0001, Arun Kejariwal, Nikil D. Dutt	Synthesis-driven Exploration of Pipelined Embedded Processors.	VLSI Design	2004	DBLP DOI BibTeX RDF
16	Ashwin K. Kumaraswamy, Ahmet T. Erdogan, Indrajit Atluri	Development of Timing Driven IP Design Flow based on Physical Knowledge Synthesis.	IWSOC	2004	DBLP DOI BibTeX RDF
16	Prabhat Mishra 0001, Nikil D. Dutt	A Methodology for Validation of Microprocessors using Equivalence Checking.	MTV	2003	DBLP DOI BibTeX RDF
16	Prithviraj Banerjee, Vikram Saxena, Juan Ramon Uribe, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, Robert Anderson	Making area-performance tradeoffs at the high level using the AccelFPGA compiler for FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF