Search results for "analog"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
27	Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin	Ultra Low Cost Analog BIST Using Spectral Analysis.	VTS	2003	DBLP DOI BibTeX RDF
27	Erik Lauwers, Georges G. E. Gielen	Power estimation methods for analog circuits for architectural exploration of integrated systems.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
27	Geert Van der Plas, Jan Vandenbussche, Georges G. E. Gielen, Willy M. C. Sansen	A layout synthesis methodology for array-type analog blocks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
27	Nam Phamdo, Udar Mittal	A joint source-channel speech coder using hybrid digital-analog (HDA) modulation.	IEEE Trans. Speech Audio Process.	2002	DBLP DOI BibTeX RDF
27	Walter Hartong, Lars Hedrich, Erich Barke	On Discrete Modeling and Model Checking for Nonlinear Analog Systems.	CAV	2002	DBLP DOI BibTeX RDF
27	Ralf Sommer, Irmtraud Rugen-Herzig, Eckhard Hennig, Umberto Gatti, Piero Malcovati, Franco Maloberti, Karsten Einwich, Christoph Clauß, Peter Schwarz, G. Noessing	From System Specification To Layout: Seamless Top-Down Design Methods for Analog and Mixed-Signal Applications.	DATE	2002	DBLP DOI BibTeX RDF
27	Tyson S. Hall, Paul E. Hasler, David V. Anderson	Field-Programmable Analog Arrays: A Floating-Gate Approach.	FPL	2002	DBLP DOI BibTeX RDF
27	G. Mulliken, Farhan Adil, Gert Cauwenberghs, Roman Genov	Delta-sigma algorithmic analog-to-digital conversion.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
27	Albert H. Titus, Anand Gopalan	A differential summing amplifier for analog VLSI systems.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
27	Anthony Chan Carusone, David A. Johns	Analog filter adaptation using a dithered linear search algorithm.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
27	Bernhard Burdiek	The qualitative form of optimum transient test signals for analog circuits derived from control theory methods.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
27	Sule Ozev, Alex Orailoglu	An Integrated Tool for Analog Test Generation and Fault Simulation.	ISQED	2002	DBLP DOI BibTeX RDF
27	Swarup Bhunia, Kaushik Roy 0001	Dynamic Supply Current Testing of Analog Circuits Using Wavelet Transform.	VTS	2002	DBLP DOI BibTeX RDF
27	Zhen Guo, Jacob Savir	Observer-Based Test of Analog Linear Time-Invariant Circuits.	DELTA	2002	DBLP DOI BibTeX RDF
27	Hajime Shibata, Soji Mori, Nobuo Fujii	Automated Design of Analog Circuits Using Cell-Based Structure .	Evolvable Hardware	2002	DBLP DOI BibTeX RDF
27	Florin Balasa	Device-level placement for analog layout: an opportunity for non-slicing topological representations.	ASP-DAC	2001	DBLP DOI BibTeX RDF
27	Sree Ganesan, Ranga Vemuri	Analog-Digital Partitioning for Field-Programmable Mixed Signal Systems.	ARVLSI	2001	DBLP DOI BibTeX RDF
27	Akira Matsuzawa	High Quality Analog CMOS and Mixed Signal LSI Design.	ISQED	2001	DBLP DOI BibTeX RDF
27	Edward Ramsden	The Isppac Family Of Reconfigurable Analog Circuits.	Evolvable Hardware	2001	DBLP DOI BibTeX RDF
27	Pramodchandran N. Variyam, Abhijit Chatterjee	Specification-driven test generation for analog circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
27	Florin Balasa, Koen Lampaert	Symmetry within the sequence-pair representation in the context ofplacement for analog design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
27	Luigi Carro, Adão Antônio de Souza Jr., Marcelo Negreiros, Gabriel Parmegiani Jahn, Denis Teixeira Franco	Non-Linear Components for Mixed Circuits Analog Front-End.	DATE	2000	DBLP DOI BibTeX RDF
27	Piet Wambacq, Petr Dobrovolný, Stéphane Donnay, Marc Engels, Ivo Bolsens	Compact Modeling of Nonlinear Distortion in Analog Communication Circuits.	DATE	2000	DBLP DOI BibTeX RDF
27	Junwei Hou, Abhijit Chatterjee	Analog Transient Concurrent Fault Simulation with Dynamic Fault Grouping.	ICCD	2000	DBLP DOI BibTeX RDF
27	Yasuhiro Ota, Bogdan M. Wilamowski	Analog implementation of pulse-coupled neural networks.	IEEE Trans. Neural Networks	1999	DBLP DOI BibTeX RDF
27	Xiang-Dong Tan, C.-J. Richard Shi	Balanced Multi-Level Multi-Way Partitioning of Large Analog Circuits for Hierarchical Symbolic Analysis.	ASP-DAC	1999	DBLP DOI BibTeX RDF
27	Ricardo Salem Zebulum, Marco Aurélio Cavalcanti Pacheco, Marley M. B. R. Vellasco	Analog Circuits Evolution in Extrinsic and Intrinsic Modes.	ICES	1998	DBLP DOI BibTeX RDF
27	Giorgio Casinovi, Jeen-Mo Yang	Multi-level simulation of large analog systems containing behavioral models.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
27	D. L. Grundy	A computational approach to VLSI analog design.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
27	Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham	Fault simulation of linear analog circuits.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF
27	John G. Harris, Christof Koch, Erik Staats, Jin Luo	Analog hardware for detecting discontinuities in early vision.	Int. J. Comput. Vis.	1990	DBLP DOI BibTeX RDF
26	Jorge Oliveros, Dwight Cabrera, Elkim Roa, Wilhelmus A. M. Van Noije	An improved and automated design tool for the optimization of CMOS OTAs using geometric programming.	SBCCI	2008	DBLP DOI BibTeX RDF	OTA design, analog CAD, analog circuit optimization, design methodologies, geometric programming
26	Sunil Rafeeque, Vinita Vasudevan	A Built-in-Self-Test Scheme for Segmented and Binary Weighted DACs.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	digital to analog converters, nonlinearity test, analog testing, mixed-signal BIST
26	Hui-Chin Tseng, Hsin-Hung Ou, Chi-Sheng Lin, Bin-Da Liu	A low-power rail-to-rail 6-bit flash ADC based on a novel complementary average-value approach.	ISLPED	2004	DBLP DOI BibTeX RDF	CMOS analog circuit, flash analog-to-digital converter, rail-to-rail, low power, comparator
26	Hesam Amir Aslanzadeh, Saeid Mehrmanesh, Mohammad B. Vahidfar, Amin Quasem Safarian, Reza Lotfi	A 1-V 1-mW high-speed class AB operational amplifier for high-speed low power pipelined A/D converters using "Slew Boost" technique.	ISLPED	2003	DBLP DOI BibTeX RDF	CMOS analog circuit, Slew Boost technique, class AB, low power, high speed, operational amplifier, pipelined analog to digital converter, ultra low voltage
26	Iasson Vassiliou, Henry Chang, Alper Demir 0001, Edoardo Charbon, Paolo Miliozzi, Alberto L. Sangiovanni-Vincentelli	A video driver system designed using a top-down, constraint-driven methodology.	ICCAD	1996	DBLP DOI BibTeX RDF	Analog CAD, Video Driver System Chips, Analog Behavioral Modeling, Design Methodologies
25	Geoffrey Ying, Andreas Kuehlmann, Kenneth S. Kundert, Georges G. E. Gielen, Eric Grimme, Martin O'Leary, Sandeep Tare, Warren Wong	Guess, solder, measure, repeat: how do I get my mixed-signal chip right?	DAC	2009	DBLP DOI BibTeX RDF	Verilog-AMS, analog behavioral modeling, low power verification, mixed-signal verification, VHDL, SPICE, functional verification, Verilog, performance verification
25	Rafail Lashevsky, Yohey Sato	Deviation-tolerant floating gate structures as a way to design an on-chip learning neural networks.	Soft Comput.	2002	DBLP DOI BibTeX RDF	?MOS transistor, Analog hardware implementation, Deviation tolerance, Artificial neural networks
25	Sebastian Steinhorst, Lars Hedrich	Model Checking of Analog Systems using an Analog Specification Language.	DATE	2008	DBLP DOI BibTeX RDF
25	Olivier Bournez, Manuel Lameiras Campagnolo, Daniel Silva Graça, Emmanuel Hainry	The General Purpose Analog Computer and Computable Analysis are Two Equivalent Paradigms of Analog Computation.	TAMC	2006	DBLP DOI BibTeX RDF
25	David W. Parent, Eric J. Basham, Shao Ng, Paul B. Weil	An Analog Leaf Cell for Analog Circuit Design.	MSE	2005	DBLP DOI BibTeX RDF
25	Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Michel Renovell, Marcelo Lubaszewski	Testing the Configurable Analog Blocks of Field Programmable Analog Arrays.	ITC	2004	DBLP DOI BibTeX RDF
25	Rosa Rodríguez-Montañés, D. Muñoz, Luz Balado, Joan Figueras	Analog Switches in Programmable Analog Devices: Quiescent Defective Behaviours.	IOLTW	2002	DBLP DOI BibTeX RDF
25	Karim Arabi, Bozena Kaminska, Janusz Rzeszut	A new built-in self-test approach for digital-to-analog and analog-to-digital converters.	ICCAD	1994	DBLP DOI BibTeX RDF
24	Ryan W. Robucci, Leung Kin Chiu, Jordan D. Gray, Justin K. Romberg, Paul E. Hasler, David V. Anderson	Compressive sensing on a CMOS separable transform image sensor.	ICASSP	2008	DBLP DOI BibTeX RDF
24	Martin Hasler, Gernot Kubin	Mixed-domain system representation using Volterra series.	ISCAS	2008	DBLP DOI BibTeX RDF
24	Nathaniel J. August	A Robust and Efficient Pre-Silicon Validation Environment for Mixed-Signal Circuits on Intel's Test Chips.	ISQED	2008	DBLP DOI BibTeX RDF	pre-silicon, validation, mixed-signal
24	Gonzalo Pajares	A Hopfield Neural Network for Image Change Detection.	IEEE Trans. Neural Networks	2006	DBLP DOI BibTeX RDF
24	Amol Y. Deshmukh, Preeti R. Bajaj, Avinash G. Keskar	Hardware Implementation of Fuzzy Controllers-Approach and Constraints.	KES (1)	2006	DBLP DOI BibTeX RDF
24	Peter R. Snoeren, Nico Karssemeijer	Gray Scale Registration of Mammograms Using a Model of Image Acquisition.	IPMI	2003	DBLP DOI BibTeX RDF
24	Liyi Xiao, Bin Li, Yizheng Ye, Guoyong Huang, JinJun Guo, Peng Zhang	A mixed-signal simulator for VHDL-AMS.	ASP-DAC	2001	DBLP DOI BibTeX RDF
24	Junwei Hou, William H. Kao, Abhijit Chatterjee	A novel concurrent fault simulation method for mixed-signal circuits.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
24	Robert W. Brodersen	System-on-a-Chip VLSI - Is It Finally Really Here?	ARVLSI	1999	DBLP DOI BibTeX RDF
24	Gordon W. Roberts	Metrics, techniques and recent developments in mixed-signal testing.	ICCAD	1996	DBLP DOI BibTeX RDF	manufacturing environment, measurement setups, quality, mixed-signal testing, mixed analogue-digital integrated circuits, manufacturing defects, product cost
24	Chen-Yang Pan, Kwang-Ting Cheng	Pseudo-random testing and signature analysis for mixed-signal circuits.	ICCAD	1995	DBLP DOI BibTeX RDF	Signature Analysis, Random Process, Pseudo-Random Testing, Impulse Response
24	Josef Heinhold	Die Anwendung des Analogrechners in der Unternehmensforschung.	Computing	1966	DBLP DOI BibTeX RDF
23	Michael Eick, Martin Strasser, Helmut E. Graeb, Ulf Schlichtmann	Automatic generation of hierarchical placement rules for analog integrated circuits.	ISPD	2010	DBLP DOI BibTeX RDF	hierarchical placement rules, constraints, placement, analog integrated circuits
23	Rob A. Rutenbar	Analog layout synthesis: what's missing?	ISPD	2010	DBLP DOI BibTeX RDF	synthesis, layout, analog
23	Cheng-Wu Lin, Jai-Ming Lin, Chun-Po Huang, Soon-Jyh Chang	Performance-driven analog placement considering boundary constraint.	DAC	2010	DBLP DOI BibTeX RDF	analog placement, boundary constraint, symmetry
23	Jernej Olensek, Árpád Bürmen, Janez Puhan, Tadej Tuma	DESA: a new hybrid global optimization method and its application to analog integrated circuit sizing.	J. Glob. Optim.	2009	DBLP DOI BibTeX RDF	Analog integrated circuit sizing, Optimization, Simulated annealing, Differential evolution
23	Jérôme Durand-Lose	Abstract geometrical computation 3: black holes for classical and analog computing.	Nat. Comput.	2009	DBLP DOI BibTeX RDF	Black hole model, Malament-Hogarth space-time, Hyper-computing, Zeno phenomenon, Analog computation, Arithmetic hierarchy, Abstract geometrical computation
23	Yukiya Miura, Jiro Kato	Adaptive Fault Diagnosis of Analog Circuits by Operation-Region Model and X - Y Zoning Method.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	MOS transistors, Fault diagnosis, Analog circuits, Adaptive test
23	Olga Goussevskaia, Roger Wattenhofer	Complexity of scheduling with analog network coding.	FOWANC	2008	DBLP DOI BibTeX RDF	analog network coding, geometric sinr, physical interference model, scheduling, complexity, np-complete, wireless ad-hoc networks
23	Shukai Duan, Lidan Wang 0001	Circuitry Analog and Synchronization of Hyperchaotic Neuron Model.	ISNN (2)	2008	DBLP DOI BibTeX RDF	Chaotic neuron model, circuitry analog, chaos synchronization, adaptive chaos synchronization
23	Gabriel Oltean, Sorin Hintea, Emilia Sipos	Computational Intelligence in Analog Circuits Design.	KES (3)	2008	DBLP DOI BibTeX RDF	genetic algorithm, optimization, fuzzy sets, neuro-fuzzy systems, analog circuit design
23	Kazuki Akutagawa, Kazuya Machida, Takao Waho	A 3/7-Level Mixed-Mode Algorithmic Analog-to-Digital Converter.	ISMVL	2008	DBLP DOI BibTeX RDF	algorithmic, redundancy, analog-to-digital converter, multiple-valued
23	Shubhankar Basu, Balaji Kommineni, Ranga Vemuri	Variation Aware Spline Center and Range Modeling for Analog Circuit Performance.	ISQED	2008	DBLP DOI BibTeX RDF	Center and Range, Process Variation, Analog, Spline
23	Laurent Gatet, Hélène Tap-Béteille, Daniel Roviras, Francis Gizard	Integrated CMOS Analog Neural Network Ability to Linearize the Distorted Characteristic of HPA Embedded in Satellites.	DELTA	2008	DBLP DOI BibTeX RDF	CMOS Analog Integrated Circuits, Nonlinear Distortion, Predistorsion, Multi-Layer Perceptrons, Neural Network Architecture
23	Daeik D. Kim, Choongyeun Cho, Jonghae Kim	Analog parallelism in ring-based VCOs.	DAC	2008	DBLP DOI BibTeX RDF	analog parallelism, clock period jitter, process-induced variation, ring-based voltage-controlled oscillator, microprocessor, phase-locked loop, phase noise
23	M. A. El-Gamal, M. D. A. Mohamed	Ensembles of Neural Networks for Fault Diagnosis in Analog Circuits.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	fault simulation, boosting, ensemble learning, analog circuits, bagging, fault classification
23	Jiayi Liu, Sheqin Dong, Yuchun Ma, Di Long, Xianlong Hong	Thermal-driven Symmetry Constraint for Analog Layout with CBL Representation.	ASP-DAC	2007	DBLP DOI BibTeX RDF	thermal-optimal placement, thermal-driven symmetry constraint, analog layout, thermal constraint, hot-spot effect, temperature gradient, symmetrical devices, placement process, geometric symmetry, corner block list, thermal model
23	Min Jiang, Zhenkun Yang, Zhaohui Gan	Optimal Components Selection for Analog Active Filters Using Clonal Selection Algorithms.	ICIC (1)	2007	DBLP DOI BibTeX RDF	Analog active filter, Butterworth approximation, Clonal selection algorithms, Components selection
23	Yaser M. A. Khalifa, Badar K. Khan, Faisal Taha	Multi-objective optimization tool for a free structure analog circuits design using genetic algorithms and incorporating parasitics.	GECCO (Companion)	2007	DBLP DOI BibTeX RDF	genetic algorithms, optimization, analog circuits
23	Nuno C. Lourenço, Nuno C. G. Horta	Automatic analog IC layout generation based on a evolutionary computation approach.	GECCO	2007	DBLP DOI BibTeX RDF	analog ICs, layout generation, evolutionary computation
23	Burcu Erkmen, Tülay Yildirim	CSFNN Synapse and Neuron Design Using Current Mode Analog Circuitry.	KES (1)	2007	DBLP DOI BibTeX RDF	Conic Section Function Neural Networks, Current Mode Analog Design, Neuron and Synapse Circuitry
23	Manuel F. M. Barros, Jorge Guilherme, Nuno Horta	GA-SVM feasibility model and optimization kernel applied to analog IC design automation.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	analog integrated circuit synthesis, genetic algorithms, support vector machines
23	Catherine Lai, Ichiro Fujinaga	Metadata data dictionary for analog sound recordings.	JCDL	2006	DBLP DOI BibTeX RDF	analog sound recordings, metadata, digitization, preservation
23	Alessandro Girardi, Sergio Bampi	Power constrained design optimization of analog circuits based on physical gm/ID characteristics.	SBCCI	2006	DBLP DOI BibTeX RDF	simulated annealing, synthesis, analog design
23	Shinichi Kouda, Chikaaki Kodama, Kunihiro Fujiyoshi	Improved method of cell placement with symmetry constraints for analog IC layout design.	ISPD	2006	DBLP DOI BibTeX RDF	symmetry constraints, linear programming, placement, analog circuits, sequence-pair
23	Rob A. Rutenbar	Design automation for analog: the next generation of tool challenges.	ICCAD	2006	DBLP DOI BibTeX RDF	computer-aided design, synthesis, analog, integrated circuits, mixed-signal
23	Ying Wei 0002, Alex Doboli	Systematic development of nonlinear analog circuit macromodels through successive operator composition and nonlinear model decoupling.	DAC	2006	DBLP DOI BibTeX RDF	nonlinear macromodel, structural macromodel, analog circuits
23	Florence Azaïs, Marcelo Lubaszewski, Pascal Nouet, Michel Renovell	A Strategy for Optimal Test Point Insertion in Analog Cascaded Filters.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	testability evaluation, design-for-test, analog and mixed-signal testing
23	Soumendu Bhattacharya, Abhijit Chatterjee	Optimized wafer-probe and assembled package test design for analog circuits.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	Assembled package, co-optimization, test cost minimization, test generation and co-optimization, wafer-probe, simulation, test, prototype, analog and mixed-signal test
23	Catherine Lai, Ichiro Fujinaga, Cynthia A. Leive	Metadata for phonograph records: facilitating new forms of use and access to analog sound recordings.	JCDL	2005	DBLP DOI BibTeX RDF	analog sound recordings, metadata, digitization, preservation
23	Lars A. Schreiner, Markus Olbrich, Erich Barke, Volker Meyer zu Bexten	Routing of analog busses with parasitic symmetry.	ISPD	2005	DBLP DOI BibTeX RDF	analog routing, net bundles, paired nets, virtual terminals, routing, EDA, RF, bus routing, IC-layout
23	Jianjun Hu, Xiwei Zhong, Erik D. Goodman	Open-ended robust design of analog filters using genetic programming.	GECCO	2005	DBLP DOI BibTeX RDF	analog filter synthesis, genetic programming, automated design, robust design, bond graphs
23	Anuradha Agarwal, Glenn Wolfe, Ranga Vemuri	Accuracy driven performance macromodeling of feasible regions during synthesis of analog circuits.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	performance modeling, circuit sizing, analog synthesis
23	Henry H. Y. Chan, Zeljko Zilic	Modeling Layout Effects for Sensitivity-Based Analog Circuit Optimization.	ISQED	2005	DBLP DOI BibTeX RDF	Analog circuit optimization, adjoint analysis, sensitivity analysis, parasitic extraction
23	Ying Wei 0002, Alex Doboli	Systematic development of analog circuit structural macromodels through behavioral model decoupling.	DAC	2005	DBLP DOI BibTeX RDF	structural macromodel, analog circuits
23	Barbara Cannas, Alessandra Fanni, Stefano Manetti, Augusto Montisci, Maria Cristina Piccirilli	Neural network-based analog fault diagnosis using testability analysis.	Neural Comput. Appl.	2004	DBLP DOI BibTeX RDF	Neural networks, Diagnosis, Analog circuits, Testability analysis
23	Carlos Eduardo Savioli, Claudio C. Czendrodi, José Vicente Calvano, Antonio Carneiro de Mesquita Filho	ATPG for fault diagnosis on analog electrical networks using evolutionary techniques.	SBCCI	2004	DBLP DOI BibTeX RDF	genetic algorithms, automatic test pattern generation, fault models, analog and mixed-signal test
23	Hongjoong Shin, Hak-soo Yu, Jacob A. Abraham	LFSR-based BIST for analog circuits using slope detection.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	slope detection, BIST, LFSR, analog testing, mixed-signal testing
23	Zhen Guo	How to reduce aliasing in linear analog testing.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	fault detection, aliasing, analog testing, parametric faults
23	Chih-Jen Yen, Mely Chen Chi, Wen-Yaw Chung, Shing-Hao Lee	A 0.75-mW analog processor IC for wireless biosignal monitor.	ISLPED	2003	DBLP DOI BibTeX RDF	analog processor, biosignal monitor, wireless, IC
23	Jincheol Yoo, Kyusun Choi, Jahan Ghaznavi	CMOS flash analog-to-digital converter for high speed and low voltage applications.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	TIQ comparator, fat tree encoder, flash ADC, analog-to-digital converter, low voltage, high speed
23	Guido Stehr, Helmut E. Graeb, Kurt Antreich	Performance trade-off analysis of analog circuits by normal-boundary intersection.	DAC	2003	DBLP DOI BibTeX RDF	normal-boundary intersection, performance space exploration, topology selection, analog circuits, Pareto optimality, trade-off analysis
23	Soon-Jyh Chang, Chung-Len Lee 0001, Jwu E. Chen	Structural Fault Based Specification Reduction for Testing Analog Circuits.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	specification-based test, analog test, fault-based test, test cost reduction
23	Simon C. Li, Jimmy C. Cha	±0.5V ±1.5V VHF CMOS LV/LP four-quadrant analog multiplier in modified bridged-triode scheme.	ISLPED	2002	DBLP DOI BibTeX RDF	modified bridged-triode scheme (MBTS), analog multiplier
23	Takayuki Sugawara, Yoshikazu Miyanaga, Norinobu Yoshida	A Design of Analog C-Matrix Circuits Used for Signal/Data Processing.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	Signal Processing, Analog Circuit
23	Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita	Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	mixed signal design, shape-based layout, placement, analog design, sequence-pair