Search results for "memories"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
21	Yoshiki Takai, Mamoru Fukuchi, Chihiro Matsui, Reika Kinoshita, Ken Takeuchi	Analysis on Hybrid SSD Configuration with Emerging Non-Volatile Memories Including Quadruple-Level Cell (QLC) NAND Flash Memory and Various Types of Storage Class Memories (SCMs).	IEICE Trans. Electron.	2020	DBLP DOI BibTeX RDF
21	Vamsee Reddy Kommareddy, Baogang Zhang, Fan Yao, Rickard Ewetz, Amro Awad	Are Crossbar Memories Secure? New Security Vulnerabilities in Crossbar Memories.	IEEE Comput. Archit. Lett.	2019	DBLP DOI BibTeX RDF
21	Chihiro Matsui, Ken Takeuchi	Design of heterogeneously-integrated memory system with storage class memories and NAND flash memories.	ASP-DAC	2019	DBLP DOI BibTeX RDF
21	Pierre G. Gianferrara, Marlieke van Kesteren, Martijn Meeter	Reinstatement of Old Memories and Integration with New Memories.	CogSci	2019	DBLP BibTeX RDF
21	Asil Kaan Bozcuoglu	Fast Robot Learning using Prospection and Experimental Knowledge : A Cognitive Approach with Narrative-Enabled Episodic Memories and Symbolic Knowledge (Schnelles Roboterlernen durch Prospektion und experimentelles Wissen : ein kognitiver Ansatz mit Narrative-Enabled Episodic Memories und symbolischem Wissen)		2019	RDF
21	Rachel Zuanon, Melissa Ramos da Silva Oliveira, Haroldo Gallo, Cláudio Lima Ferreira	Drawing Memories: Intersections Between the Sites of Memory and the Memories of Places.	HCI (17)	2018	DBLP DOI BibTeX RDF
21	Hiroki Shirakawa, Keita Yamaguchi, Masaaki Araidai, Katsumasa Kamiya, Kenji Shiraishi	Possibility of Metal-Oxide-Nitride-Oxide-Semiconductor Memories for Long Lifespan Archive Memories.	IEICE Trans. Electron.	2017	DBLP DOI BibTeX RDF
21	Felipe L. Teixeira, Maurício L. Pilla, André Rauber Du Bois, Daniel Mossé	Impact of Version Management for Transactional Memories on Phase-Change Memories.	SBAC-PAD (Workshops)	2017	DBLP DOI BibTeX RDF
21	Tetsuo Endoh, Hiroki Koike, Shoji Ikeda, Takahiro Hanyu, Hideo Ohno	An Overview of Nonvolatile Emerging Memories - Spintronics for Working Memories.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2016	DBLP DOI BibTeX RDF
21	Fabrice Guet, Luca Santinelli, Jérôme Morio	Probabilistic analysis of cache memories and cache memories impacts on multi-core embedded systems.	SIES	2016	DBLP DOI BibTeX RDF
21	Wooheon Kang, Hyungjun Cho, Joohwan Lee, Sungho Kang	A BIRA for Memories With an Optimal Repair Rate Using Spare Memories for Area Reduction.	IEEE Trans. Very Large Scale Integr. Syst.	2014	DBLP DOI BibTeX RDF
21	Nathan Burles, Simon O'Keefe, James Austin, Stephen Hobson	ENAMeL: A Language for Binary Correlation Matrix Memories - Reducing the Memory Constraints of Matrix Memories.	Neural Process. Lett.	2014	DBLP DOI BibTeX RDF
21	Hsin-Jung Yang, Kermin Fleming, Michael Adler, Joel S. Emer	LEAP Shared Memories: Automating the Construction of FPGA Coherent Memories.	FCCM	2014	DBLP DOI BibTeX RDF
21	Gyula O. H. Katona	Memories on Shadows and Shadows of Memories.	The Mathematics of Paul Erdős II	2013	DBLP DOI BibTeX RDF
21	Peter Stephan, Markus Eich, Jörg Neidig, Martin Rosjat, Roberto Hengst	Applying Digital Product Memories in Industrial Production.	SemProM	2013	DBLP DOI BibTeX RDF
21	Marc Seißler, Peter Stephan, Jochen Schlick, Ines Dahmann	DPM Mapper: A Concept to Bridge the Gap Between XML-Based Digital Product Memories and Their Binary Representation.	SemProM	2013	DBLP DOI BibTeX RDF
21	Gerrit Kahl, Carsten Magerkurth, Jörg Preißinger, Patrick Gebhard, Benjamin Weyl	Enhancement of Consumer Support in Retail Scenarios by Utilization of Semantic Product Memories.	SemProM	2013	DBLP DOI BibTeX RDF
21	Jörg Neidig	Using Basic RFID-Based Digital Product Memories for Protection against Counterfeit Goods in Manufacturing Plants.	SemProM	2013	DBLP DOI BibTeX RDF
21	Jens Haupert, Michael Schneider 0003	The Object Memory Server for Semantic Product Memories.	SemProM	2013	DBLP DOI BibTeX RDF
21	Bruno Kiesel, Jörg Neidig	The Block Interface: Accessing Digital Product Memories.	SemProM	2013	DBLP DOI BibTeX RDF
21	Michael Schmitz 0001, Boris Brandherm, Jörg Neidig, Stefanie Schachtl, Matthias Schuster	Interaction Modalities for Digital Product Memories.	SemProM	2013	DBLP DOI BibTeX RDF
21	Johannes Lemburg, Dennis Mronga, Achint Aggarwal, Jose de Gea Fernandez, Marc Ronthaler, Frank Kirchner	A Robotic Platform for Building and Exploiting Digital Product Memories.	SemProM	2013	DBLP DOI BibTeX RDF
21	Gerrit Meixner, Alexander Kröner, Gerrit Kahl	A Summary of End-User Feedback on Digital Product Memories.	SemProM	2013	DBLP DOI BibTeX RDF
21	Sven Horn, Barbara Schennerlein, Anne Pförtner, Thorbjørn Hansen	Distributed Digital Product Memories.	SemProM	2013	DBLP DOI BibTeX RDF
21	Alexander Kröner, Jens Haupert, Jose de Gea Fernandez, Rainer Steffen, Christian Kleegrewe, Martin Schneider	Supporting Interaction with Digital Product Memories.	SemProM	2013	DBLP DOI BibTeX RDF
21	Gerd Herzog, Alexander Kröner	Towards an Integrated Framework for Semantic Product Memories.	SemProM	2013	DBLP DOI BibTeX RDF
21	Patrick Gebhard	Controlling Interaction with Digital Product Memories.	SemProM	2013	DBLP DOI BibTeX RDF
21	Jörg Neidig	Hardware Requirements for Digital Product Memories.	SemProM	2013	DBLP DOI BibTeX RDF
21	Susanne Diekelmann, Ines Wilhelm, Ullrich Wagner, Jan Born	Elevated Cortisol at Retrieval Suppresses False Memories in Parallel with Correct Memories.	J. Cogn. Neurosci.	2011	DBLP DOI BibTeX RDF
21	Michiko Sakaki, Kazuhisa Niki, Mara Mather	Updating Existing Emotional Memories Involves the Frontopolar/Orbito-frontal Cortex in Ways that Acquiring New Emotional Memories Does Not.	J. Cogn. Neurosci.	2011	DBLP DOI BibTeX RDF
21	Nathalie Basselin, Alexander Kröner	From Personal Memories to Sharable Memories.	LWA	2006	DBLP BibTeX RDF
21	Jeannette Allis Bastian, Gregory Colati, Elizabeth Yakel, Kelly S. Drake	Digital memories/mediated memories: Influences on the creation of archival and cultural web sites.	ASIST	2004	DBLP DOI BibTeX RDF
19	Roberto Antonio Vázquez Espinoza de los Monteros, Juan Humberto Sossa Azuela	A Bidirectional Hetero-Associative Memory for True-Color Patterns.	Neural Process. Lett.	2008	DBLP DOI BibTeX RDF	Pattern recognition, Dynamical synapses, Bidirectional associative memories
19	Marc González 0001, Nikola Vujic, Xavier Martorell, Eduard Ayguadé, Alexandre E. Eichenberger, Tong Chen 0001, Zehra Sura, Tao Zhang, Kevin O'Brien, Kathryn M. O'Brien	Hybrid access-specific software cache techniques for the cell BE architecture.	PACT	2008	DBLP DOI BibTeX RDF	memory classification, OpenMP, compiler optimizations, local memories, software cache
19	Jiang Lin, Hongzhong Zheng, Zhichun Zhu, Eugene Gorbatov, Howard David, Zhao Zhang 0010	Software thermal management of dram memory for multicore systems.	SIGMETRICS	2008	DBLP DOI BibTeX RDF	thermal management, DRAM memories
19	Rui M. Jesus, Ricardo J. Dias, Rute Frias, Arnaldo J. Abrantes, Nuno Correia 0001	Memoria mobile: sharing pictures of a point of interest.	AVI	2008	DBLP DOI BibTeX RDF	multimedia information retrieval, mobile user interfaces, personal memories
19	Gerasimos G. Rigatos	Stochastic Processes in Machine Intelligence: Neural Structures Based on the Model of the Quantum Harmonic Oscillator.	ICQNM	2008	DBLP DOI BibTeX RDF	quantum harmonic oscillator, Schr¨odinger’s equation, Langevin’s equation, quantum associative memories, diffusion, attractors, Wiener process
19	Liadh Kelly	Context and linking in retrieval from personal digital archives.	SIGIR	2008	DBLP DOI BibTeX RDF	human digital memories, personal information management, context-based retrieval
19	Ricardo J. Dias, Rui M. Jesus, Rute Frias, Nuno Correia 0001	Mobile interface of the memoria project.	SIGIR	2007	DBLP DOI BibTeX RDF	multimedia information retrieval, mobile user interfaces, personal memories
19	Seungwon Yang, Ben Congleton, George Luc, Manuel A. Pérez-Quiñones, Edward A. Fox	Demonstrating the use of a SenseCam in two domains.	JCDL	2006	DBLP DOI BibTeX RDF	MyLifeBits, ubiquitous computing, personal memories
19	Xavier Vera, Jaume Abella 0001, Josep Llosa, Antonio González 0001	An accurate cost model for guiding data locality transformations.	ACM Trans. Program. Lang. Syst.	2005	DBLP DOI BibTeX RDF	genetic algorithms, Cache memories, tiling, padding
19	Michimune Kohno, Jun Rekimoto	Searching common experience: a social communication tool based on mobile ad-hoc networking.	Mobile HCI	2005	DBLP DOI BibTeX RDF	ad hoc computing, co-locate communication, common memories, synchronized shutters, social networking, photo sharing
19	Prassanna Sithambaram, Alberto Macii, Enrico Macii	Exploring the impact of architectural parameters on energy efficiency of application-specific block-enabled SRAMs.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	DBL, DWL, partitioning, embedded, memories, SRAM, application-specific
19	Lotfi Admane	A generic model of corporate memory: application to the industrial systems.	K-CAP	2005	DBLP DOI BibTeX RDF	ReCaRo, meta-model, corporate memories, re-use
19	Luigi Dilillo, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian	Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies.	DAC	2005	DBLP DOI BibTeX RDF	SRAM memories, VDSM technologies, core-cell, test, march test, dynamic faults, defect analysis
19	Xavier Vera, Nerina Bermudo, Josep Llosa, Antonio González 0001	A fast and accurate framework to analyze and optimize cache memory behavior.	ACM Trans. Program. Lang. Syst.	2004	DBLP DOI BibTeX RDF	optimization, sampling, Cache memories
19	Max H. Garzon, Derrel Blain, Kiranchand V. Bobba, Andrew Neel, Michael West	Self-Assembly of DNA-like Structures In Silico.	Genet. Program. Evolvable Mach.	2003	DBLP DOI BibTeX RDF	online genetic algorithms, DNA-based associative memories, efficiency of DNA computing, reaction kinetics in DNA-based computational protocols, Hamiltonian path problem
19	Oleg Bessonov, Dominique Fougère, Bernard Roux	Analysis of Architecture and Design of Linear Algebra Kernels for Superscalar Processors.	PaCT	2003	DBLP DOI BibTeX RDF	linear algebra kernels, LINPACK benchmark, performance measurements, instruction level parallelism, cache memories, microarchitecture, out-of-order processors
19	Zhigang Hu, Stefanos Kaxiras, Margaret Martonosi	Let caches decay: reducing leakage energy via exploitation of cache generational behavior.	ACM Trans. Comput. Syst.	2002	DBLP DOI BibTeX RDF	generational behavior, Cache memories, leakage power, cache decay
19	Mahmut T. Kandemir, J. Ramanujam, Alok N. Choudhary	Exploiting shared scratch pad memory space in embedded multiprocessor systems.	DAC	2002	DBLP DOI BibTeX RDF	data tiles, memories, compiler optimizations, energy consumption, access patterns, scratch pad, embedded multiprocessors
19	Wieslaw Citko, Andrzej Luksza, Wieslaw Sienko	Chaos Generators for CDMA Communication Using Neural Networks.	IJCNN (5)	2000	DBLP DOI BibTeX RDF	Chaotic associative memories, Chaos generators, Chaos-based communication systems
19	Mirjam Minor, Alexandre Hanft	The Life Cycle of Test Cases in a CBR System.	EWCBR	2000	DBLP DOI BibTeX RDF	knowledge acquisition, maintenance, Case-based reasoning, corporate memories
19	Alexis Vartanian, Jean-Luc Béchennec, Nathalie Drach-Temam	Two Schemes to Improve the Performance of a Sort-Last 3D Parallel Rendering Machine with Texture Caches.	Euro-Par	1999	DBLP DOI BibTeX RDF	texture mapping, Cache memories, parallel rendering, multiprocessing, application specific architecture
19	Jürgen Teich, Tobias Blickle, Lothar Thiele	An evolutionary approach to system-level synthesis.	CODES	1997	DBLP DOI BibTeX RDF	architecture selection, cost constraints, graph-based mapping model, heterogeneous hardware/software architecture, optimal mapping, performance constraints, task-level specification mapping, video-codec implementations, genetic algorithms, scheduling, memories, ASICs, design space exploration, allocation, optimization problem, binding, buses, system-level synthesis, evolutionary approach, algorithm mapping, general-purpose processors, dedicated processors
19	Frédéric Pétrot, Denis Hommais, Alain Greiner	Cycle precise core based hardware/software system simulation with predictable event propagation.	EUROMICRO	1997	DBLP DOI BibTeX RDF	hardware software system simulation, predictable event propagation, cycle precise core based system simulator, digital embedded systems, Mealy signals, combinational signals, MIPS R3000, microprocessor core, PI-Bus, Pentium 120, communication, graph, C, high level synthesis, memories, directed graph, FSM, topological sort, compile-time, communicating finite state machines
19	José V. Busquets-Mataix, Juan José Serrano, Rafael Ors, Pedro J. Gil, Andy J. Wellings	Using harmonic task-sets to increase the schedulable utilization of cache-based preemptive real-time systems.	RTCSA	1996	DBLP DOI BibTeX RDF	harmonic task-sets, schedulable utilization, preemptive real-time systems, better performance, cache-related preemption cost, Response Time schedulability Analysis, real-time systems, cache memories, worst-case execution time, schedulability analysis
19	Injong Rhee	Optimizing a FIFO, scalable spin lock using consistent memory.	RTSS	1996	DBLP DOI BibTeX RDF	FIFO optimization, scalable spin lock, consistent memory, FIFO queue based scalable spin lock, non atomic read, atomic swap operation, timing guarantee, scalable mutual exclusion problem, NUMA architectures, FSSL algorithm, write operations, non atomic memory operations, weakly consistent memories, multiprocessors, shared memory systems, real time applications, atomic operations
19	Christian Piguet, Thierry Schneider, Jean-Marc Masgonty, Claude Arm, Serge Durand, M. Stegers	Low-Power Embedded Microprocessor Design.	EUROMICRO	1996	DBLP DOI BibTeX RDF	low-power embedded microprocessor design, low-power RISC-like architectures, gated clock techniques, power savings, microprocessor chips, CMOS technology, hierarchical memories, clock cycles
19	Antonio J. Acosta 0001, Manuel J. Bellido, Manuel Valencia-Barrero, Angel Barriga, Raúl Jiménez, José L. Huertas	New CMOS VLSI linear self-timed architectures.	ASYNC	1995	DBLP DOI BibTeX RDF	semiconductor storage, CMOS VLSI linear self-timed architectures, digital signal processor circuits, self-timed techniques, synchronous VLSI circuits, FIFO memories, VLSI, asynchronous circuits, asynchronous circuits, digital signal processing chips, CMOS memory circuits, hardware resources
19	Jelica Protic, Milo Tomasevic, Veljko M. Milutinovic	A survey of distributed shared memory systems.	HICSS (1)	1995	DBLP DOI BibTeX RDF	shared memory programming paradigm, physically distributed memories, classification taxonomy, classification criteria, DSM mechanism, hybrid DSM implementations, distributed systems, parallel programming, shared memory multiprocessors, shared memory systems, distributed memory systems, distributed shared memory systems, DSM systems
19	David M. Koppelman	Reducing PE/Memory Traffic in Multiprocessors by the Difference Coding of Memory Addresses.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	memory traffic, difference coding, memory addresses, shared memory parallel computer, trace-drivensimulation, traffic volume, lower cost, lower latency network, networklatency, virtual machines, multiprocessors, message passing, multiprocessor interconnection networks, memories, shared memory systems, storage management, buffer storage, processing elements, coherent cache
19	Isaac D. Scherson	Orthogonal Graphs for the Construction of a Class of Interconnection Networks.	IEEE Trans. Parallel Distributed Syst.	1991	DBLP DOI BibTeX RDF	multidimensional access memories, graph theoretical representation, orthogonal binary vectors, link modes, node covering problem, binary m-cube, spanning-bus meshes, orthogonal shared memorymultiprocessing systems, interconnection networks, graph theory, connectivity, placement, bipartite graphs, multiprocessor interconnectionnetworks
18	Thomas Wennekers	On the Natural Hierarchical Composition of Cliques in Cell Assemblies.	Cogn. Comput.	2009	DBLP DOI BibTeX RDF	Clique codes, Formal concept analysis, Associative memory, Bio-inspired computing, Cell assemblies
18	Shu Li, Tong Zhang 0002	Improving multi-level NAND flash memory storage reliability using concatenated TCM-BCH coding.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	fault-tolerance, nand flash, tcm
18	Hassan A. Salamy, J. Ramanujam	A Framework for Task Scheduling and Memory Partitioning for Multi-Processor System-on-Chip.	HiPEAC	2009	DBLP DOI BibTeX RDF
18	Ping Zhou, Bo Zhao 0007, Jun Yang 0002, Youtao Zhang	A durable and energy efficient main memory using phase change memory technology.	ISCA	2009	DBLP DOI BibTeX RDF	low power, phase change memory, endurance
18	Lushan Liu, Pradeep Nagaraj, Shambhu J. Upadhyaya, Ramalingam Sridhar	Defect Analysis and Defect Tolerant Design of Multi-port SRAMs.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Multi-port SRAMs, Defect/fault tolerant design, Defect analysis
18	Hiroshige Hayashizaki, Yutaka Sugawara, Mary Inaba, Kei Hiraki	MCAMP: communication optimization on massively parallel machines with hierarchical scratch-pad memory.	PACT	2008	DBLP DOI BibTeX RDF	GRAPE-DR, copy candidates, scratch-pad memory management, memory hierarchy, massively parallel architecture
18	Liadh Kelly, Yi Chen 0017, Marguerite Fuller, Gareth J. F. Jones	A study of remembered context for information access from personal digital archives.	IIiX	2008	DBLP DOI BibTeX RDF
18	Taewhan Kim, Jungeun Kim	Integration of Code Scheduling, Memory Allocation, and Array Binding for Memory-Access Optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
18	Gary Gréwal, Stelian Coros, Dilip K. Banerji, Andrew Morton	Assigning data to dual memory banks in DSPs with a genetic algorithm using a repair heuristic.	Appl. Intell.	2007	DBLP DOI BibTeX RDF	Memory assignment, Repair method, Genetic algorithm, Multi-Objective optimization, Embedded processors
18	Gonzalo Urcid, Gerhard X. Ritter	Noise Masking for Pattern Recall Using a Single Lattice Matrix Associative Memory.	Computational Intelligence Based on Lattice Theory	2007	DBLP DOI BibTeX RDF
18	Minako Kubo, Akihiko Kodama, Etsushi Takaishi, Rikio Chiba, Keita Watanabe, Michiaki Yasumura	Interactive Design of Memory Sharing Applications for Families.	HCI (4)	2007	DBLP DOI BibTeX RDF	application platform, memory, home, ubiquitous interface
18	Johan Ditmar, Steve McKeever	Array Synthesis in SystemC Hardware Compilation.	FPL	2007	DBLP DOI BibTeX RDF
18	Rosanna Bova, Hye-Young Paik, Salima Hassas, Salima Benbernou, Boualem Benatallah	WS-Advisor: A Task Memory for Service Composition Frameworks.	ICCCN	2007	DBLP DOI BibTeX RDF
18	Irith Pomeranz, Sudhakar M. Reddy	Semi-Concurrent On-Line Testing of Transition Faults Through Output Response Comparison of Identical Circuits.	DFT	2007	DBLP DOI BibTeX RDF
18	Koichiro Yamauchi 0001, Masayoshi Sato	Incremental Learning of Spatio-temporal Patterns with Model Selection.	ICANN (1)	2007	DBLP DOI BibTeX RDF	RBF, model selection, incremental learning, spatio-temporal patterns
18	Takashi Saeki, Tsutomu Miki	Effectiveness of Scale Free Network to the Performance Improvement of a Morphological Associative Memory without a Kernel Image.	ICONIP (1)	2007	DBLP DOI BibTeX RDF	recall rate, scale free, Morphological associative memory
18	Aaron J. Gruber, Peter Dayan, Boris S. Gutkin, Sara A. Solla	Dopamine modulation in the basal ganglia locks the gate to working memory.	J. Comput. Neurosci.	2006	DBLP DOI BibTeX RDF	Spiny neuron, Phasic release, Attention, Salience
18	Eero Aho, Jarno Vanne, Timo D. Hämäläinen	Parallel Memory Implementation for Arbitrary Stride Accesses.	ICSAMOS	2006	DBLP DOI BibTeX RDF
18	Tsu-Wei Tseng, Jin-Fu Li 0001, Da-Ming Chang	A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap.	DATE	2006	DBLP DOI BibTeX RDF
18	Dionisios N. Pnevmatikatos, Aggelos Arelakis	Variable-Length Hashing for Exact Pattern Matching.	FPL	2006	DBLP DOI BibTeX RDF
18	Kiranchand V. Bobba, Andrew Neel, Vinhthuy T. Phan, Max H. Garzon	"Reasoning" and "Talking" DNA: Can DNA Understand English?	DNA	2006	DBLP DOI BibTeX RDF	Semantic analysis and information retrieval, DNA chips and microarrays, sensitivy analysis, data classification and discrimination, question answering
18	Peter Muhmenthaler	New on-Chip DFT and ATE Features for Efficient Embedded Memory Test.	MTDT	2006	DBLP DOI BibTeX RDF
18	Ilie I. Luican, Hongwei Zhu 0001, Florin Balasa	Formal model of data reuse analysis for hierarchical memory organizations.	ICCAD	2006	DBLP DOI BibTeX RDF
18	Anders Hall, Dragan Bosevski, Reinell Larkin	Blogging by the dead.	NordiCHI	2006	DBLP DOI BibTeX RDF	ubiquitous computing, mobile, GIS, social computing
18	Yu-Jen Huang, Da-Ming Chang, Jin-Fu Li 0001	A Built-In Redundancy-Analysis Scheme for Self-Repairable RAMs with Two-Level Redundancy.	DFT	2006	DBLP DOI BibTeX RDF
18	Ozcan Ozturk 0001, Mahmut T. Kandemir	Data Replication in Banked DRAMs for Reducing Energy Consumption.	ISQED	2006	DBLP DOI BibTeX RDF
18	Shibaji Banerjee, Dipanwita Roy Chowdhury	Built-In Self-Test for Flash Memory Embedded in SoC.	DELTA	2006	DBLP DOI BibTeX RDF
18	Jin-Fu Li 0001, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu	A built-in self-repair design for RAMs with 2-D redundancy.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
18	Michael Nicolaidis, Lorena Anghel, Nadir Achouri	Memory Defect Tolerance Architectures for Nanotechnologies.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	word repair, nanotechnologies, BISR, memory repair, high defect densities
18	Guilin Chen, Guangyu Chen, Ozcan Ozturk 0001, Mahmut T. Kandemir	Exploiting Inter-Processor Data Sharing for Improving Behavior of Multi-Processor SoCs.	ISVLSI	2005	DBLP DOI BibTeX RDF
18	Lars Wehmeyer, Peter Marwedel	Influence of Memory Hierarchies on Predictability for Time Constrained Embedded Software.	DATE	2005	DBLP DOI BibTeX RDF
18	Wolfgang Heenes, Rolf Hoffmann, Sebastian Kanthak	FPGA Implementations of the Massively Parallel GCA Model.	IPDPS	2005	DBLP DOI BibTeX RDF
18	Yusei Tsuboi, Zuwairie Ibrahim, Osamu Ono	Semantic Model for Circular DNA-Based Memory.	WSTST	2005	DBLP DOI BibTeX RDF
18	Jungeun Kim, Taewhan Kim	Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design.	DAC	2005	DBLP DOI BibTeX RDF	scheduling, binding, memory access
18	Kanad Chakraborty	Testing and Reliability Techniques for High-Bandwidth Embedded RAMs.	J. Electron. Test.	2004	DBLP DOI BibTeX RDF	multiport RAM, BIST (built-in self-test), BISR (built-in self-repair), column-multiplexed addressing, fault tolerance, reliability, bandwidth
18	Jean Michel Daga, Caroline Papaix, Marylene Combe, Emmanuel Racape, Vincent Sialelli	Embedded EEPROM Speed Optimization Using System Power Supply Resources.	PATMOS	2004	DBLP DOI BibTeX RDF
18	Armin Wellig, Julien Zory, Norbert Wehn	Energy- and Area-Efficient Deinterleaving Architecture for High-Throughput Wireless Applications.	PATMOS	2004	DBLP DOI BibTeX RDF
18	Saman Adham, Benoit Nadeau-Dostie	A BIST Algorithm for Bit/Group Write Enable Faults in SRAMs.	MTDT	2004	DBLP DOI BibTeX RDF