Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
19 | Tamio Hoshino |
UDL/I version Two: A New Horizon of HDL Standards. |
CHDL |
1993 |
DBLP BibTeX RDF |
|
19 | Felice Balarin, Gary York |
Verilog HDL Modeling Styles for Formal Verification. |
CHDL |
1993 |
DBLP BibTeX RDF |
|
19 | Gustavo R. Alves, Manuel G. Gericota, José L. Ramalho, José Manuel Martins Ferreira |
An HDL approach to board-level BIST. |
EURO-DAC |
1993 |
DBLP DOI BibTeX RDF |
|
19 | Frank Buijs |
ALU synthesis from HDL descriptions to optimized multi-level logic. |
EURO-DAC |
1992 |
DBLP DOI BibTeX RDF |
|
19 | Timothy Kam, P. A. Subrahmanyam |
Comparing Layouts with HDL Models: A Formal Verification Technique. |
ICCD |
1992 |
DBLP DOI BibTeX RDF |
|
19 | Ryszard F. Gajda, Miroslaw Thor, Marek Tudruj |
Enhancing a control graph based HDL for performance evaluation of simulated architectures. |
Microprocessing and Microprogramming |
1990 |
DBLP DOI BibTeX RDF |
|
19 | Daniel Fischer, Yossi Levhari, Gadi Singer |
NETHDL: abstraction of schematics to high-level HDL. |
EURO-DAC |
1990 |
DBLP DOI BibTeX RDF |
|
19 | Auli Reinikka, Antti Auer, Ari Okkonen |
Automatic synthesis of structural HDL descriptions from graphic specification of embedded asics. |
Microprocessing and Microprogramming |
1989 |
DBLP DOI BibTeX RDF |
|
19 | Sumit Ghosh |
Using Ada as an HDL. |
IEEE Des. Test |
1988 |
DBLP DOI BibTeX RDF |
|
19 | James B. Rawlings |
VHSIC HDL. |
DAC |
1982 |
DBLP DOI BibTeX RDF |
|
19 | Sajjan G. Shiva |
Combinational logic synthesis from an HDL description. |
DAC |
1980 |
DBLP DOI BibTeX RDF |
|
10 | Brahim Al Farisi, Karel Bruneel, Harald Devos, Dirk Stroobandt |
Automatic tool flow for shift-register-LUT reconfiguration: making run-time reconfiguration fast and easy (abstract only). |
FPGA |
2010 |
DBLP DOI BibTeX RDF |
parameterizable configurations, tmap, fpga, reconfigurable computing, run-time reconfiguration, srl, icap |
10 | Nicola Bombieri, Franco Fummi, Graziano Pravadelli |
Abstraction of RTL IPs into embedded software. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
RTL IP reuse, embedded software generation |
10 | ByongChan Lim, Jaeha Kim, Mark A. Horowitz |
An efficient test vector generation for checking analog/mixed-signal functional models. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
linear abstraction, validation, equivalence checking, verilog, functional model, test vector, mixed-signal circuits |
10 | Petr Kobierský, Jan Korenek, Libor Polcak |
Packet header analysis and field extraction for multigigabit networks. |
DDECS |
2009 |
DBLP DOI BibTeX RDF |
|
10 | Per Karlström, Dake Liu |
NoGAP: A Micro Architecture Construction Framework. |
SAMOS |
2009 |
DBLP DOI BibTeX RDF |
|
10 | Warren A. Hunt Jr., Sol Swords |
Centaur Technology Media Unit Verification. |
CAV |
2009 |
DBLP DOI BibTeX RDF |
|
10 | Stephen Jang, Dennis Wu, Mark Jarvin, Billy Chan, Kevin Chung, Alan Mishchenko, Robert K. Brayton |
SmartOpt: an industrial strength framework for logic synthesis. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
abc, blif, edge flow, smartopt, fpga, interface, technology mapping |
10 | Junguk Cho, Shahnam Mirzaei, Jason Oberg, Ryan Kastner |
Fpga-based face detection system using Haar classifiers. |
FPGA |
2009 |
DBLP DOI BibTeX RDF |
haar classifier, fpga, image processing, real-time, architecture, face detection, adaboost |
10 | Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang |
A PD-based methodology to enhance efficiency in testbenches with random stimulation. |
SBCCI |
2009 |
DBLP DOI BibTeX RDF |
parameter domains, system-on-chip, design methodologies, functional verification, coverage analysis |
10 | Jaeyoung Yi, Karam Park, Joonseok Park, Won Woo Ro |
Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm. |
ARC |
2009 |
DBLP DOI BibTeX RDF |
Block Cipher Algorithm, Field Programmable Gate Arrays (FPGA), Cryptography, SEED |
10 | Jack Whitham, Neil C. Audsley, Martin Schoeberl |
Using hardware methods to improve time-predictable performance in real-time Java systems. |
JTRES |
2009 |
DBLP DOI BibTeX RDF |
|
10 | Balaji V. Iyer, Thomas M. Conte |
On power and energy trends of IEEE 802.11n PHY. |
MSWiM |
2009 |
DBLP DOI BibTeX RDF |
power and energy characterization, IEEE 802.11n |
10 | Gongyu Wang, Greg Stitt, Herman Lam, Alan D. George |
A framework for core-level modeling and design of reconfigurable computing algorithms. |
HPRCTA@SC |
2009 |
DBLP DOI BibTeX RDF |
|
10 | Zhi Guo, Walid A. Najjar, Betul Buyukkurt |
Efficient hardware code generation for FPGAs. |
ACM Trans. Archit. Code Optim. |
2008 |
DBLP DOI BibTeX RDF |
FPGA, high-level synthesis, VHDL, Reconfigurable computing, data reuse |
10 | Bingfeng Mei, Bjorn De Sutter, Tom Vander Aa, M. Wouters, Andreas Kanstein, Steven Dupont |
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder. |
J. Signal Process. Syst. |
2008 |
DBLP DOI BibTeX RDF |
H.264/AVC decoder, FPGA, multimedia, embedded system, reconfigurable architecture, VLIW |
10 | Chun-Lung Hsu, Yu-Sheng Huang |
A Fast-Deblocking Boundary-strength Based Architecture Design of Deblocking Filter in H.264/AVC Applications. |
J. Signal Process. Syst. |
2008 |
DBLP DOI BibTeX RDF |
FDBS, H.264/AVC, PSNR, bit-rate, deblocking filter |
10 | Kuo-Kai Shyu, Ming-Huan Lee, Yu-Te Wu, Po-Lei Lee |
Implementation of Pipelined FastICA on FPGA for Real-Time Blind Source Separation. |
IEEE Trans. Neural Networks |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Bernhard Peischl, Naveed Riaz, Franz Wotawa |
Advances in Automated Source-Level Debugging of Verilog Designs. |
New Challenges in Applied Intelligence Technologies |
2008 |
DBLP DOI BibTeX RDF |
debugging of hardware designs, multiple testcases, model-based diagnosis, software debugging |
10 | Yazmín Maldonado, Oscar Montiel, Roberto Sepúlveda, Oscar Castillo 0001 |
Design and Simulation of the Fuzzification Stage through the Xilinx System Generator. |
Soft Computing for Hybrid Intelligent Systems |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Christian Haufe, Frank Rogin |
Ad-Hoc Translations to Close Verilog Semantics Gap. |
DDECS |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Jaume Joven, Oriol Font-Bach, David Castells-Rufas, Ricardo Martínez, Lluís Terés, Jordi Carrabina |
xENoC - An eXperimental Network-On-Chip Environment for Parallel Distributed Computing on NoC-based MPSoC Architectures. |
PDP |
2008 |
DBLP DOI BibTeX RDF |
NoC-based MPSoCs, Message Passing Interface, Distributed Programming, Design Tools and Techniques |
10 | Topon Kumar Paul, Ken Ueno, Koichiro Iwata, Toshio Hayashi, Nobuyoshi Honda |
Genetic Algorithm Based Methods for Identification of Health Risk Factors Aimed at Preventing Metabolic Syndrome. |
SEAL |
2008 |
DBLP DOI BibTeX RDF |
unbalanced data, metabolic syndrome, RPMBGA+, AUC balanced, classification, Feature selection, fitness evaluation |
10 | Mohammad Reza Kakoee, Mohammad Riazati, Siamak Mohammadi |
Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification. |
DSD |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Mehdi Dehbashi, Vahid Lari, Seyed Ghassem Miremadi, Mohammad Shokrollah-Shirazi |
Fault Effects in FlexRay-Based Networks with Hybrid Topology. |
ARES |
2008 |
DBLP DOI BibTeX RDF |
FlexRay Protocol, Fault Injection, Error Propagation, Distributed Embedded Systems, Dependability Evaluation |
10 | Norio Yamagaki, Reetinder P. S. Sidhu, Satoshi Kamiya |
High-speed regular expression matching engine using multi-character NFA. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Ruchika Verma, Ali Akoglu |
A coarse grained and hybrid reconfigurable architecture with flexible NoC router for variable block size motion estimation. |
IPDPS |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Miaoqing Huang, Kris Gaj, Soonhak Kwon, Tarek A. El-Ghazawi |
An Optimized Hardware Architecture for the Montgomery Multiplication Algorithm. |
Public Key Cryptography |
2008 |
DBLP DOI BibTeX RDF |
MWR2MM Algorithm, Field Programmable Gate Arrays, Montgomery Multiplication |
10 | Armando Astarloa, Unai Bidarte, Jaime Jimenez, Jesús Lázaro 0001, Iñigo Martínez de Alegría |
Secure Ethernet Point-to-Point Links for Autonomous Electronic Ballot Boxes. |
ATC |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Kok-Leong Chang, Yao Zhu, Bah-Hwee Gwee |
De-synchronization of a point-of-sales digital-logic controller. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
10 | J. Divyasree, H. Rajashekar, Kuruvilla Varghese |
Dynamically reconfigurable regular expression matching architecture. |
ASAP |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Koji Nakano, Kensuke Kawakami, Koji Shigemoto, Yuki Kamada, Yasuaki Ito |
A Tiny Processing System for Education and Small Embedded Systems on the FPGAs. |
EUC (2) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Hiroyuki Torikai, Sho Hashimoto |
A hardware-oriented learning algorithm for a digital spiking neuron. |
IJCNN |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Masaya Ohta, Keiichi Mizutani, Naoki Fujita, Katsumi Yamashita |
Complexity suppression of neural networks for PAPR reduction of OFDM signal and its FPGA implementation. |
IJCNN |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Shahid Rizwan |
Retimed Decomposed Serial Berlekamp-Massey (BM) Architecture for High-Speed Reed-Solomon Decoding. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Mohammed Shareef I, Pradeep Nair, Bharadwaj Amrutur |
Energy Reduction in SRAM using Dynamic Voltage and Frequency Management. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
Delay Monitor, DVFM, Pareto optimal curve, Replica circuits, SRAM, Energy reduction, Energy monitor |
10 | Maxim Leonov, Vyacheslav V. Kitaev |
Feasibility Study of Implementing Multi-Channel Correlation for DSP Applications on Reconfigurable CPU+FPGA Platform. |
PDCAT |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Xiang Xiao, Jaehwan John Lee |
A Novel Parallel Deadlock Detection Algorithm and Hardware for Multiprocessor System-on-a-Chip. |
IEEE Comput. Archit. Lett. |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Maria Stepanova, Feng Lin 0002, Valerie C.-L. Lin |
A Hopfield Neural Classifier and Its FPGA Implementation for Identification of Symmetrically Structured DNA Motifs. |
J. VLSI Signal Process. |
2007 |
DBLP DOI BibTeX RDF |
DNA motifs, sequence structure identification, hopfield classifier, field-programmable gate arrays, recurrent neural network |
10 | Sandip Ray, Warren A. Hunt Jr. |
Mechanized Certification of Secure Hardware Designs. |
MTV |
2007 |
DBLP DOI BibTeX RDF |
|
10 | B. Lorente, Raul Aragonés, Joan Oliver, Carles Ferrer 0001 |
Behavioural modelling and simulation for heterogeneous design applied to aerospace inertial microinstrumentation development. |
SCSC |
2007 |
DBLP BibTeX RDF |
smart inertial sensors, UML, design methodology, behavioral modeling, distributed architecture, VHDL-AMS |
10 | Ilker Hamzaoglu, Ozgur Tasdizen, Esra Sahin |
An efficient H.264 intra frame coder system design. |
VLSI-SoC |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Ioannis Mavroidis, Ioannis Papaefstathiou |
Efficient testbench code synthesis for a hardware emulator system. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Shireesh Verma, Ian G. Harris, Kiran Ramineni |
Interactive presentation: Automatic generation of functional coverage models from behavioral verilog descriptions. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Wolfgang Ecker, Volkan Esen, Lars Schönberg, Thomas Steininger, Michael Velten, Michael Hull |
Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Esra Sahin, Ilker Hamzaoglu |
Interactive presentation: An efficient hardware architecture for H.264 intra prediction algorithm. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Maciej J. Ciesielski, Serkan Askar, Daniel Gomez-Prado, Jérémie Guillot, Emmanuel Boutillon |
Data-flow transformations using Taylor expansion diagrams. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Oana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu, Alexandru Amaricai |
Saboteur-Based Fault Injection for Quantum Circuits Fault Tolerance Assessment. |
DSD |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Esra Sahin, Ilker Hamzaoglu |
An Efficient Intra Prediction Hardware Architecture for H.264 Video Decoding. |
DSD |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Serkan Oktem, Ilker Hamzaoglu |
An Efficient Hardware Architecture for Quarter-Pixel Accurate H.264 Motion Estimation. |
DSD |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Muhammad T. Anan, Ghulam M. Chaudhry |
A Real-Time Hardware-Based Scheduler For Next-Generation Optical Burst Switches. |
ICC |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Takeshi Shiro, Masaaki Abe, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai |
A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Xiao Hu, Pengyong Ma, Shuming Chen |
Scheduling for Combining Traffic of On-Chip Trace Data in Embedded Multi-core Processor. |
ICESS |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Ali Ahmadinia, Balal Ahmad, Ahmet T. Erdogan, Tughrul Arslan |
System-level Modelling and Analysis of Embedded Reconfigurable Cores for Wireless Systems. |
FPL |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Gaye Lightbody, Roger F. Woods, Jonathan Francey |
Soft IP core implementation of recursive least squares filter using only multplicative and additive operators. |
FPL |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Sangkil Jung, Sangjin Hong, Kyungtae Kim |
On Achieving High Performance Wireless Mesh Networks With Data Fusion. |
WOWMOM |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Jin-Oh Jeon, Su-Bong Ryu, Tae-Min Chang, Ho-Yong Choi, Min-Sup Kang |
Digital Codec Design for RFID Tag Based on Cryptographic Authentication Protocol. |
FGCN (2) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Rainer Scholz |
Adapting and Automating XILINX's Partial Reconfiguration Flow for Multiple Module Implementations. |
ARC |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Himanshu Arora, Nikolaus Klemmer, Thomas Jochum, Patrick D. Wolf |
Design Methodology and CAD Tools for Prototyping Delta-Sigma Fractional-N Frequency Synthesizers. |
IEEE International Workshop on Rapid System Prototyping |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Ik-Jae Chun, Tae Moon Roh, Bo-Gwan Kim |
Binary-Truncated CDMA-Based On-Chip Network. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Jun Wang 0010, Kyeong-Yuk Min, Jong-Wha Chong |
A Hybrid Image Coding in Overdriving for Motion Blur Reduction in LCD. |
ICEC |
2007 |
DBLP DOI BibTeX RDF |
Overdriving, Block Truncation Coding, Adaptive Quantization Coding, Compression, LCD, Motion blur |
10 | Mustafa Parlak, Ilker Hamzaoglu |
A Low Power Implementation of H.264 Adaptive Deblocking Filter Algorithm. |
AHS |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Jin-Oh Jeon, Su-Bong Ryu, Sang-Jo Park, Min-Sup Kang |
Strong Authentication Protocol for RFID Tag Using SHA-1 Hash Algorithm. |
ICCSA (1) |
2007 |
DBLP DOI BibTeX RDF |
Strong authentication protocol, SHA-1 hash algorithm, Three-way challenge response, ISO/IEC 1800-3 standard, Digital Codec design, RFID Tag |
10 | Taikyeong Jeong, Jinsuk Kang, Youngjun John, Inhwa Choi, Sungsoo Choi, Hyosik Yang, Gyung-Leen Park, Sehwan Yoo |
A Time Division Multiplexing (TDM) Logic Mapping Method for Computational Applications. |
ICCSA (1) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Kazuo Sakiyama, Elke De Mulder, Bart Preneel, Ingrid Verbauwhede |
Side-channel resistant system-level design flow for public-key cryptography. |
ACM Great Lakes Symposium on VLSI |
2007 |
DBLP DOI BibTeX RDF |
elliptic curve cryptography, side-channel attack, system-level modeling |
10 | Haruhiko Kaneko, Eiji Fujiwara |
Reconstruction of Erasure Correcting Codes for Dependable Distributed Storage System without Spare Disks. |
DFT |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Seung-Man Pyen, Kyeong-Yuk Min, Jong-Wha Chong |
An Efficient VLSI Architecture for Full-Search Variable Block Size Motion Estimation in H.264/AVC. |
MMM (2) |
2007 |
DBLP DOI BibTeX RDF |
VBSME, VLSI, motion estimation, H.264/AVC, block matching algorithm |
10 | Mohammad Ali Ghodrat, Kanishka Lahiri, Anand Raghunathan |
Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Stephen A. Edwards, Olivier Tardieu |
SHIM: a deterministic model for heterogeneous embedded systems. |
IEEE Trans. Very Large Scale Integr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Maciej J. Ciesielski, Priyank Kalla, Serkan Askar |
Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
Register transfer level—design aids, arithmetic and logic structures—verification, symbolic and algebraic manipulation, verification |
10 | Jaehwan John Lee, Vincent John Mooney |
A Novel {O(n)} Parallel Banker's Algorithm for System-on-a-Chip. |
IEEE Trans. Parallel Distributed Syst. |
2006 |
DBLP DOI BibTeX RDF |
Parallel Banker's Algorithm, deadlock avoidance in hardware, multiprocessor system-on-a-chip |
10 | Kim Sandström, Ian Oliver |
A UML Profile for Asynchronous Hardware Design. |
SAMOS |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Ali Habibi, Haja Moinudeen, Amer Samarah, Sofiène Tahar |
Towards a Faster Simulation of SystemC Designs. |
ISVLSI |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Masood Deh-Yadegari, Mohsen Nickray, Ali Afzali-Kusha, Zainalabedin Navabi |
A New Protocol Stack Model for Network on Chip. |
ISVLSI |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Sinan Yalcin, Ilker Hamzaoglu |
A High Performance Hardware Architecture for Half-Pixel Accurate H.264 Motion Estimation. |
VLSI-SoC |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Hamid Shojaei, Mohammad Sayyaran |
Signal Coverage Computation in Formal Verification. |
VLSI-SoC |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Alexander Kamkin |
The UniTESK Approach to Specification-Based Validation of Hardware Designs. |
ISoLA |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Baofeng Li, Qiang Shao |
Deeply Parallel Architecture for Lifting-Based 2D DWT in JPEG2000. |
CIT |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Sangkil Jung, Sangjin Hong, Peom Park |
Effect of RObust Header Compression (ROHC) and Packet Aggregation on Multi-hop Wireless Mesh Networks. |
CIT |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Lin Qiang, Nigel M. Allinson |
Spatial Optical Distortion Correction in an FPGA. |
SiPS |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Choudhury A. Rahman, Wael M. Badawy |
An Area Efficient Real-time CAVLC IP-Block towards the H.264/AVC Encoder. |
SiPS |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Seung-Man Pyen, Kyeong-Yuk Min, Jong-Wha Chong, Satoshi Goto |
An Efficient Hardware Architecture for Full-Search Variable Block Size Motion Estimation in H.264/AVC. |
ISVC (2) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Encarnación Castillo, Luis Parrilla 0001, Antonio García 0001, Antonio Lloris-Ruíz, Uwe Meyer-Bäse |
IPP Watermarking Technique for IP Core Protection on FPL Devices. |
FPL |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Zude Zhou, Songlin Cheng, Quan Liu |
Application of DDR Controller for High-speed Data Acquisition Board. |
ICICIC (2) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Jérôme Lemaitre, Ed F. Deprettere |
FPGA Implementation of a Prototype Hierarchical Control Network for Large-Scale Signal Processing Applications. |
Euro-Par |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Victor M. Goulart Ferreira, Lovic Gauthier, Takayuki Kando, Takuma Matsuo, Toshihiko Hashinaga, Kazuaki J. Murakami |
REDEFIS: a system with a redefinable instruction set processor. |
SBCCI |
2006 |
DBLP DOI BibTeX RDF |
ISA customization, dynamically reconfigurable processor, low power, SoC, high performance |
10 | Dong-Sun Kim 0002, Hyunsik Kim, Duck-Jin Chung |
Implementation of a Neural Network Processor Based on RISC Architecture for Various Signal Processing Applications. |
ISNN (2) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Gerald R. Morris, Viktor K. Prasanna, Richard D. Anderson |
A Hybrid Approach for Mapping Conjugate Gradient onto an FPGA-Augmented Reconfigurable Supercomputer. |
FCCM |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Tom Van Court, Martin C. Herbordt |
Application-Specific Memory Interleaving Enables High Performance in FPGA-based Grid Computations. |
FCCM |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Jack Whitham, Neil C. Audsley |
Integrating Custom Instruction Specifications into C Development Processes. |
ARC |
2006 |
DBLP DOI BibTeX RDF |
|