Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
19 | Tamio Hoshino |
UDL/I version Two: A New Horizon of HDL Standards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHDL ![In: Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications - CHDL '93, sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC, Ottawa, Ontario, Canada, 26-28 April, 1993, pp. 437-452, 1993, North-Holland, 0-444-81641-0. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
19 | Felice Balarin, Gary York |
Verilog HDL Modeling Styles for Formal Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHDL ![In: Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications - CHDL '93, sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC, Ottawa, Ontario, Canada, 26-28 April, 1993, pp. 453-465, 1993, North-Holland, 0-444-81641-0. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
19 | Gustavo R. Alves, Manuel G. Gericota, José L. Ramalho, José Manuel Martins Ferreira |
An HDL approach to board-level BIST. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings of the European Design Automation Conference 1993, EURO-DAC '93 with EURO-VHDL'93, Hamburg, Germany, September 20-24, 1993, pp. 410-415, 1993, IEEE Computer Society, 0-8186-4350-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
19 | Frank Buijs |
ALU synthesis from HDL descriptions to optimized multi-level logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings of the conference on European design automation, EURO-DAC '92, Hamburg, Germany, September 7-10, 1992, pp. 175-180, 1992, IEEE Computer Society Press, 0-8186-2780-8. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
19 | Timothy Kam, P. A. Subrahmanyam |
Comparing Layouts with HDL Models: A Formal Verification Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, ICCD '92, Cambridge, MA, USA, October 11-14, 1992, pp. 588-591, 1992, IEEE Computer Society, 0-8186-3110-4. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
19 | Ryszard F. Gajda, Miroslaw Thor, Marek Tudruj |
Enhancing a control graph based HDL for performance evaluation of simulated architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocessing and Microprogramming ![In: Microprocessing and Microprogramming 30(1-5), pp. 683-691, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
19 | Daniel Fischer, Yossi Levhari, Gadi Singer |
NETHDL: abstraction of schematics to high-level HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 90-96, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
19 | Auli Reinikka, Antti Auer, Ari Okkonen |
Automatic synthesis of structural HDL descriptions from graphic specification of embedded asics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocessing and Microprogramming ![In: Microprocessing and Microprogramming 27(1-5), pp. 473-478, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
19 | Sumit Ghosh |
Using Ada as an HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test ![In: IEEE Des. Test 5(1), pp. 30-42, 1988. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
19 | James B. Rawlings |
VHSIC HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 19th Design Automation Conference, DAC '82, Las Vegas, Nevada, USA, June 14-16, 1982, pp. 213, 1982, ACM/IEEE. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
|
19 | Sajjan G. Shiva |
Combinational logic synthesis from an HDL description. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 17th Design Automation Conference, DAC '80, Minneapolis, Minnesota, USA, June 23-25, 1980, pp. 550-555, 1980, ACM/IEEE, 0-89791-020-6. The full citation details ...](Pics/full.jpeg) |
1980 |
DBLP DOI BibTeX RDF |
|
10 | Brahim Al Farisi, Karel Bruneel, Harald Devos, Dirk Stroobandt |
Automatic tool flow for shift-register-LUT reconfiguration: making run-time reconfiguration fast and easy (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 287, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
parameterizable configurations, tmap, fpga, reconfigurable computing, run-time reconfiguration, srl, icap |
10 | Nicola Bombieri, Franco Fummi, Graziano Pravadelli |
Abstraction of RTL IPs into embedded software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 24-29, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
RTL IP reuse, embedded software generation |
10 | ByongChan Lim, Jaeha Kim, Mark A. Horowitz |
An efficient test vector generation for checking analog/mixed-signal functional models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 767-772, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
linear abstraction, validation, equivalence checking, verilog, functional model, test vector, mixed-signal circuits |
10 | Petr Kobierský, Jan Korenek, Libor Polcak |
Packet header analysis and field extraction for multigigabit networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, April 15-17, 2009, Liberec, Czech Republic, pp. 96-101, 2009, IEEE Computer Society, 978-1-4244-3341-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
10 | Per Karlström, Dake Liu |
NoGAP: A Micro Architecture Construction Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 9th International Workshop, SAMOS 2009, Samos, Greece, July 20-23, 2009. Proceedings, pp. 171-180, 2009, Springer, 978-3-642-03137-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
10 | Warren A. Hunt Jr., Sol Swords |
Centaur Technology Media Unit Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAV ![In: Computer Aided Verification, 21st International Conference, CAV 2009, Grenoble, France, June 26 - July 2, 2009. Proceedings, pp. 353-367, 2009, Springer, 978-3-642-02657-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
10 | Stephen Jang, Dennis Wu, Mark Jarvin, Billy Chan, Kevin Chung, Alan Mishchenko, Robert K. Brayton |
SmartOpt: an industrial strength framework for logic synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 237-240, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
abc, blif, edge flow, smartopt, fpga, interface, technology mapping |
10 | Junguk Cho, Shahnam Mirzaei, Jason Oberg, Ryan Kastner |
Fpga-based face detection system using Haar classifiers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 103-112, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
haar classifier, fpga, image processing, real-time, architecture, face detection, adaboost |
10 | Carlos Ivan Castro Marquez, Marius Strum, Jiang Chau Wang |
A PD-based methodology to enhance efficiency in testbenches with random stimulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
parameter domains, system-on-chip, design methodologies, functional verification, coverage analysis |
10 | Jaeyoung Yi, Karam Park, Joonseok Park, Won Woo Ro |
Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings, pp. 181-192, 2009, Springer, 978-3-642-00640-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Block Cipher Algorithm, Field Programmable Gate Arrays (FPGA), Cryptography, SEED |
10 | Jack Whitham, Neil C. Audsley, Martin Schoeberl |
Using hardware methods to improve time-predictable performance in real-time Java systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
JTRES ![In: Proceedings of the 7th International Workshop on Java Technologies for Real-Time and Embedded Systems, JTRES 2009, Madrid, Spain, September 23-25, 2009, pp. 130-139, 2009, ACM, 978-1-60558-732-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
10 | Balaji V. Iyer, Thomas M. Conte |
On power and energy trends of IEEE 802.11n PHY. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSWiM ![In: Proceedings of the 12th International Symposium on Modeling Analysis and Simulation of Wireless and Mobile Systems, MSWiM 2009, Tenerife, Canary Islands, Spain, October 26-19, 2009, pp. 353-356, 2009, ACM, 978-1-60558-616-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
power and energy characterization, IEEE 802.11n |
10 | Gongyu Wang, Greg Stitt, Herman Lam, Alan D. George |
A framework for core-level modeling and design of reconfigurable computing algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPRCTA@SC ![In: Proceedings of the Third International Workshop on High-Performance Reconfigurable Computing Technology and Applications, HPRTCA 2009, November 15, 2009, Portland, Oregon, USA, pp. 29-38, 2009, ACM, 978-1-60558-721-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
10 | Zhi Guo, Walid A. Najjar, Betul Buyukkurt |
Efficient hardware code generation for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 5(1), pp. 6:1-6:26, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FPGA, high-level synthesis, VHDL, Reconfigurable computing, data reuse |
10 | Bingfeng Mei, Bjorn De Sutter, Tom Vander Aa, M. Wouters, Andreas Kanstein, Steven Dupont |
Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 51(3), pp. 225-243, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
H.264/AVC decoder, FPGA, multimedia, embedded system, reconfigurable architecture, VLIW |
10 | Chun-Lung Hsu, Yu-Sheng Huang |
A Fast-Deblocking Boundary-strength Based Architecture Design of Deblocking Filter in H.264/AVC Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 52(3), pp. 211-229, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FDBS, H.264/AVC, PSNR, bit-rate, deblocking filter |
10 | Kuo-Kai Shyu, Ming-Huan Lee, Yu-Te Wu, Po-Lei Lee |
Implementation of Pipelined FastICA on FPGA for Real-Time Blind Source Separation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Neural Networks ![In: IEEE Trans. Neural Networks 19(6), pp. 958-970, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Bernhard Peischl, Naveed Riaz, Franz Wotawa |
Advances in Automated Source-Level Debugging of Verilog Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
New Challenges in Applied Intelligence Technologies ![In: New Challenges in Applied Intelligence Technologies, pp. 363-372, 2008, Springer, 978-3-540-79354-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
debugging of hardware designs, multiple testcases, model-based diagnosis, software debugging |
10 | Yazmín Maldonado, Oscar Montiel, Roberto Sepúlveda, Oscar Castillo 0001 |
Design and Simulation of the Fuzzification Stage through the Xilinx System Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Soft Computing for Hybrid Intelligent Systems ![In: Soft Computing for Hybrid Intelligent Systems, pp. 297-305, 2008, Springer, 978-3-540-70811-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Christian Haufe, Frank Rogin |
Ad-Hoc Translations to Close Verilog Semantics Gap. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008, pp. 195-200, 2008, IEEE Computer Society, 978-1-4244-2276-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Jaume Joven, Oriol Font-Bach, David Castells-Rufas, Ricardo Martínez, Lluís Terés, Jordi Carrabina |
xENoC - An eXperimental Network-On-Chip Environment for Parallel Distributed Computing on NoC-based MPSoC Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 16th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP 2008), 13-15 February 2008, Toulouse, France, pp. 141-148, 2008, IEEE Computer Society, 978-0-7695-3089-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
NoC-based MPSoCs, Message Passing Interface, Distributed Programming, Design Tools and Techniques |
10 | Topon Kumar Paul, Ken Ueno, Koichiro Iwata, Toshio Hayashi, Nobuyoshi Honda |
Genetic Algorithm Based Methods for Identification of Health Risk Factors Aimed at Preventing Metabolic Syndrome. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SEAL ![In: Simulated Evolution and Learning, 7th International Conference, SEAL 2008, Melbourne, Australia, December 7-10, 2008. Proceedings, pp. 210-219, 2008, Springer, 978-3-540-89693-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
unbalanced data, metabolic syndrome, RPMBGA+, AUC balanced, classification, Feature selection, fitness evaluation |
10 | Mohammad Reza Kakoee, Mohammad Riazati, Siamak Mohammadi |
Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008, pp. 714-720, 2008, IEEE Computer Society, 978-0-7695-3277-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Mehdi Dehbashi, Vahid Lari, Seyed Ghassem Miremadi, Mohammad Shokrollah-Shirazi |
Fault Effects in FlexRay-Based Networks with Hybrid Topology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARES ![In: Proceedings of the The Third International Conference on Availability, Reliability and Security, ARES 2008, March 4-7, 2008, Technical University of Catalonia, Barcelona , Spain, pp. 491-496, 2008, IEEE Computer Society, 978-0-7695-3102-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FlexRay Protocol, Fault Injection, Error Propagation, Distributed Embedded Systems, Dependability Evaluation |
10 | Norio Yamagaki, Reetinder P. S. Sidhu, Satoshi Kamiya |
High-speed regular expression matching engine using multi-character NFA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008, pp. 131-136, 2008, IEEE, 978-1-4244-1961-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Ruchika Verma, Ali Akoglu |
A coarse grained and hybrid reconfigurable architecture with flexible NoC router for variable block size motion estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-8, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Miaoqing Huang, Kris Gaj, Soonhak Kwon, Tarek A. El-Ghazawi |
An Optimized Hardware Architecture for the Montgomery Multiplication Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Public Key Cryptography ![In: Public Key Cryptography - PKC 2008, 11th International Workshop on Practice and Theory in Public-Key Cryptography, Barcelona, Spain, March 9-12, 2008. Proceedings, pp. 214-228, 2008, Springer, 978-3-540-78439-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
MWR2MM Algorithm, Field Programmable Gate Arrays, Montgomery Multiplication |
10 | Armando Astarloa, Unai Bidarte, Jaime Jimenez, Jesús Lázaro 0001, Iñigo Martínez de Alegría |
Secure Ethernet Point-to-Point Links for Autonomous Electronic Ballot Boxes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATC ![In: Autonomic and Trusted Computing, 5th International Conference, ATC 2008, Oslo, Norway, June 23-25, 2008, Proceedings, pp. 603-614, 2008, Springer, 978-3-540-69294-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Kok-Leong Chang, Yao Zhu, Bah-Hwee Gwee |
De-synchronization of a point-of-sales digital-logic controller. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 3402-3405, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | J. Divyasree, H. Rajashekar, Kuruvilla Varghese |
Dynamically reconfigurable regular expression matching architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 19th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2008, July 2-4, 2008, Leuven, Belgium, pp. 120-125, 2008, IEEE Computer Society, 978-1-4244-1897-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Koji Nakano, Kensuke Kawakami, Koji Shigemoto, Yuki Kamada, Yasuaki Ito |
A Tiny Processing System for Education and Small Embedded Systems on the FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC (2) ![In: 2008 IEEE/IPIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), Shanghai, China, December 17-20, 2008, Volume II: Workshops, pp. 472-479, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Hiroyuki Torikai, Sho Hashimoto |
A hardware-oriented learning algorithm for a digital spiking neuron. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IJCNN ![In: Proceedings of the International Joint Conference on Neural Networks, IJCNN 2008, part of the IEEE World Congress on Computational Intelligence, WCCI 2008, Hong Kong, China, June 1-6, 2008, pp. 2472-2479, 2008, IEEE, 978-1-4244-1820-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Masaya Ohta, Keiichi Mizutani, Naoki Fujita, Katsumi Yamashita |
Complexity suppression of neural networks for PAPR reduction of OFDM signal and its FPGA implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IJCNN ![In: Proceedings of the International Joint Conference on Neural Networks, IJCNN 2008, part of the IEEE World Congress on Computational Intelligence, WCCI 2008, Hong Kong, China, June 1-6, 2008, pp. 3474-3478, 2008, IEEE, 978-1-4244-1820-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Shahid Rizwan |
Retimed Decomposed Serial Berlekamp-Massey (BM) Architecture for High-Speed Reed-Solomon Decoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 53-58, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Mohammed Shareef I, Pradeep Nair, Bharadwaj Amrutur |
Energy Reduction in SRAM using Dynamic Voltage and Frequency Management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 503-508, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Delay Monitor, DVFM, Pareto optimal curve, Replica circuits, SRAM, Energy reduction, Energy monitor |
10 | Maxim Leonov, Vyacheslav V. Kitaev |
Feasibility Study of Implementing Multi-Channel Correlation for DSP Applications on Reconfigurable CPU+FPGA Platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDCAT ![In: Ninth International Conference on Parallel and Distributed Computing, Applications and Technologies, PDCAT 2008, Dunedin, Otago, New Zealand, 1-4 December 2008, pp. 159-166, 2008, IEEE Computer Society, 978-0-7695-3443-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
10 | Xiang Xiao, Jaehwan John Lee |
A Novel Parallel Deadlock Detection Algorithm and Hardware for Multiprocessor System-on-a-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Comput. Archit. Lett. ![In: IEEE Comput. Archit. Lett. 6(2), pp. 41-44, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Maria Stepanova, Feng Lin 0002, Valerie C.-L. Lin |
A Hopfield Neural Classifier and Its FPGA Implementation for Identification of Symmetrically Structured DNA Motifs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 48(3), pp. 239-254, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
DNA motifs, sequence structure identification, hopfield classifier, field-programmable gate arrays, recurrent neural network |
10 | Sandip Ray, Warren A. Hunt Jr. |
Mechanized Certification of Secure Hardware Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), Common Challenges and Solutions, 5-6 December 2007, Austin, Texas, USA, pp. 25-32, 2007, IEEE Computer Society, 978-0-7695-3241-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | B. Lorente, Raul Aragonés, Joan Oliver, Carles Ferrer 0001 |
Behavioural modelling and simulation for heterogeneous design applied to aerospace inertial microinstrumentation development. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCSC ![In: Proceedings of the 2007 Summer Computer Simulation Conference, SCSC 2007, San Diego, California, USA, July 16-19, 2007, pp. 551-558, 2007, Simulation Councils, Inc., 1-56555-316-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
smart inertial sensors, UML, design methodology, behavioral modeling, distributed architecture, VHDL-AMS |
10 | Ilker Hamzaoglu, Ozgur Tasdizen, Esra Sahin |
An efficient H.264 intra frame coder system design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2007, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA, 15-17 October 2007, pp. 200-205, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Ioannis Mavroidis, Ioannis Papaefstathiou |
Efficient testbench code synthesis for a hardware emulator system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 888-893, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Shireesh Verma, Ian G. Harris, Kiran Ramineni |
Interactive presentation: Automatic generation of functional coverage models from behavioral verilog descriptions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 900-905, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Wolfgang Ecker, Volkan Esen, Lars Schönberg, Thomas Steininger, Michael Velten, Michael Hull |
Interactive presentation: Impact of description language, abstraction layer, and value representation on simulation performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 767-772, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Esra Sahin, Ilker Hamzaoglu |
Interactive presentation: An efficient hardware architecture for H.264 intra prediction algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 183-188, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Maciej J. Ciesielski, Serkan Askar, Daniel Gomez-Prado, Jérémie Guillot, Emmanuel Boutillon |
Data-flow transformations using Taylor expansion diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 455-460, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Oana Boncalo, Mihai Udrescu, Lucian Prodan, Mircea Vladutiu, Alexandru Amaricai |
Saboteur-Based Fault Injection for Quantum Circuits Fault Tolerance Assessment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany, pp. 634-640, 2007, IEEE Computer Society, 0-7695-2978-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Esra Sahin, Ilker Hamzaoglu |
An Efficient Intra Prediction Hardware Architecture for H.264 Video Decoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany, pp. 448-454, 2007, IEEE Computer Society, 0-7695-2978-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Serkan Oktem, Ilker Hamzaoglu |
An Efficient Hardware Architecture for Quarter-Pixel Accurate H.264 Motion Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany, pp. 444-447, 2007, IEEE Computer Society, 0-7695-2978-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Muhammad T. Anan, Ghulam M. Chaudhry |
A Real-Time Hardware-Based Scheduler For Next-Generation Optical Burst Switches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICC ![In: Proceedings of IEEE International Conference on Communications, ICC 2007, Glasgow, Scotland, UK, 24-28 June 2007, pp. 2289-2293, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Takeshi Shiro, Masaaki Abe, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai |
A Processor Generation Method from Instruction Behavior Description Based on Specification of Pipeline Stages and Functional Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 286-291, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Xiao Hu, Pengyong Ma, Shuming Chen |
Scheduling for Combining Traffic of On-Chip Trace Data in Embedded Multi-core Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICESS ![In: Embedded Software and Systems, [Third] International Conference, ICESS 2007, Daegu, Korea, May 14-16, 2007, Proceedings, pp. 67-79, 2007, Springer, 978-3-540-72684-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Ali Ahmadinia, Balal Ahmad, Ahmet T. Erdogan, Tughrul Arslan |
System-level Modelling and Analysis of Embedded Reconfigurable Cores for Wireless Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 757-760, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Gaye Lightbody, Roger F. Woods, Jonathan Francey |
Soft IP core implementation of recursive least squares filter using only multplicative and additive operators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 597-600, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Sangkil Jung, Sangjin Hong, Kyungtae Kim |
On Achieving High Performance Wireless Mesh Networks With Data Fusion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WOWMOM ![In: 2007 International Symposium on a World of Wireless, Mobile and Multimedia Networks (WoWMoM 2007), 18-21 June 2007, Helsinki, Finland, Proceedings, pp. 1-8, 2007, IEEE Computer Society, 1-4244-0992-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Jin-Oh Jeon, Su-Bong Ryu, Tae-Min Chang, Ho-Yong Choi, Min-Sup Kang |
Digital Codec Design for RFID Tag Based on Cryptographic Authentication Protocol. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FGCN (2) ![In: Future Generation Communication and Networking, FGCN 2007, Ramada Plaza Jeju, Jeju-Island, Korea, December 6-8, 2007, Proceedings, pp. 119-124, 2007, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Rainer Scholz |
Adapting and Automating XILINX's Partial Reconfiguration Flow for Multiple Module Implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, Third International Workshop, ARC 2007, Mangaratiba, Brazil, March 27-29, 2007., pp. 122-129, 2007, Springer, 978-3-540-71430-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Himanshu Arora, Nikolaus Klemmer, Thomas Jochum, Patrick D. Wolf |
Design Methodology and CAD Tools for Prototyping Delta-Sigma Fractional-N Frequency Synthesizers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 28-30 May 2007, Porto Alegre, RS, Brazil, pp. 150-156, 2007, IEEE Computer Society, 978-0-7695-2834-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Ik-Jae Chun, Tae Moon Roh, Bo-Gwan Kim |
Binary-Truncated CDMA-Based On-Chip Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 397-400, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Jun Wang 0010, Kyeong-Yuk Min, Jong-Wha Chong |
A Hybrid Image Coding in Overdriving for Motion Blur Reduction in LCD. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICEC ![In: Entertainment Computing - ICEC 2007, 6th International Conference, Shanghai, China, September 15-17, 2007, Proceedings, pp. 263-270, 2007, Springer, 978-3-540-74872-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Overdriving, Block Truncation Coding, Adaptive Quantization Coding, Compression, LCD, Motion blur |
10 | Mustafa Parlak, Ilker Hamzaoglu |
A Low Power Implementation of H.264 Adaptive Deblocking Filter Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), August 5-8, 2007, University of Edinburgh, Scotland, United Kingdom, pp. 127-133, 2007, IEEE Computer Society, 0-7695-2866-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Jin-Oh Jeon, Su-Bong Ryu, Sang-Jo Park, Min-Sup Kang |
Strong Authentication Protocol for RFID Tag Using SHA-1 Hash Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSA (1) ![In: Computational Science and Its Applications - ICCSA 2007, International Conference, Kuala Lumpur, Malaysia, August 26-29, 2007. Proceedings, Part I, pp. 634-643, 2007, Springer, 978-3-540-74468-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Strong authentication protocol, SHA-1 hash algorithm, Three-way challenge response, ISO/IEC 1800-3 standard, Digital Codec design, RFID Tag |
10 | Taikyeong Jeong, Jinsuk Kang, Youngjun John, Inhwa Choi, Sungsoo Choi, Hyosik Yang, Gyung-Leen Park, Sehwan Yoo |
A Time Division Multiplexing (TDM) Logic Mapping Method for Computational Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSA (1) ![In: Computational Science and Its Applications - ICCSA 2007, International Conference, Kuala Lumpur, Malaysia, August 26-29, 2007. Proceedings, Part I, pp. 1096-1106, 2007, Springer, 978-3-540-74468-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Kazuo Sakiyama, Elke De Mulder, Bart Preneel, Ingrid Verbauwhede |
Side-channel resistant system-level design flow for public-key cryptography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 144-147, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
elliptic curve cryptography, side-channel attack, system-level modeling |
10 | Haruhiko Kaneko, Eiji Fujiwara |
Reconstruction of Erasure Correcting Codes for Dependable Distributed Storage System without Spare Disks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy., pp. 349-358, 2007, IEEE Computer Society, 0-7695-2885-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Seung-Man Pyen, Kyeong-Yuk Min, Jong-Wha Chong |
An Efficient VLSI Architecture for Full-Search Variable Block Size Motion Estimation in H.264/AVC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MMM (2) ![In: Advances in Multimedia Modeling, 13th International Multimedia Modeling Conference, MMM 2007, Singapore, January 9-12, 2007. Proceedings, Part II, pp. 41-50, 2007, Springer, 978-3-540-69428-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
VBSME, VLSI, motion estimation, H.264/AVC, block matching algorithm |
10 | Mohammad Ali Ghodrat, Kanishka Lahiri, Anand Raghunathan |
Accelerating System-on-Chip Power Analysis Using Hybrid Power Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 883-886, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
10 | Stephen A. Edwards, Olivier Tardieu |
SHIM: a deterministic model for heterogeneous embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 14(8), pp. 854-867, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Maciej J. Ciesielski, Priyank Kalla, Serkan Askar |
Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(9), pp. 1188-1201, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Register transfer level—design aids, arithmetic and logic structures—verification, symbolic and algebraic manipulation, verification |
10 | Jaehwan John Lee, Vincent John Mooney |
A Novel {O(n)} Parallel Banker's Algorithm for System-on-a-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 17(12), pp. 1377-1389, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Parallel Banker's Algorithm, deadlock avoidance in hardware, multiprocessor system-on-a-chip |
10 | Kim Sandström, Ian Oliver |
A UML Profile for Asynchronous Hardware Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 6th International Workshop, SAMOS 2006, Samos, Greece, July 17-20, 2006, Proceedings, pp. 15-26, 2006, Springer, 3-540-36410-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Ali Habibi, Haja Moinudeen, Amer Samarah, Sofiène Tahar |
Towards a Faster Simulation of SystemC Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 418-419, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Masood Deh-Yadegari, Mohsen Nickray, Ali Afzali-Kusha, Zainalabedin Navabi |
A New Protocol Stack Model for Network on Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 440-441, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Sinan Yalcin, Ilker Hamzaoglu |
A High Performance Hardware Architecture for Half-Pixel Accurate H.264 Motion Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006, pp. 63-67, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Hamid Shojaei, Mohammad Sayyaran |
Signal Coverage Computation in Formal Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006, pp. 92-97, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Alexander Kamkin |
The UniTESK Approach to Specification-Based Validation of Hardware Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISoLA ![In: Leveraging Applications of Formal Methods, Second International Symposium, ISoLA 2006, Paphos, Cyprus, 15-19 November 2006, pp. 60-66, 2006, IEEE Computer Society, 978-0-7695-3071-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Baofeng Li, Qiang Shao |
Deeply Parallel Architecture for Lifting-Based 2D DWT in JPEG2000. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIT ![In: Sixth International Conference on Computer and Information Technology (CIT 2006), 20-22 September 2006, Seoul, Korea, pp. 178, 2006, IEEE Computer Society, 0-7695-2687-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Sangkil Jung, Sangjin Hong, Peom Park |
Effect of RObust Header Compression (ROHC) and Packet Aggregation on Multi-hop Wireless Mesh Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIT ![In: Sixth International Conference on Computer and Information Technology (CIT 2006), 20-22 September 2006, Seoul, Korea, pp. 91, 2006, IEEE Computer Society, 0-7695-2687-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Lin Qiang, Nigel M. Allinson |
Spatial Optical Distortion Correction in an FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada, pp. 268-273, 2006, IEEE, 1-4244-0382-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Choudhury A. Rahman, Wael M. Badawy |
An Area Efficient Real-time CAVLC IP-Block towards the H.264/AVC Encoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada, pp. 368-371, 2006, IEEE, 1-4244-0382-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Seung-Man Pyen, Kyeong-Yuk Min, Jong-Wha Chong, Satoshi Goto |
An Efficient Hardware Architecture for Full-Search Variable Block Size Motion Estimation in H.264/AVC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVC (2) ![In: Advances in Visual Computing, Second International Symposium, ISVC 2006 Lake Tahoe, NV, USA, November 6-8, 2006. Proceedings, Part II, pp. 554-563, 2006, Springer. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Encarnación Castillo, Luis Parrilla 0001, Antonio García 0001, Antonio Lloris-Ruíz, Uwe Meyer-Bäse |
IPP Watermarking Technique for IP Core Protection on FPL Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-6, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Zude Zhou, Songlin Cheng, Quan Liu |
Application of DDR Controller for High-speed Data Acquisition Board. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICIC (2) ![In: First International Conference on Innovative Computing, Information and Control (ICICIC 2006), 30 August - 1 September 2006, Beijing, China, pp. 611-614, 2006, IEEE Computer Society, 0-7695-2616-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Jérôme Lemaitre, Ed F. Deprettere |
FPGA Implementation of a Prototype Hierarchical Control Network for Large-Scale Signal Processing Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28 - September 1, 2006, Proceedings, pp. 1192-1203, 2006, Springer, 3-540-37783-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Victor M. Goulart Ferreira, Lovic Gauthier, Takayuki Kando, Takuma Matsuo, Toshihiko Hashinaga, Kazuaki J. Murakami |
REDEFIS: a system with a redefinable instruction set processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2006, Ouro Preto, MG, Brazil, August 28 - September 1, 2006, pp. 14-19, 2006, ACM. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
ISA customization, dynamically reconfigurable processor, low power, SoC, high performance |
10 | Dong-Sun Kim 0002, Hyunsik Kim, Duck-Jin Chung |
Implementation of a Neural Network Processor Based on RISC Architecture for Various Signal Processing Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISNN (2) ![In: Advances in Neural Networks - ISNN 2006, Third International Symposium on Neural Networks, Chengdu, China, May 28 - June 1, 2006, Proceedings, Part III, pp. 1340-1349, 2006, Springer, 3-540-34482-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Gerald R. Morris, Viktor K. Prasanna, Richard D. Anderson |
A Hybrid Approach for Mapping Conjugate Gradient onto an FPGA-Augmented Reconfigurable Supercomputer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 24-26 April 2006, Napa, CA, USA, Proceedings, pp. 3-12, 2006, IEEE Computer Society, 0-7695-2661-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Tom Van Court, Martin C. Herbordt |
Application-Specific Memory Interleaving Enables High Performance in FPGA-based Grid Computations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 24-26 April 2006, Napa, CA, USA, Proceedings, pp. 305-306, 2006, IEEE Computer Society, 0-7695-2661-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
10 | Jack Whitham, Neil C. Audsley |
Integrating Custom Instruction Specifications into C Development Processes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures and Applications, Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006, Revised Selected Papers, pp. 431-442, 2006, Springer. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|