Search results for "RAMs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
12	Joseph M. Palmer, Brent E. Nelson	A Parallel FFT Architecture for FPGAs.	FPL	2004	DBLP DOI BibTeX RDF
12	Norbert Pramstaller, Johannes Wolkerstorfer	A Universal and Efficient AES Co-processor for Field Programmable Logic Arrays.	FPL	2004	DBLP DOI BibTeX RDF
12	Alireza Hodjat, Ingrid Verbauwhede	A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA.	FCCM	2004	DBLP DOI BibTeX RDF
12	Michael Attig, Sarang Dharmapurikar, John W. Lockwood	Implementation Results of Bloom Filters for String Matching.	FCCM	2004	DBLP DOI BibTeX RDF
12	Rajeshwar S. Sable, Ravindra P. Saraf, Rubin A. Parekhji, Arun N. Chandorkar	Built-in Self-test Technique for Selective Detection of Neighbourhood Pattern Sensitive Faults in Memories.	VLSI Design	2004	DBLP DOI BibTeX RDF	Built-in self-test for memories, neighbourhood pattern sensitive faults, programmable BIST
12	Sung-Hsien Sun, Shie-Jue Lee	A JPEG Chip for Image Compression and Decompression.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	image compression/decompression, standard cell design, FPGA, VHDL, CAD tools, VLSI chip
12	Ivo Schanstra, Ad J. van de Goor	Consequences of RAM Bitline Twisting for Test Coverage.	DATE	2003	DBLP DOI BibTeX RDF
12	Alessandro Pirola	A Solution for Hardware Emulation of Non Volatile Memory Macrocells.	DATE	2003	DBLP DOI BibTeX RDF
12	Khaled Benkrid, S. Sukhsawas, Danny Crookes, Abdsamad Benkrid	An FPGA-Based Image Connected Component Labeller.	FPL	2003	DBLP DOI BibTeX RDF
12	Yosuke Miyajima, Tsutomu Maruyama	A Real-Time Stereo Vision System with FPGA.	FPL	2003	DBLP DOI BibTeX RDF
12	Sang-Chul Moon, In-Cheol Park	Area-efficient memory-based architecture for FFT processing.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
12	Arturo M. Amendola, Roberto Di Maio, M. L. Iacobuzio, Fabio Poli, Fernando Scalabrini	Lessons Learned in Designing and Evaluating Railway Control Systems.	WORDS Fall	2003	DBLP DOI BibTeX RDF
12	Xiaoling Sun, Bruce F. Cockburn, Duncan G. Elliott	An Efficient Functional Test for the Massively-Parallel C ?RAM Logic-Enhanced Memory Architecture.	DFT	2003	DBLP DOI BibTeX RDF
12	T. S. Rajesh Kumar, R. Govindarajan, C. P. Ravikumar	Optimal Code and Data Layout in Embedded Systems.	VLSI Design	2003	DBLP DOI BibTeX RDF
12	Pawel Chodowiec, Kris Gaj	Very Compact FPGA Implementation of the AES Algorithm.	CHES	2003	DBLP DOI BibTeX RDF
12	Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu	Fault simulation and test algorithm generation for random accessmemories.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
12	Premkumar T. Devanbu, Stuart G. Stubblebine	Stack and Queue Integrity on Hostile Platforms.	IEEE Trans. Software Eng.	2002	DBLP DOI BibTeX RDF	correctness of memories, oblivious ram, security, data structures, software protection
12	Kiyoo Itoh 0001	Trends in Ultralow-Voltage RAM Technology.	PATMOS	2002	DBLP DOI BibTeX RDF
12	Toshinori Sato, Itsujiro Arita	Simplifying Instruction Issue Logic in Superscalar Processors.	DSD	2002	DBLP DOI BibTeX RDF
12	Valery A. Vardanian, Yervant Zorian	A March-Based Fault Location Algorithm for Static Random Access Memories.	MTDT	2002	DBLP DOI BibTeX RDF
12	Manfred Ley, Herbert Grünbacher	TTA-C2, A Single Chip Communication Controller for the Time-Triggered-Protocol.	ICCD	2002	DBLP DOI BibTeX RDF
12	Valery A. Vardanian, Yervant Zorian	A March-Based Fault Location Algorithm for Static Random Access Memories.	IOLTW	2002	DBLP DOI BibTeX RDF
12	Atsumu Iseno, Yukihiro Iguchi	A Method for Storing Fail Bit Maps in Burn-in Memory Testers.	DELTA	2002	DBLP DOI BibTeX RDF
12	Eisaku Ohbuchi, Hiroshi Unno 0004	A Real-Time Configurable Shader Based on Lookup Tables.	CW	2002	DBLP DOI BibTeX RDF
12	Gianfranco Bilardi, Kattamuri Ekanadham, Pratap Pattnaik	Optimal organizations for pipelined hierarchical memories.	SPAA	2002	DBLP DOI BibTeX RDF	hierarchical memory processor, scalable pipeline
12	Caroline Benveniste, Peter A. Franaszek, John T. Robinson	Cache-Memory Interfaces in Compressed Memory Systems.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	memory compression, performance analysis, trace-driven simulation, cache design, Memory system design
12	Gianfranco Bilardi, Enoch Peserico	A Characterization of Temporal Locality and Its Portability across Memory Hierarchies.	ICALP	2001	DBLP DOI BibTeX RDF
12	Davide Appello, Fulvio Corno, M. Giovinetto, Maurizio Rebaudengo, Matteo Sonza Reorda	A P1500 Compliant BIST-Based Approach to Embedded RAM Diagnosis.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
12	G. Kallos, A. Voudouri, I. Pytharoulis, O. Kakaliagou	Modelling Framework for Atmospheric Mercury over the Mediterranean Region: Model Development and Applications.	LSSC	2001	DBLP DOI BibTeX RDF
12	Timothy Wheeler, Paul S. Graham, Brent E. Nelson, Brad L. Hutchings	Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification.	FPL	2001	DBLP DOI BibTeX RDF
12	S. K. Tewksbury	Challenges Facing Practical DFT for MEMS.	DFT	2001	DBLP DOI BibTeX RDF	Microelectromechanical systems, microsystems technologies, fault tolerance, defect tolerance
12	Gianfranco Bilardi, Kattamuri Ekanadham, Pratap Pattnaik	Computational power of pipelined memory hierarchies.	SPAA	2001	DBLP DOI BibTeX RDF
12	Yoshiki Yamaguchi, Akira Miyashita, Tsutomu Maruyama, Tsutomu Hoshino	A Co-processor System with a Virtex FPGA for Evolutionary Computation.	FPL	2000	DBLP DOI BibTeX RDF
12	Sanjive Agarwala, Charles Fuoco, Tim Anderson, Dave Comisky, Christopher Mobley	A Multi-Level Memory System Architecture for High-Performance DSP Applications.	ICCD	2000	DBLP DOI BibTeX RDF
12	Chi-Feng Wu, Chih-Tsun Huang, Kuo-Liang Cheng, Cheng-Wen Wu	Simulation-Based Test Algorithm Generation for Random Access Memories.	VTS	2000	DBLP DOI BibTeX RDF	RAM fault simulation, March test algorithm, Cocktail-March test algorithms, semiconductor memories, RAM testing
12	Mohammad Gh. Mohammad, Kewal K. Saluja, Alex S. Yap	Testing Flash Memories.	VLSI Design	2000	DBLP DOI BibTeX RDF	FG transistor, Testing, Flash memories, Disturbances
12	Vyacheslav N. Yarmolik, I. V. Bykov, Sybille Hellebrand, Hans-Joachim Wunderlich	Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms.	EDCC	1999	DBLP DOI BibTeX RDF
12	Spencer M. Gold, Richard B. Brown, Bruce Bernhardt	A Quantitative Approach to Nonlinear Process Design Rule Scaling.	ARVLSI	1999	DBLP DOI BibTeX RDF
12	José Carlos Alves, José Silva Matos	RVC - A Reconfigurable Coprocessor for Vector Processing Applications.	FCCM	1998	DBLP DOI BibTeX RDF
12	Premkumar T. Devanbu, Stuart G. Stubblebine	Stack and Queue Integrity on Hostile Platforms.	S&P	1998	DBLP DOI BibTeX RDF
12	Jim Gray 0001, Goetz Graefe	The Five-Minute Rule Ten Years Later, and Other Computer Storage Rules of Thumb.	SIGMOD Rec.	1997	DBLP DOI BibTeX RDF
12	Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue, Hideo Fujiwara	Testing for the programming circuit of LUT-based FPGAs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	programming circuit, control circuit, configuration memory cell array, FPGA, fault model, SRAM, shift registers, shift registers, look-up table
12	Dima Grigoriev, Anatol Slissenko	Computing Minimum-Link Path in a Homotopy Class amidst Semi-Algebraic Obstacles in the Plane.	AAECC	1997	DBLP DOI BibTeX RDF
12	René J. Glaise, J. Munier	A Low Cost Searching Device for an ATM Adapter.	ICCCN	1997	DBLP DOI BibTeX RDF
12	Michael Nicolaidis, Vladimir Castro Alves, Hakim Bederr	Testing complex couplings in multiport memories.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
12	Mirjam Schönfeld, Jens Franzen, Markus Schwiegershausen, Peter Pirsch, Uwe Vehlies, Andreas Münzner	The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques.	J. VLSI Signal Process.	1995	DBLP DOI BibTeX RDF
12	Masayuki Abe, Hikaru Morita	Higher Radix Nonrestoring Modular Multiplication Algorithm and Public-key LSI Architecture with Limited Hardware Resources.	ASIACRYPT	1994	DBLP DOI BibTeX RDF
12	Sundarar Mohan, Pinaki Mazumder	Analytical and simulation studies of failure modes in SRAMs using high electron mobility transistors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
12	Robert Cypher, C. Bernard Shung	Generalized trace-back techniques for survivor memory management in the Viterbi algorithm.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF	trace-back, survivor memory, VLSI area requirements, Viterbi algorithm
12	Christian von Reventlow, Maati Talmi, Stefan Wolf, M. Ernst, K. Müller, C. Stoffers	System considerations and the system level design of a chip set for real-time TV and HDTV motion estimation.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF
12	Warren H. Debany Jr., Kevin A. Kwiat, Sami A. Al-Arian	A Method for Consistent Fault Coverage Reporting.	IEEE Des. Test Comput.	1993	DBLP DOI BibTeX RDF
12	Samir Naik, Frank Agricola, Wojciech Maly	Failure Analysis of High-Density CMOS SRAMs: Using Realistic Defect Modeling and I/Sub DDQ/ Testing.	IEEE Des. Test Comput.	1993	DBLP DOI BibTeX RDF
12	Jos van Sas, Francky Catthoor, Hugo De Man	Test Algorithms for Double-Buffered Random Access and Pointer-Addressed Memories.	IEEE Des. Test Comput.	1993	DBLP DOI BibTeX RDF
12	Vishwani D. Agrawal, Charles R. Kime, Kewal K. Saluja	A Tutorial on Built-In Self-Test, Part 2: Applications.	IEEE Des. Test Comput.	1993	DBLP DOI BibTeX RDF
12	Shiva Chaudhuri, Torben Hagerup, Rajeev Raman	Approximate and Exact Deterministic Parallel Selection.	MFCS	1993	DBLP DOI BibTeX RDF
12	Nader H. Bshouty	Lower Bounds for the Complexity of Functions in a Realistic RAM Model.	ISTCS	1992	DBLP DOI BibTeX RDF
12	Jochen Kölzer, Johann Otto	Electrical Characterization of Megabit DRAMs, Part 2: Internal Testing.	IEEE Des. Test Comput.	1991	DBLP DOI BibTeX RDF
12	Georg Antonin, Hans-Dieter Oberle, Jochen Kölzer	Electrical Characterization of Megabit DRAMs, Part 1: External Testing.	IEEE Des. Test Comput.	1991	DBLP DOI BibTeX RDF
12	Wei-Kang Huang, Yinan N. Shen, Fabrizio Lombardi	New approaches for the repairs of memories with redundancy by row/column deletion for yield enhancement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
12	Ronald F. Ayres	Completely automatic completion of VLSI designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
12	Ashok K. Goel 0002, Apurva Kalia	Simulation of ram-based asynchronous sequential circuits.	Annual Simulation Symposium	1990	DBLP DOI BibTeX RDF
12	Marek Karpinski, Friedhelm Meyer auf der Heide	On the Complexity of Genuinely Polynomial Computation.	MFCS	1990	DBLP DOI BibTeX RDF
12	Andreas Geyer-Schulz, Johann Mitlöhner, Alfred Taudes	An APL-Simulator of Non-Von Neumann Computer Architectures.	APL	1990	DBLP DOI BibTeX RDF	APL
12	Etienne Grandjean, J. M. Robson	RAM with Compact Memory: A Realistic and Robust Model of Computation.	CSL	1990	DBLP DOI BibTeX RDF
12	Larry Carter, Leendert M. Huisman, Tom W. Williams	TRIM: testability range by ignoring the memory.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
12	Pinaki Mazumder, Janak H. Patel, W. Kent Fuchs	Design and Algorithms for Parallel Testing of Random Access and Content Addressable Memories.	DAC	1987	DBLP DOI BibTeX RDF
12	W. Stephen Adolph, Hassan K. Reghbati, Amar Sanmugasunderam	A frame based system for representing knowledge about VLSI design: a proposal.	DAC	1986	DBLP DOI BibTeX RDF	computer assisted design, knowledge representation, VLSI design, silicon compilation
12	John H. Reif, J. D. Tygar	Efficient Parallel Pseudo-Random Number Generation.	CRYPTO	1985	DBLP DOI BibTeX RDF
12	Cyrus Bamji, Charles E. Hauck, Jonathan Allen	A design by example regular structure generator.	DAC	1985	DBLP DOI BibTeX RDF
12	Douglas L. Finke	Dynamic RAM architectures for graphics applications.	AFIPS National Computer Conference	1983	DBLP DOI BibTeX RDF