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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 2846 occurrences of 1432 keywords
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Results
Found 14080 publication records. Showing 14080 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
23 | Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen |
An efficient optimization--based technique to generate posynomial performance models for analog integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 431-436, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
performance modeling for analog circuits, posynomial response surface modeling, geometric programming |
23 | Mandeep Singh, Israel Koren |
Reliability Enhancement of Analog-to-Digital Converters (ADCs). ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings, pp. 347-, 2001, IEEE Computer Society, 0-7695-1203-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Fault sensitivity, Alpha particle, Fault tolerance, Reliability, Transient faults, Analog-to-Digital Converters |
23 | Gloria Huertas, Diego Vázquez, Eduardo J. Peralías, Adoración Rueda, José L. Huertas |
Testing mixed-signal cores: practical oscillation-based test in an analog macrocell. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 31-38, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
analog macrocell, mixed signal integrated circuit, OBT, mixed-signal macrocell, integrated circuit testing, mixed analogue-digital integrated circuits, oscillation-based test |
23 | M. A. El-Gamal, Mohamed Fathy Abu El-Yazeed |
A Combined Clustering and Neural Network Approach for Analog Multiple Hard Fault Classification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 14(3), pp. 207-217, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
multiple hard faults, fault clustering, learning vector quantization neural networks, feature selection, analog circuits, fault classification |
23 | Sam D. Huynh, Jinyan Zhang, Seongwon Kim, Giri Devarayanadurg, Mani Soma |
Efficient Test Set Design for Analog and Mixed-Signal Circuits and Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 239-, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Efficient, ATPG, Digital, Analog, Mixed-Signal |
23 | Chauchin Su, Yue-Tsang Chen, Chung-Len Lee 0001 |
Analog Metrology and Stimulus Selection in a Noisy Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 233-238, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Mixed Signal and Analog Test |
23 | Charles S. Wilson, Tonia G. Morris, Stephen P. DeWeerth |
A Two-Dimensional, Object-Based Analog VLSI Visual Attention System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 18th Conference on Advanced Research in VLSI (ARVLSI '99), 21-24 March 1999, Atlanta, GA, USA, pp. 291-308, 1999, IEEE Computer Society, 0-7695-0056-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
attention, analog VLSI, neuromorphic, focal plane |
23 | Lars Hedrich, Erich Barke |
A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 649-654, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
electronic design automation circuit simulation, formal verification, analog circuits |
23 | Michel Renovell, Florence Azaïs, Yves Bertrand |
Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 815-821, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
VLSI, Test, Analog Circuit, Mixed Signal Circuit |
23 | Thorsten Adler, Juergen Schaeuble |
An Interactive Router for Analog IC Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 414-420, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
schematic driven layout, global router, maze router, 45 degrees, analog circuits, electronic design automation |
23 | Saeid Sadeghi-Emamchaie, Graham A. Jullien, Vassil S. Dimitrov, William C. Miller |
Digital Arithmetic Using Analog Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 19-21 February 1998, Lafayette, LA, USA, pp. 202-207, 1998, IEEE Computer Society, 0-8186-8409-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Cellular Neural Networks, Double-Base Number System, Analog VLSI |
23 | Pramodchandran N. Variyam, Abhijit Chatterjee |
Specification-Driven Test Design for Analog Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 2-4 November 1998, Austin, TX, USA, Proceedings, pp. 335-340, 1998, IEEE Computer Society, 0-8186-8832-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Genetic algorithms, Test generation, Analog and mixed-signal test |
23 | Chauchin Su, Yi-Ren Cheng, Yue-Tsang Chen, Shing Tenchen |
Analog signal metrology for mixed signal ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 194-, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
Analog signal metrology, multiple period low-rate sampled waveform, high-rate sampled waveform, DSP based testing, on-chip ADC, 20 MHz, mixed analogue-digital integrated circuits, Signal reconstruction, mixed signal IC |
23 | Pramodchandran N. Variyam, Abhijit Chatterjee, Naveena Nagi |
Low-cost and efficient digital-compatible BIST for analog circuits using pulse response sampling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 15th IEEE VLSI Test Symposium (VTS'97), April 27-May 1, 1997, Monterey, California, USA, pp. 261-266, 1997, IEEE Computer Society, 0-8186-7810-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
digital-compatible BIST scheme, pulse response sampling, low-cost BIST scheme, built-in self test scheme, rectangular pulses, digital linear feedback shift register, transient testing, synchronization circuitry, comparison circuitry, BIST hardware design, built-in self test, analog circuits |
23 | K. Ravi Shanker, Vinita Vasudevan |
Synthesis of Analog CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 439-445, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
synthesis, analog circuits |
23 | Tao Wei, Mike W. T. Wong, Yim-Shu Lee |
Efficient Multifrequency Analysis of Fault Diagnosis in Analog Circuits Based on Large Change Sensitivity Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 232-237, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
large change sensitivity, fault diagnosis, analog circuits |
23 | Chen-Yang Pan, Kwang-Ting Cheng |
Implicit functional testing for analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 489-494, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
implicit functional testing, linear time-invariant circuits, impulse response samples, pseudo-random technique, production testing time, yield coverages, VLSI, integrated circuit testing, fault coverage, analog circuits, analogue integrated circuits, mixed analogue-digital integrated circuits, transient response |
23 | Michel Renovell, Florence Azaïs, Yves Bertrand |
The multi-configuration: A DFT technique for analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 54-59, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
multi-configuration technique, diagnosis facilities, 8/sup th/ order band pass filter, integrated circuit testing, design for testability, integrated circuit design, analog circuits, analogue integrated circuits, band-pass filters, DFT technique |
23 | Diego Vázquez, José L. Huertas, Adoración Rueda |
Reducing the impact of DFT on the performance of analog integrated circuits: improved sw-op amp design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 42-47, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
sw-op amp design, CMOS implementations, design efforts, cell design, integrated circuit testing, design for testability, DFT, integrated circuit design, power dissipation, operational amplifiers, area, analogue integrated circuits, IC testing, analog integrated circuits, CMOS analogue integrated circuits |
23 | F. Mohamed, M. Manzouki, Anton Biasizzo, Franc Novak |
Analog circuit simulation and troubleshooting with FLAMES. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 495-501, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
analog circuit simulation, model-based expert system, VLSI, fuzzy logic, fuzzy logic, integrated circuit testing, circuit analysis computing, analogue integrated circuits, troubleshooting, diagnostic expert systems, FLAMES |
23 | J. van Spaandonk, Tom A. M. Kevenaar |
Iterative test-point selection for analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 66-73, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
iterative test-point selection, analog ICs, random measurement errors, VLSI, integrated circuit testing, iterative methods, functional testing, iterative algorithm, analogue integrated circuits, measurement errors, decomposition technique |
23 | S. K. Gupta, M. M. Hasan |
KANSYS: a CAD tool for analog circuit synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 333-334, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
KANSYS, analog circuit synthesis, knowledge intensive hierarchical design, transistor circuit designs, functional circuits, knowledge based systems, hierarchy, integrated circuit design, circuit CAD, CAD tool, analogue integrated circuits, design knowledge, process specifications |
23 | V. C. Prasad, N. Sarat Chandra Babu |
On minimal set of test nodes for fault dictionary of analog circuit fault diagnosis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 7(3), pp. 255-258, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
test nodes, analog circuits, fault dictionary |
23 | Giri Devarayanadurg, Mani Soma |
Dynamic test signal design for analog ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 627-630, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
minmax, optimization, test, dynamic, analog, time-domain |
23 | Lars Hedrich, Erich Barke |
A formal approach to nonlinear analog circuit verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 123-127, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
analog nonlinear circuits, formal verification, functional verification, electronic design automation, behavioral description |
23 | S. R. Kadivar, Doris Schmitt-Landsiedel, Heinrich Klar |
A new algorithm for the design of stable higher order single loop sigma delta analog-to-digital converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 554-561, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
SD ADC, convertors, network scaling, nonlinear interactive optimization, performance criteria, sigma delta analog-to-digital converters, single loop, CAD, higher order, analogue-digital conversion, electronic engineering computing |
23 | Chauchin Su, Shenshung Chiang, Shyh-Jye Jou |
Impulse response fault model and fault extraction for functional level analog circuit diagnosis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 631-636, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Testing, Diagnosis, Analog Circuit |
23 | Tonia G. Morris, Denise M. Wilson, Stephen P. DeWeerth |
Analog VLSI circuits for manufacturing inspection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 241-257, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
analog VLSI circuits, manufacturing inspection, programmable structuring elements, oriented edge detection, high speed preprocessors, serial/parallel processing, focal-plane processing, vertical bipolar phototransistors, digital CMOS process, adaptive image threshold, 2.0 micron, computer vision, VLSI, edge detection, mathematical morphology, machine vision, manufacture, morphological operations, selective attention, massively parallel architectures, CMOS analogue integrated circuits, automatic optical inspection, focal planes, analogue processing circuits |
23 | Michael Goedecke, Sorin A. Huss, Kai Morich |
Automatic Parallelization of the Visual Data-Flow Language Cantata for Efficient Characterization of Analog Circuit Behavior. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VL ![In: Proceedings 11th International IEEE Symposium on Visual Languages, Darmstadt, Germany, September 5-9, 1995, pp. 69-76, 1995, IEEE Computer Society, 0-8186-7045-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
engineering workstations, Cantata visual data-flow language, analog circuit behavior characterisation, application specific functions, execution time reduction, data-flow scheduler, usable workstations, usable workstation performance, program availability, fully automated process, simulation, computational complexity, load balancing, parallel programming, resource allocation, visual languages, digital simulation, processor scheduling, circuit analysis computing, workloads, automatic parallelization, parallel languages, distributed environment, workstations, analogue circuits, control operators |
23 | Ashok Balivada, Yatin Vasant Hoskote, Jacob A. Abraham |
Verification of transient response of linear analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 42-47, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
linear network analysis, circuit behavior, operational amplifier macro circuits, input waveforms, extracted state equations, Z-domain, digital representation, finite state machines, active networks, transfer functions, transfer function, transient analysis, operational amplifiers, frequency-domain analysis, formal techniques, state-space methods, analogue circuits, transient response, transient response, linear analog circuits, equivalent circuits |
23 | Khaled Saab 0001, Bozena Kaminska, Bernard Courtois, Marcelo Lubaszewski |
Frequency-based BIST for analog circuit testin. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 54-59, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
waveform generators, frequency-based BIST, analog circuit testing, sine wave generator, sinusoidal input signals, variable frequency input stimulus, frequency input signal, T-BIST approach, frequency-counter BIST approach, VLSI, VLSI, built-in self test, integrated circuit testing, analogue integrated circuits |
23 | Janusz A. Starzyk, Hong Dai |
A decomposition approach for testing large analog networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(3), pp. 181-195, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
circuit decomposition, large system identification, Analog testing, test programming |
23 | Subhajit Ray, Peter R. Kinget |
Ultra-Low-Power and Compact-Area Analog Audio Feature Extraction Based on Time-Mode Analog Filterbank Interpolation and Time-Mode Analog Rectification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 58(4), pp. 1025-1036, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
23 | Subhajit Ray, Peter R. Kinget |
A 31-Feature, 80nW, 0.53mm2 Audio Analog Feature Extractor based on Time-Mode Analog Filterbank Interpolation and Time-Mode Analog Rectification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Technology and Circuits ![In: IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), Honolulu, HI, USA, June 12-17, 2022, pp. 184-185, 2022, IEEE, 978-1-6654-9772-5. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Jin-O. Seo, Mingoo Seok, SeongHwan Cho |
ARCHON: A 332.7TOPS/W 5b Variation-Tolerant Analog CNN Processor Featuring Analog Neuronal Computation Unit and Analog Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: IEEE International Solid-State Circuits Conference, ISSCC 2022, San Francisco, CA, USA, February 20-26, 2022, pp. 258-260, 2022, IEEE, 978-1-6654-2800-2. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Rahul Bhattacharya, Santosh Biswas, Siddhartha Mukhopadhyay |
FPGA based chip emulation system for test development and verification of analog and mixed signal circuits (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 284, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
ams testing, concurrent test development, behavioral modeling |
22 | Nguyen Thien Hoang, Hoang Duong Tuan, Truong Q. Nguyen, Hung Gia Hoang |
Optimized Analog Filter Designs With Flat Responses by Semidefinite Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 57(3), pp. 944-955, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
22 | Laurent Gatet, Hélène Tap-Béteille, Francis Bony |
Comparison Between Analog and Digital Neural Network Implementations for Range-Finding Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Neural Networks ![In: IEEE Trans. Neural Networks 20(3), pp. 460-470, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
22 | Kyung-Joong Kim 0001, Sung-Bae Cho |
Combining Multiple Evolved Analog Circuits for Robust Evolvable Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IDEAL ![In: Intelligent Data Engineering and Automated Learning - IDEAL 2009, 10th International Conference, Burgos, Spain, September 23-26, 2009. Proceedings, pp. 359-367, 2009, Springer, 978-3-642-04393-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
22 | Eddy Chiu, Paul Ho |
Transmit Beamforming with Analog Channel State Information Feedback. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Wirel. Commun. ![In: IEEE Trans. Wirel. Commun. 7(3), pp. 878-887, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Lihong Zhang, Nuttorn Jangkrajarng, Sambuddha Bhattacharya, C.-J. Richard Shi |
Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(5), pp. 791-802, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Vinod M. Prabhakaran, Rohit Puri, Kannan Ramchandran |
Colored Gaussian Source-Channel Broadcast for Heterogeneous (Analog/Digital) Receivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Theory ![In: IEEE Trans. Inf. Theory 54(4), pp. 1807-1814, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Marcello De Matteis, Stefano D'Amico, Andrea Baschirotto |
Advanced Analog Filters for Telecommunications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1316-1321, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann |
Sizing Rules for Bipolar Analog Circuit Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 140-145, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Sha Yao, Mikael Skoglund |
Dimension Compression Relaying for Slow Fading Channels Based on Hybrid Digital-Analog Source-Channel Coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICC ![In: Proceedings of IEEE International Conference on Communications, ICC 2008, Beijing, China, 19-23 May 2008, pp. 1103-1107, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Darius Grabowski, Markus Olbrich, Erich Barke |
Analog circuit simulation using range arithmetics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 762-767, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Martin Strasser, Michael Eick, Helmut Gräb, Ulf Schlichtmann, Frank M. Johannes |
Deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 306-313, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Mitra Mirhassani, Majid Ahmadi, Graham A. Jullien |
Robust analog neural network based on continuous valued number system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 1384-1387, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Joachim Becker, Fabian Henrici, Stanis Trendelenburg, Maurits Ortmanns, Yiannos Manoli |
A hexagonal Field Programmable Analog Array consisting of 55 digitally tunable OTAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 2897-2900, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Silvia Soldà, Daniele Vogrig, Andrea Bevilacqua, Andrea Gerosa, Andrea Neviani |
Analog decoding of trellis coded modulation for multi-level flash memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 744-747, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Tomonori Shirotori, Yuko Osana |
Kohonen feature map associative memory with area representation for sequential analog patterns. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IJCNN ![In: Proceedings of the International Joint Conference on Neural Networks, IJCNN 2008, part of the IEEE World Congress on Computational Intelligence, WCCI 2008, Hong Kong, China, June 1-6, 2008, pp. 818-823, 2008, IEEE, 978-1-4244-1820-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Claudio Mattiussi, Dario Floreano |
Analog Genetic Encoding for the Evolution of Circuits and Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Evol. Comput. ![In: IEEE Trans. Evol. Comput. 11(5), pp. 596-607, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Xin Li 0001, Padmini Gopalakrishnan, Yang Xu 0017, Lawrence T. Pileggi |
Robust Analog/RF Circuit Design With Projection-Based Performance Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(1), pp. 2-15, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Fang Liu 0029, Sule Ozev |
Statistical Test Development for Analog Circuits Under High Process Variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(8), pp. 1465-1477, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam |
A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: First International Symposium on Networks-on-Chips, NOCS 2007, 7-9 May 2007, Princeton, New Jersey, USA, Proceedings, pp. 173-182, 2007, IEEE Computer Society, 978-0-7695-2773-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Christer Svensson |
Analog Power Modelling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings, pp. 578, 2007, Springer, 978-3-540-74441-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Zhe Wang, Xiaolin Zhang 0002, Lei Chen |
Analog Error-Control Coding Based on Dimension-Expanding Shannon Mapping for Robust Image Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICME ![In: Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, ICME 2007, July 2-5, 2007, Beijing, China, pp. 723-726, 2007, IEEE Computer Society, 1-4244-1017-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Chi-Chang Lu, Jyun-Yi Wu, Tsung-Sum Lee |
A 1.5V 10-b 30-MS/s CMOS Pipelined Analog-to-Digital Converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1955-1958, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | David W. Graham, Paul E. Hasler |
Run-Time Programming of Analog Circuits Using Floating-Gate Transistors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 3816-3819, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Jeffrey Ayres, Michael L. Bushnell |
Analog Circuit Testing Using Auto Regressive Moving Average Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 775-780, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Anna Wang 0001, Junfang Liu, Hao Wang, Ran Tao |
A Novel Fault Diagnosis of Analog Circuit Algorithm Based on Incomplete Wavelet Packet Transform and Improved Balanced Binary-Tree SVMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LSMS (1) ![In: Bio-Inspired Computational Intelligence and Applications, International Conference on Life System Modeling and Simulation, LSMS 2007, Shanghai, China, September 14-17, 2007, Proceedings, pp. 482-493, 2007, Springer, 978-3-540-74768-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Mahmoud Taherzadeh, Amir K. Khandani |
Analog Coding for Delay-Limited Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CISS ![In: Proceedings of the 41st Annual Conference on Information Sciences and Systems, CISS 2007, 14-16 March 2007, Johns Hopkins University, Department of Electrical Engineering, Baltimore, MD, USA, pp. 101-106, 2007, IEEE, 1-4244-1037-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Osamu Nomura, Takashi Morie |
Projection-Field-Type VLSI Convolutional Neural Networks Using Merged/Mixed Analog-Digital Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICONIP (1) ![In: Neural Information Processing, 14th International Conference, ICONIP 2007, Kitakyushu, Japan, November 13-16, 2007, Revised Selected Papers, Part I, pp. 1081-1090, 2007, Springer, 978-3-540-69154-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
22 | Catherine Wideman, Jacqueline Gallet |
Analog to Digital Workflow Improvement: A Quantitative Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Digit. Imaging ![In: J. Digit. Imaging 19(S-1), pp. 29-34, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
radiology management, time study, Workflow, efficiency |
22 | Haralampos-G. D. Stratigopoulos, Yiorgos Makris |
Concurrent detection of erroneous responses in linear analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5), pp. 878-891, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Sheng-Jang Lin, I-Shun Chen, Bo-Wei Chen, Feng-Hsiang Lo |
The Design of Analog Front-End Circuitry for 1X HD-DVD PRML Read Channel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 128-132, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Joachim Becker, Yiannos Manoli |
Synthesis of Analog Filters on a Continuous-Time FPAA Using a Genetic Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-4, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Ginés Doménech-Asensi, Juan Martínez-Alajarín, Ramón Ruiz Merino, José-Alejandro López Alcantud |
Synthesis on FPAA of a Smart Sthetoscope Analog Subsystem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-5, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Erik Schüler, Luigi Carro |
Increasing analog programmability in SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Sorin A. Huss |
Analog circuit synthesis: a search for the Holy Grail? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Thomas Jacob Koickal, Alister Hamilton, Tim C. Pearce, Su-Lim Tan, James Anthony Covington, Julian W. Gardner |
Analog VLSI design of an adaptive neuromorphic chip for olfactory systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Baoyong Chi, Jinke Yao, Shuguang Han, Xiang Xie, Guolin Li, Zhihua Wang 0001 |
A 2.4GHz low power wireless transceiver analog front-end for endoscopy capsule system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Anthony S. Deese, Chika O. Nwankpa |
Emulation of power system load dynamic behavior through reconfigurable analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Takafumi Yamaji, Tetsuro Itakura, Rui Ito, Takeshi Ueno, Hidenori Okuni |
Balanced 3-phase analog signal processing for radio communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Anthony Kopa, Alyssa B. Apsel |
Common-emitter feedback transimpedance amplifier for analog optical receivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Rasit Onur Topaloglu |
Early, Accurate and Fast Yield Estimation through Monte Carlo-Alternative Probabilistic Behavioral Analog System Simulations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA, pp. 136-142, 2006, IEEE Computer Society, 0-7695-2514-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Tathagato Rai Dastidar, P. P. Chakrabarti 0001, Partha Ray |
A synthesis system for analog circuits based on evolutionary search and topological reuse. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Evol. Comput. ![In: IEEE Trans. Evol. Comput. 9(2), pp. 211-224, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Viera Stopjaková, Pavol Malosek, Marek Matej, Vladislav Nagy, Martin Margala |
Defect detection in analog and mixed circuits by neural networks using wavelet analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Reliab. ![In: IEEE Trans. Reliab. 54(3), pp. 441-448, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Sheldon X.-D. Tan, Weikun Guo, Zhenyu Qi |
Hierarchical approach to exact symbolic analysis of large analog circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(8), pp. 1241-1250, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Swarup Bhunia, Arijit Raychowdhury, Kaushik Roy 0001 |
Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(2), pp. 147-159, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Defect Oriented Testing (DOT), dynamic supply current (IDD), wavelet transform, Fourier transform |
22 | John Tuthill, Antonio Cantoni |
Efficient compensation for frequency-dependent errors in analog reconstruction filters used in IQ modulators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Commun. ![In: IEEE Trans. Commun. 53(3), pp. 489-496, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Guillermo Zatorre, Nicolás J. Medrano-Marqués, Santiago Celma, Bonifacio Martín-del-Brío, Antonio Bono-Nuez |
Smart Sensing with Adaptive Analog Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWANN ![In: Computational Intelligence and Bioinspired Systems, 8th International Work-Conference on Artificial Neural Networks, IWANN 2005, Vilanova i la Geltrú, Barcelona, Spain, June 8-10, 2005, Proceedings, pp. 463-470, 2005, Springer, 3-540-26208-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Huiying Yang, Anuradha Agarwal, Ranga Vemuri |
Fast Analog Circuit Synthesis Using Multiparameter Sensitivity Analysis Based on Element-Coefficient Diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA, pp. 71-76, 2005, IEEE Computer Society, 0-7695-2365-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Kaiping Zeng, Sorin A. Huss |
RAMS: A VHDL-AMS Code Refactoring Tool Supporting High Level Analog Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA, pp. 266-267, 2005, IEEE Computer Society, 0-7695-2365-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Fang Liu 0029, Jacob J. Flomenberg, Devaka V. Yasaratne, Sule Ozev |
Hierarchical Variance Analysis for Analog Circuits Based on Graph Modelling and Correlation Loop Tracing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 126-131, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Charlotte Soens, Geert Van der Plas, Piet Wambacq, Stéphane Donnay |
Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 270-275, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | A. William Stoffel |
An Agent Based Hybrid Analog-Digital Robotic Sensor Web Meta-system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WRAC ![In: Innovative Concepts for Autonomic and Agent-Based Systems, Second International Workshop on Radical Agent Concepts, WRAC 2005, Greenbelt, MD, USA, September 20-22, 2005. Revised Papers, pp. 281-285, 2005, Springer, 978-3-540-69265-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Fang Liu 0029, Sule Ozev |
Fast Hierarchical Process Variability Analysis and Parametric Test Development for Analog/RF Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 161-170, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Dylan R. Muir, Giacomo Indiveri, Rodney J. Douglas |
Form specifies function: robust spike-based computation in analog VLSI without precise synaptic weights. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5150-5153, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Mladen Panovic, Andreas Demosthenous |
Architectures for analog motion estimation processors: a comparison. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 4566-4569, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | David Haley, Chris Winstead, Vincent C. Gaudet, Alex J. Grant, Christian Schlegel |
An analog/digital mode-switching LDPC codec. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5790-5793, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya |
Analog CMOS implementation of a neuromorphic oscillator with current-mode low-pass filters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1923-1926, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Raoul F. Badaoui, Ranga Vemuri |
Analog VLSI circuit-level synthesis using multi-placement structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5978-5981, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Mladen Panovic, Andreas Demosthenous |
A low power block-matching analog motion estimation processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 4827-4830, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Adão Antônio de Souza Jr., Luigi Carro, Jawad Tousaad |
Adaptive processing applied to the design of highly digital analog interfaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 5597-5600, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | A. L. Dalcastangê, Sidnei Noceti Filho |
On the analog generation of pink noise from white noise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1944-1947, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Shinya Okuda, Shigeo Kaneda, Hirohide Haga |
Human Position/Height Detection Using Analog Type Pyroelectric Sensors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC Workshops ![In: Embedded and Ubiquitous Computing - EUC 2005 Workshops, EUC 2005 Workshops: UISW, NCUS, SecUbiq, USN, and TAUES, Nagasaki, Japan, December 6-9, 2005, Proceedings, pp. 306-315, 2005, Springer, 3-540-30803-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Yu Liu, Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita |
System level design language extensions for timed/untimed digital-analog combined system design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 130-133, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
AMS extension, timed/untimed, synchronization, system level design, mixed-signal |
22 | Giuseppe Trautteur |
Beyond the Super-Turing Snare: Analog Computation and Digital Virtuality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CiE ![In: New Computational Paradigms, First Conference on Computability in Europe, CiE 2005, Amsterdam, The Netherlands, June 8-12, 2005, Proceedings, pp. 507-514, 2005, Springer, 3-540-26179-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
22 | Reza Asgary, Karim Mohammadi |
Analog Fault Detection Using a Neuro Fuzzy Pattern Recognition Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICANN (2) ![In: Artificial Neural Networks: Formal Models and Their Applications - ICANN 2005, 15th International Conference, Warsaw, Poland, September 11-15, 2005, Proceedings, Part II, pp. 893-898, 2005, Springer, 3-540-28755-8. The full citation details ...](Pics/full.jpeg) |
2005 |
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