Search results for "instruction"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
28	T. N. Vijaykumar, Irith Pomeranz, Karl Cheng	Transient-Fault Recovery Using Simultaneous Multithreading.	ISCA	2002	DBLP DOI BibTeX RDF
28	Yuan Xie 0001, Wayne H. Wolf, Haris Lekatsas	A code decompression architecture for VLIW processors.	MICRO	2001	DBLP DOI BibTeX RDF
28	Craig B. Zilles, Gurindar S. Sohi	Understanding the backward slices of performance degrading instructions.	ISCA	2000	DBLP DOI BibTeX RDF
28	William E. Dougherty, David J. Pursley, Donald E. Thomas	Subsetting Behavioral Intellectual Property for Low Power ASIP Design.	J. VLSI Signal Process.	1999	DBLP DOI BibTeX RDF
28	Andreas Moshovos, Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi	Dynamic Speculation and Synchronization of Data Dependences.	ISCA	1997	DBLP DOI BibTeX RDF
27	M'hammed Abdous, Miki Yoshimura	Learner outcomes and satisfaction: A comparison of live video-streamed instruction, satellite broadcast instruction, and face-to-face instruction.	Comput. Educ.	2010	DBLP DOI BibTeX RDF
27	Nikolaos Vernadakis, Andreas Avgerinos, Eleni Zetou, Maria Giannousi, Efthimis Kioumourtzoglou	Comparsion of Multimedia Computer Assisted Instruction, Traditional Instruction and Combined Instruction on Learning the Skills of Long Jump.	Int. J. Comput. Sci. Sport	2006	DBLP BibTeX RDF
27	Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	Adapting instruction level parallelism for optimizing leakage in VLIW architectures.	LCTES	2003	DBLP DOI BibTeX RDF	power supply gating, instruction level parallelism, instruction scheduling, VLIW architecture, leakage energy, functional units
27	Baruch Solomon, Avi Mendelson, Doron Orenstein, Yoav Almog, Ronny Ronen	Micro-operation cache: a power aware frontend for the variable instruction length ISA.	ISLPED	2001	DBLP DOI BibTeX RDF	micro-operation cache, instruction cache, instruction, power reduction
27	William Y. Chen, Pohua P. Chang, Thomas M. Conte, Wen-mei W. Hwu	The Effect of Code Expanding Optimizations on Instruction Cache Design.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	code expanding optimizations, instruction placement, function inline expansion, superscalar optimizations, small caches, medium caches, load forwarding, large caches, C compiler, code expansion, optimisation, cache memory, memory architecture, buffer storage, instruction cache, code optimization, cache design, miss ratio
27	Michael J. Flynn, John D. Johnson, Scott P. Wakefield	On Instruction Sets and Their Formats.	IEEE Trans. Computers	1985	DBLP DOI BibTeX RDF	execution architecture, instruction format, Computer architecture, instruction set, program representation
27	Lorrie Lawrence Hoffman	Test gen: A tool for emancipation from traditional instruction.	ACM Annual Conference (2)	1978	DBLP DOI BibTeX RDF	Individualized instruction, Computer-assisted instruction
27	Walter A. Helbig, Veljko M. Milutinovic	A DCFL E/D-MESFET GaAs Experimental RISC Machine.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	RCA, DCFL E/D-MESFET, RISC machine, GaAs microprocessor, instruction execution sequence, III-V semiconductors, microprocessor chips, instruction set architecture, software environment, reduced instruction set computing, 32 bit, field effect integrated circuits, gallium arsenide
26	Andhi Janapsatya, Aleksandar Ignjatovic, Sri Parameswaran, Jörg Henkel	Instruction trace compression for rapid instruction cache simulation.	DATE	2007	DBLP DOI BibTeX RDF
26	Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Francky Catthoor, Henk Corporaal	Instruction buffering exploration for low energy VLIWs with instruction clusters.	ASP-DAC	2004	DBLP DOI BibTeX RDF
26	Joshua J. Yi, Resit Sendag, David J. Lilja	Increasing Instruction-Level Parallelism with Instruction Precomputation (Research Note).	Euro-Par	2002	DBLP DOI BibTeX RDF
26	Koji Inoue, Vasily G. Moshnyaga, Kazuaki J. Murakami	Reducing power consumption of instruction ROMs by exploiting instruction frequency.	APCCAS (2)	2002	DBLP DOI BibTeX RDF
26	Zhimin Chen 0002, Richard Neil Pittman, Alessandro Forin	Combining multicore and reconfigurable instruction set extensions.	FPGA	2010	DBLP DOI BibTeX RDF	extensible microprocessors, reconfigurable instruction set extensions, embedded, multi-core
26	Christopher D. Hundhausen, Anukrati Agrawal, Dana Fairbrother, Michael Trevisan	Does studio-based instruction work in CS 1?: an empirical comparison with a traditional approach.	SIGCSE	2010	DBLP DOI BibTeX RDF	pedagogical code review, studio-based learning and instruction, cs1, peer review, code inspection
26	Teemu Pitkänen, Jarno K. Tanskanen, Risto Mäkinen, Jarmo Takala	Parallel Memory Architecture for Application-Specific Instruction-Set Processors.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	TTA, Transport triggered architecture, Low power, ASIP, Application-specific instruction-set processors, Parallel memory
26	Demid Borodin, Ben H. H. Juurlink, Said Hamdioui, Stamatis Vassiliadis	Instruction-Level Fault Tolerance Configurability.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Instruction-level configurability, Fault tolerance, Performance, Reliability, Energy consumption
26	Seungrok Jung, Jungsoo Kim, Sangkwon Na, Chong-Min Kyung	Energy-aware instruction-set customization for real-time embedded multiprocessor systems.	ISLPED	2009	DBLP DOI BibTeX RDF	DVFS, instruction set extensions, configurable processors
26	Sheng-Hui Hsu, Shu-Chen Cheng, Yueh-Min Huang	The Experience of Adopting Game-Based Learning in Library Instruction.	Edutainment	2009	DBLP DOI BibTeX RDF	library instruction, educational game, Game-based learning
26	Suresh K. Bhavnani, Frederick A. Peck, Frederick Reif	Strategy-Based Instruction: Lessons Learned in Teaching the Effective and Efficient Use of Computer Applications.	ACM Trans. Comput. Hum. Interact.	2008	DBLP DOI BibTeX RDF	strategy-based instruction, training, teaching, Strategies
26	Peter Rounce, Alberto Ferreira de Souza	Dynamic Instruction Scheduling in a Trace-based Multi-threaded Architecture.	Int. J. Parallel Program.	2008	DBLP DOI BibTeX RDF	Simultaneous multi-threading, Wide issue architectures, VLIW, Dynamic instruction scheduling
26	Abid M. Malik, Tyrel Russell, Michael Chase, Peter van Beek	Learning heuristics for basic block instruction scheduling.	J. Heuristics	2008	DBLP DOI BibTeX RDF	List scheduling heuristics, Machine learning, Instruction scheduling
26	Katherine E. Coons, Behnam Robatmili, Matthew E. Taylor, Bertrand A. Maher, Doug Burger, Kathryn S. McKinley	Feature selection and policy optimization for distributed instruction placement using reinforcement learning.	PACT	2008	DBLP DOI BibTeX RDF	compiler heuristics, genetic algorithms, neural networks, machine learning, instruction scheduling
26	Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon	Speculative DMA for architecturally visible storage in instruction set extensions.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	architecturally visible storage, speculative direct memory access, instruction set extensions, application-specific processors
26	Maziar Goudarzi, Tohru Ishihara	Instruction cache leakage reduction by changing register operands and using asymmetric sram cells.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	asymmetric sram, leakage, instruction cache, register renaming
26	Toshinori Sato, Shingo Watanabe	Instruction Scheduling for Variation-Originated Variable Latencies.	ISQED	2008	DBLP DOI BibTeX RDF	variable latency adder, long latency adder, instruction criticality, microprocessors, parameter variations
26	Hangpei Tian, Deyuan Gao, Deli Wang, Yian Zhu, Shengbing Zhang, Jing Wang	Dynamically Reconfigurable Instruction Set for Software Radio Encoding/Coding.	MUE	2008	DBLP DOI BibTeX RDF	Instruction Set, Software Radio
26	Eui-Young Chung, Cheol Hong Kim, Sung Woo Chung	An Accurate and Energy-Efficient Way Determination Technique for Instruction Caches by Early Tab Matching.	DELTA	2008	DBLP DOI BibTeX RDF	way predictioin, low power, Instruction cache
26	Guilherme Ottoni, David I. August	Communication optimizations for global multi-threaded instruction scheduling.	ASPLOS	2008	DBLP DOI BibTeX RDF	graph min-cut, communication, synchronization, data-flow analysis, multi-threading, instruction scheduling
26	Chung-Ho Chen, Kuo-Su Hsiao	Scalable Dynamic Instruction Scheduler through Wake-Up Spatial Locality.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	CAM-based wakeup logic, matrix-based wakeup logic, scalable instruction scheduler, wakeup spatial locality, low power, issue logic
26	Yiyu Tan, Anthony S. Fong, Xiaojian Yang	An Instruction Folding Solution to a Java Processor.	NPC	2007	DBLP DOI BibTeX RDF	Instruction folding, Java virtual machine, Bytecode, Java processor
26	Orna Muller, David Ginat, Bruria Haberman	Pattern-oriented instruction and its influence on problem decomposition and solution construction.	ITiCSE	2007	DBLP DOI BibTeX RDF	algorithmic patterns, pattern-oriented instruction, problem solving, problem decomposition
26	Huynh Phung Huynh, Joon Edward Sim, Tulika Mitra	An efficient framework for dynamic reconfiguration of instruction-set customization.	CASES	2007	DBLP DOI BibTeX RDF	dynamic reconfiguration, instruction-set extensions, temporal partitioning, customizable processors
26	Gang Li 0016, Kin-Hong Lee, Kwong-Sak Leung	Using Instruction Matrix Based Genetic Programming to Evolve Programs.	ISICA	2007	DBLP DOI BibTeX RDF	Instruction Matrix based Genetic Programming, Genetic Programming
26	Carlo Galuzzi, Elena Moscu Panainte, Yana Yankova, Koen Bertels, Stamatis Vassiliadis	Automatic selection of application-specific instruction-set extensions.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	reconfigurable computing, instruction-set extension, HW/SW codesign
26	M. Anton Ertl, Kevin Casey, David Gregg	Fast and flexible instruction selection with on-demand tree-parsing automata.	PLDI	2006	DBLP DOI BibTeX RDF	tree parsing, dynamic programming, automaton, lazy, instruction selection
26	Jason E. Miller, Anant Agarwal	Software-based instruction caching for embedded processors.	ASPLOS	2006	DBLP DOI BibTeX RDF	instruction cache, chaining, software caching
26	Partha Biswas, Nikil D. Dutt	Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	DSP, VLIW, ASIP, Coprocessors, instruction set extensions, code size reduction
26	Ismail Kadayif, Anand Sivasubramaniam, Mahmut T. Kandemir, Gokul B. Kandiraju, Guangyu Chen	Optimizing instruction TLB energy using software and hardware techniques.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	instruction locality, translation look-aside buffer, Power consumption, compiler optimization, cache design
26	Chuanjun Zhang	An efficient direct mapped instruction cache for application-specific embedded systems.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	efficient cache design, instruction cache, low power cache
26	GuangWei Zou, Xiang Liu	An Efficient Approach to Custom Instruction Set Generation.	RTCSA	2005	DBLP DOI BibTeX RDF	Major Block, Profiling, Hardware Acceleration, ASIPs, Custom Instruction
26	ZhiLei Chai, ZhiQiang Tang, LiMing Wang, Shi-liang Tu	An Effective Instruction Optimization Method for Embedded Real-Time Java Processor.	ICPP Workshops	2005	DBLP DOI BibTeX RDF	Embedded Real-time Java Processor, Instruction Optimization, WCET (Worst Case Execution Time), Java Processor
26	Suman Mamidi, Emily R. Blem, Michael J. Schulte, C. John Glossner, Daniel Iancu, Andrei Iancu, Mayan Moudgill, Sanjay Jinturkar	Instruction set extensions for software defined radio on a multithreaded processor.	CASES	2005	DBLP DOI BibTeX RDF	convolutional encoding, multithreading, forward error correction, software defined radio, Reed-Solomon coding, instruction set extensions, digital signal processor, Viterbi decoding, turbo decoding
26	Roshan G. Ragel, Sri Parameswaran, Sayed Mohammad Kia	Micro embedded monitoring for security in application specific instruction-set processors.	CASES	2005	DBLP DOI BibTeX RDF	micro embedded monitoring, microinstructions, self-monitoring instructions, application specific instruction-set processors, security monitoring
26	Stefan Tillich, Johann Großschädl	Accelerating AES Using Instruction Set Extensions for Elliptic Curve Cryptography.	ICCSA (2)	2005	DBLP DOI BibTeX RDF	32-bit implementation, software acceleration, Advanced Encryption Standard, Rijndael, instruction set extensions
26	Soong Hyun Shin, Cheol Hong Kim, Chu Shik Jhon	An Effective Instruction Cache Prefetch Policy by Exploiting Cache History Information.	EUC	2005	DBLP DOI BibTeX RDF	Computer architecture, embedded processor, instruction cache, cache prefetching
26	Partha Biswas, Vinay Choudhary, Kubilay Atasu, Laura Pozzi, Paolo Ienne, Nikil D. Dutt	Introduction of local memory elements in instruction set extensions.	DAC	2004	DBLP DOI BibTeX RDF	ad-hoc functional units, genetic algorithm, ASIPs, coprocessors, instruction set extensions, customizable processors
26	Kubilay Atasu, Laura Pozzi, Paolo Ienne	Automatic Application-Specific Instruction-Set Extensions Under Microarchitectural Constraints.	Int. J. Parallel Program.	2003	DBLP DOI BibTeX RDF	customisable processors, automatic partitioning, hardware/software codesign, instruction-set extensions
26	Jude A. Rivers, Sameh W. Asaad, John-David Wellman, Jaime H. Moreno	Reducing instruction fetch energy with backwards branch control information and buffering.	ISLPED	2003	DBLP DOI BibTeX RDF	loop buffer, low-power, instruction fetch
26	Yi Zhang, Steve Haga, Rajeev Barua	Execution history guided instruction prefetching.	ICS	2002	DBLP DOI BibTeX RDF	performance, prefetching, hardware, instruction cache
26	Tejas Karkhanis, James E. Smith 0001, Pradip Bose	Saving energy with just in time instruction delivery.	ISLPED	2002	DBLP DOI BibTeX RDF	adaptive processor, low-power, instruction delivery
26	John Kalamatianos, Alireza Khalafi, David R. Kaeli, Waleed Meleis	Analysis of Temporal-Based Program Behavior for Improved Instruction Cache Performance.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	program reordering, graph pruning, graph coloring, Instruction caches, temporal locality, conflict misses
26	Steven Wallace, Nader Bagherzadeh	Modeled and Measured Instruction Fetching Performance for Superscalar Microprocessors.	IEEE Trans. Parallel Distributed Syst.	1998	DBLP DOI BibTeX RDF	performance analysis, Computer architecture, instruction fetching, branch target buffer, superscalar microprocessor
26	Hiroyuki Tomiyama, Tohru Ishihara, Akihiko Inoue, Hiroto Yasuura	Instruction Scheduling for Power Reduction in Processor-Based System Design.	DATE	1998	DBLP DOI BibTeX RDF	Caches, Low-Power Design, Instruction Scheduling
26	Jack L. Lo, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Rebecca L. Stamm, Dean M. Tullsen	Converting Thread-Level Parallelism to Instruction-Level Parallelism via Simultaneous Multithreading.	ACM Trans. Comput. Syst.	1997	DBLP DOI BibTeX RDF	multiprocessors, multithreading, instruction-level parallelism, thread-level parallelism, simultaneous multithreading, cache interference
26	Pradip Bose, B. Ramakrishna Rau, Michael S. Schlansker	Systematically derived instruction sets for high-level language support.	ACM Southeast Regional Conference	1982	DBLP DOI BibTeX RDF	directly interpretable languages, space-time efficiency, syntax and semantics, compilation, interpretation, high-level languages, semantic gap, instruction set design
26	Virginia Escuder, Raúl Durán, Rafael Rico	Analysis of x86 ISA Condition Codes Influence on Superscalar Execution.	HiPC	2007	DBLP DOI BibTeX RDF	Condition codes, Graph theory, Instruction level parallelism, Instruction set architecture
26	Georgi Gaydadjiev, Stamatis Vassiliadis	SCISM vs IA-64 Tagging: Differences/Code Density Effects.	Euro-Par	2004	DBLP DOI BibTeX RDF	Instruction Tagging, SCISM, Instruction Level Parallelism, IA-64
26	Christoph W. Keßler, Andrzej Bednarski	Optimal integrated code generation for clustered VLIW architectures.	LCTES-SCOPES	2002	DBLP DOI BibTeX RDF	integrated code generation, space profile, dynamic programming, register allocation, instruction scheduling, instruction selection
26	Aneesh Aggarwal, Manoj Franklin	Hierarchical Interconnects for On-Chip Clustering.	IPDPS	2002	DBLP DOI BibTeX RDF	on-chip clustering, instruction distribution algo-rithms, Scalability, on-chip interconnect, Instruction-level parallelism (ILP)
26	Phillip Stanley-Marbell, Liviu Iftode	Scylla: a smart virtual machine for mobile embedded systems.	WMCSA	2000	DBLP DOI BibTeX RDF	Scylla, smart virtual machine, mobile embedded systems, virtualized processor architecture, inter-device communication, mobile computing, embedded systems, wireless LAN, virtual machines, power management, embedded processors, error recovery, instruction sets, instruction set, prototype system, code mobility, wireless devices
26	Shlomit S. Pinter, Adi Yoaz	Tango: A Hardware-Based Data Prefetching Technique for Superscalar Processors.	MICRO	1996	DBLP DOI BibTeX RDF	LRU mechanism, SPEC92 benchmark, Tango, base line architecture, hardware-based data prefetching technique, memory reference instructions, program progress graph, performance, parallel processing, instruction level parallelism, simulation results, superscalar processors, branch target buffer, instruction prefetching, hardware resources, slack time
26	Tai-Yi Huang, Jane W.-S. Liu, David Hull	A Method for Bounding the Effect of DMA I/O Interference on Program Execution Time.	RTSS	1996	DBLP DOI BibTeX RDF	DMA I/O operation, program execution time, DMA controller, cycle-stealing mode, bus cycles, cycle stealing operation, executing program, machine instruction, instruction-cache architectures, input output operation, simulations, real-time systems, worst-case execution time, data transfer
26	Sung-Kwan Kim, Sang Lyul Min, Rhan Ha	Efficient worst case timing analysis of data caching.	IEEE Real Time Technology and Applications Symposium	1996	DBLP DOI BibTeX RDF	efficient worst case timing analysis, accurate timing analysis, pipelined execution, multiple memory locations, pointer based references, dynamic load/store instructions, WCET overestimation, global data flow analysis, benchmark programs, real-time systems, computational complexity, data caching, cache storage, instruction sets, reduced instruction set computing, data dependence analysis, cache block
26	Clifford Liem, Pierre G. Paulin, Marco Cornero, Ahmed Amine Jerraya	Industrial experience using rule-driven retargetable code generation for multimedia applications.	ISSS	1995	DBLP DOI BibTeX RDF	VideoPhone codec controller, audio telecommunications, dedicated compiler availability, high-fidelity audio, optimization abilities, rule-driven retargetable code generation, video telecommunications, knowledge based systems, computer architecture, multiprocessing systems, multimedia systems, application specific integrated circuits, multimedia applications, application-specific instruction set processors, instruction sets, telecommunication computing, codecs, VLIW processor, VLIW architecture, transformation rules, controller architecture, optimising compilers, industrial experience, videotelephony, target architecture, MPEG audio
26	Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita	Power analysis and low-power scheduling techniques for embedded DSP software.	ISSS	1995	DBLP DOI BibTeX RDF	circuit state, embedded DSP software, general-purpose commercial microprocessors, instruction-level power model, measurement based power analysis, micro-architectural power model, on-chip Booth multiplier, scheduling, real-time systems, application specific integrated circuits, energy consumption, scheduling algorithm, power analysis, energy minimization, circuit CAD, digital signal processing chips, instruction sets, energy reduction, low-power scheduling, DSP processor
26	William F. Richardson, Erik Brunvand	Precise exception handling for a self-timed processor.	ICCD	1995	DBLP DOI BibTeX RDF	precise exception handling, self-timed processor, multiple concurrent processes, self-timed queues, decoupled computer architectures, micropipelined processor, Fred, pipelined computer architecture, out-of-order instruction completion, parallel architectures, exception handling, instruction level parallelism, self-adjusting systems, self-timed systems
26	Lorrie Fava Lindon, Selim G. Akl	An Optimal Implementation of Broadcasting with Selective Reduction.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	optimal implementation, broadcasting with selective reduction, concurrent-read concurrent-write, concurrentmemory access, BROADCAST instruction, memory locations, parallel computation, parallel random access machine, PRAM, instruction sets, random-access storage, parallelalgorithms
26	Sanjay Ranka, Sartaj Sahni	Clustering on a Hypercube Multicomputer.	IEEE Trans. Parallel Distributed Syst.	1991	DBLP DOI BibTeX RDF	square error, clustering problem, NMK processors, multiple-data, parallel algorithms, computational complexity, hypercube networks, single-instruction multiple-data, SIMD, MIMD, hypercube multicomputer, multiple-instruction
25	George Xenoulis, Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis	Instruction-Based Online Periodic Self-Testing of Microprocessors with Floating-Point Units.	IEEE Trans. Dependable Secur. Comput.	2009	DBLP DOI BibTeX RDF
25	Cuiping Xu, Ge Zhang, Shouqing Hao	Fast Way-Prediction Instruction Cache for Energy Efficiency and High Performance.	NAS	2009	DBLP DOI BibTeX RDF
25	Marios Kleanthous, Yiannakis Sazeides	CATCH: A Mechanism for Dynamically Detecting Cache-Content-Duplication and its Application to Instruction Caches.	DATE	2008	DBLP DOI BibTeX RDF
25	Carlo Galuzzi, Koen Bertels	The Instruction-Set Extension Problem: A Survey.	ARC	2008	DBLP DOI BibTeX RDF
25	Yuan-Shin Hwang, Jia-Jhe Li	Snug set-associative caches: Reducing leakage power of instruction and data caches with no performance penalties.	ACM Trans. Archit. Code Optim.	2007	DBLP DOI BibTeX RDF	Caches, leakage power, drowsy caches, cache decay
25	Priya Nagpurkar, Harold W. Cain, Mauricio J. Serrano, Jong-Deok Choi, Chandra Krintz	Call-chain Software Instruction Prefetching in J2EE Server Applications.	PACT	2007	DBLP DOI BibTeX RDF
25	Michael Med, Andreas Krall	Instruction Set Encoding Optimization for Code Size Reduction.	ICSAMOS	2007	DBLP DOI BibTeX RDF
25	Miquel Pericàs, Adrián Cristal, Rubén González 0001, Daniel A. Jiménez, Mateo Valero	A decoupled KILO-instruction processor.	HPCA	2006	DBLP DOI BibTeX RDF
25	Nicolas Beucher, Normand Bélanger, Yvon Savaria, Guy Bois	Motion Compensated Frame Rate Conversion Using a Specialized Instruction Set Processor.	SiPS	2006	DBLP DOI BibTeX RDF
25	Tom Vander Aa, Murali Jayapala, Henk Corporaal, Francky Catthoor, Geert Deconinck	Instruction Transfer And Storage Exploration for Low Energy VLIWs.	SiPS	2006	DBLP DOI BibTeX RDF
25	Houman Homayoun, Ted H. Szymanski	Reducing the Instruction Queue Leakage Power in Superscalar Processors.	CCECE	2006	DBLP DOI BibTeX RDF
25	Zheng Shen, Hu He 0001, Yanjun Zhang, Yihe Sun	VS-ISA: A Video Specific Instruction Set Architecture for ASIP Design.	IIH-MSP	2006	DBLP DOI BibTeX RDF
25	Fei Sun, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Hybrid Custom Instruction and Co-Processor Synthesis Methodology for Extensible Processors.	VLSI Design	2006	DBLP DOI BibTeX RDF
25	Kang Zhao, Jinian Bian	A Clustering ILP Model for Fast Instruction Selection in Embedded Applicated Specific Processor Design.	APCCAS	2006	DBLP DOI BibTeX RDF
25	Tien-Fu Chen, Chia-Ming Hsu, S.-R. Wu	Flexible Heterogeneous Multicore Architectures for Versatile Media Processing Via Customized Long Instruction Words.	IEEE Trans. Circuits Syst. Video Technol.	2005	DBLP DOI BibTeX RDF
25	Cheol Hong Kim, Sung-Hoon Shim, Jong Wook Kwak, Sung Woo Chung, Chu Shik Jhon	First-Level Instruction Cache Design for Reducing Dynamic Energy Consumption.	SAMOS	2005	DBLP DOI BibTeX RDF
25	Stephen Hines, Gary S. Tyson, David B. Whalley	Reducing Instruction Fetch Cost by Packing Instructions into RegisterWindows.	MICRO	2005	DBLP DOI BibTeX RDF
25	Ahmad Zmily, Earl Killian, Christos Kozyrakis	Improving Instruction Delivery with a Block-Aware ISA.	Euro-Par	2005	DBLP DOI BibTeX RDF
25	Joseph J. Sharkey, Dmitry V. Ponomarev	Instruction Recirculation: Eliminating Counting Logic in Wakeup-Free Schedulers.	Euro-Par	2005	DBLP DOI BibTeX RDF
25	Ayose Falcón, Alex Ramírez, Mateo Valero	Effective Instruction Prefetching via Fetch Prestaging.	IPDPS	2005	DBLP DOI BibTeX RDF
25	Shu Xiao 0001, Edmund Ming-Kit Lai, A. Benjamin Premkumar	Rule-Based Power-Balanced VLIW Instruction Scheduling with Uncertainty.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
25	Masayuki Masuda, Kazuhito Ito	Rapid and precise instruction set evaluation for application specific processor design.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
25	Mohammad Mostafizur Rahman Mozumdar, Kingshuk Karuri, Anupam Chattopadhyay, Stefan Kraemer, Hanno Scharwächter, Heinrich Meyr, Gerd Ascheid, Rainer Leupers	Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study.	ASAP	2005	DBLP DOI BibTeX RDF
25	Siu-Kei Wong, Chi-Ying Tsui	Re-Configurable Bus Encoding Scheme for Reducing Power Consumption of the Cross Coupling Capacitance for Deep Sub-Micron Instruction Bus.	DATE	2004	DBLP DOI BibTeX RDF
25	Ravi V. Batchu, Daniel A. Jiménez	Exploiting Procedure Level Locality to Reduce Instruction Cache Misses.	Interaction between Compilers and Computer Architectures	2004	DBLP DOI BibTeX RDF
25	Aviral Shrivastava, Nikil D. Dutt	Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA).	ASP-DAC	2004	DBLP DOI BibTeX RDF
25	Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi	Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF