Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
11 | Christophe Jelger, Christian F. Tschudin |
Dynamic names and private address maps: complete self-configuration for MANETs. |
CoNEXT |
2006 |
DBLP DOI BibTeX RDF |
MANET self-configuration, name autoconfiguration, address autoconfiguration |
11 | Minsik Cho, David Z. Pan, Hua Xiang 0001, Ruchir Puri |
Wire density driven global routing for CMP variation and timing. |
ICCAD |
2006 |
DBLP DOI BibTeX RDF |
performance, VLSI, manufacturability, global routing |
11 | Pui-In Mak, Seng-Pan U., Rui Paulo Martins |
Design and test strategy underlying a low-voltage analog-baseband IC for 802.11a/b/g WLAN SiP receivers. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Taraneh Taghavi, Soheil Ghiasi, Majid Sarrafzadeh |
Routing algorithms: architecture driven rerouting enhancement for FPGAs. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Ali Hammad Akbar 0001, Ki-Hyung Kim, Won-Do Jung, Ali Kashif Bashir, Seung-Wha Yoo |
GARPAN: Gateway-Assisted Inter-PAN Routing for 6LoWPANs. |
ICCSA (2) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Shashidhar Mysore, Banit Agrawal, Navin Srivastava, Sheng-Chih Lin, Kaustav Banerjee, Timothy Sherwood |
Introspective 3D chips. |
ASPLOS |
2006 |
DBLP DOI BibTeX RDF |
3D Architectures, hardware support for profiling, introspection |
11 | Ravi Arora, Sachin Shrivastava |
Area Recovery by Abutted Cell Placement: Can Fillers be Killers? An Eye-opening Viewpoint! |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Charles J. Alpert, Andrew B. Kahng, Cliff C. N. Sze, Qinke Wang |
Timing-driven Steiner trees are (practically) free. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
arborescence, timing-driven, rectilinear Steiner tree |
11 | Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han |
Novel full-chip gridless routing considering double-via insertion. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
redundant via insertion, routing, manufacturability |
11 | Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang, Bo Yao |
The Y architecture for on-chip interconnect: analysis and methodology. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Ankur Srivastava 0001, Seda Ogrenci Memik, Bo-Kyung Choi, Majid Sarrafzadeh |
On effective slack management in postscheduling phase. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Puneet Gupta 0001, Andrew B. Kahng, Stefanus Mantik |
Routing-aware scan chain ordering. |
ACM Trans. Design Autom. Electr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
testing, Layout, scan chain |
11 | Jason Cong, Joseph R. Shinnerl, Min Xie 0004, Tim Kong, Xin Yuan 0005 |
Large-scale circuit placement. |
ACM Trans. Design Autom. Electr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
optimality, scalability, Placement, large-scale optimization |
11 | Deepak Rautela, Rajendra S. Katti |
Design and Implementation of FPGA Router for Efficient Utilization of Heterogeneous Routing Resources. |
ISVLSI |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Chao-Yang Yeh, Malgorzata Marek-Sadowska |
Skew-programmable clock design for FPGA and skew-aware placement. |
FPGA |
2005 |
DBLP DOI BibTeX RDF |
clock architecture, skew optimization, placement |
11 | Deepak Rautela, Rajendra S. Katti |
Efficient utilization of heterogeneous routing resources for FPGAs (abstract only). |
FPGA |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Petra Färm, Elena Dubrova, Andreas Kuehlmann |
Logic optimization using rule-based randomized search. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Chen Li 0004, Cheng-Kok Koh, Patrick H. Madden |
Floorplan management: incremental placement for gate sizing and buffer insertion. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
11 | David Varghese, J. Neil Ross |
A continuous-time hierarchical field programmable analogue array for rapid prototyping and hierarchical approach to analogue systems design. |
SBCCI |
2005 |
DBLP DOI BibTeX RDF |
HFPAA, differential difference amplifier, interconnectivity analysis, non-permuting grouped combinations listing algorithm, rents rule, second generation current-conveyor, hierarchical architecture, FPAA |
11 | Qinghua Liu, Malgorzata Marek-Sadowska |
Wire length prediction-based technology mapping and fanout optimization. |
ISPD |
2005 |
DBLP DOI BibTeX RDF |
prediction, congestion, wire length |
11 | Jarrod A. Roy, David A. Papa, Saurabh N. Adya, Hayward H. Chan, Aaron N. Ng, James F. Lu, Igor L. Markov |
Capo: robust and scalable open-source min-cut floorplacer. |
ISPD |
2005 |
DBLP DOI BibTeX RDF |
placement, physical design, floorplanning |
11 | Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang 0003, Hsin-Hsien Ho |
Modem floorplanning with abutment and fixed-outline constraints. |
ISCAS (6) |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Jingyu Xu, Xianlong Hong, Tong Jing |
Timing-driven global routing with efficient buffer insertion. |
ISCAS (3) |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Fei He 0001, William N. N. Hung, Xiaoyu Song, Ming Gu 0001, Jiaguang Sun 0001 |
Segmented channel routing with pin rearrangements via satisfiability. |
ISCAS (6) |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Seung-Yeon Lee, Eui-nam Huh, Sangbok Kim, Youngsong Mun |
An Efficient Performance Enhancement Scheme for Fast Mobility Service in MIPv6. |
ICCSA (1) |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Yang Yang 0040, Tong Jing, Xianlong Hong, Yu Hu 0002, Qi Zhu 0002, Xiaodong Hu 0001, Guiying Yan |
Via-Aware Global Routing for Good VLSI Manufacturability and High Yield. |
ASAP |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Tsung-Yi Ho, Chen-Feng Chang, Yao-Wen Chang, Sao-Jie Chen |
Multilevel full-chip routing for the X-based architecture. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
Xarchitecture, routing, physical design, multilevel optimization |
11 | Yao-Wen Chang, Shih-Ping Lin 0001 |
MR: a new framework for multilevel full-chip routing. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Tong Jing, Xianlong Hong, Jingyu Xu, Haiyun Bao, Chung-Kuan Cheng, Jun Gu |
UTACO: a unified timing and congestion optimization algorithm for standard cell global routing. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif |
A methodology for the simultaneous design of supply and signal networks. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Nicholas Weaver, John R. Hauser, John Wawrzynek |
The SFRA: a corner-turn FPGA architecture. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
FPGA CAD, FPGA design study, FPGA optimization, FPGA architecture |
11 | Tomasz S. Czajkowski, Jonathan Rose |
A synthesis oriented omniscient manual editor. |
FPGA |
2004 |
DBLP DOI BibTeX RDF |
virtex-e, synthesis, manual |
11 | Jing Huang 0001, Mehdi Baradaran Tahoori, Fabrizio Lombardi |
Fault Tolerance of Programmable Switch Blocks. |
DATE |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Yi-Hui Cheng, Yao-Wen Chang |
Integrating buffer planning with floorplanning for simultaneous multi-objective optimization. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada |
High speed layout synthesis for minimum-width CMOS logic cells via Boolean satisfiability. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Jin-Tai Yan, Shun-Hua Lin |
Timing-constrained congestion-driven global routing. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Andrea Lodi 0002, Roberto Giansante, Carlo Chiesa, Luca Ciccarelli, Fabio Campi, Mario Toma |
Compact Buffered Routing Architecture. |
FPL |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Alexander Danilin, Sergei Sawitzki |
Optimizing the Performance of the Simulated Annealing Based Placement Algorithms for Island-Style FPGAs. |
FPL |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Mircea R. Stan, Fatih Hamzaoglu, David Garrett |
Non-Manhattan maze routing. |
SBCCI |
2004 |
DBLP DOI BibTeX RDF |
Manhattan routing, multi-layer routing, non-Manhattan routing, global routing, local routing |
11 | Jing Huang 0001, Mehdi Baradaran Tahoori, Fabrizio Lombardi |
Probabilistic Analysis of Fault Tolerance of FPGA Switch Block Array. |
IPDPS |
2004 |
DBLP DOI BibTeX RDF |
fault tolerance, FPGA, routing, testing |
11 | Sami Khawam, Tughrul Arslan, Fred Westall |
Unidirectional Switch-Boxes for Synthesizable Reconfigurable Arrays. |
FCCM |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Miyoung Kim, Hyewon K. Lee, Youngsong Mun |
A Mutual Authentication and Route Optimization Method between MN and CN Using AAA in Mobile IPv6. |
International Conference on Computational Science |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Changnam Kim, Young Sin Kim, Eui-nam Huh, Youngsong Mun |
Performance Improvement in Mobile IPv6 Using AAA and Fast Handoff. |
ICCSA (1) |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Jing Huang 0001, Mehdi Baradaran Tahoori, Fabrizio Lombardi |
On the Defect Tolerance of Nano-Scale Two-Dimensional Crossbars. |
DFT |
2004 |
DBLP DOI BibTeX RDF |
|
11 | Victor N. Kravets, Prabhakar Kudva |
Implicit enumeration of structural changes in circuit optimization. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
optimization, decomposition, technology mapping, physical synthesis, re-synthesis |
11 | Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan |
Dynamic FPGA routing for just-in-time FPGA compilation. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
FPGA, dynamic optimization, system-on-a-chip, platforms, codesign, hardware/software partitioning, just-in-time compilation, configurable logic, place and route, warp processors |
11 | Andrew B. Kahng, Sherief Reda |
Placement feedback: a concept and method for better min-cut placements. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
min-cut placement, terminal propagation, feedback |
11 | Amit Singh 0001, Arindam Mukherjee 0001, Luca Macchiarulo, Malgorzata Marek-Sadowska |
PITIA: an FPGA for throughput-intensive applications. |
IEEE Trans. Very Large Scale Integr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Frank Schmiedle, Rolf Drechsler, Bernd Becker 0001 |
Exact Routing with Search Space Reduction. |
IEEE Trans. Computers |
2003 |
DBLP DOI BibTeX RDF |
forced cells, MDDs, Detailed routing, fixed point iteration |
11 | Hongbing Fan, Jiping Liu, Yu-Liang Wu |
General Models and a Reduction Design Technique for FPGA Switch Box Designs. |
IEEE Trans. Computers |
2003 |
DBLP DOI BibTeX RDF |
hyper-universal, FPGA, global routing, detailed routing, reduction technique, optimum design, switch box |
11 | Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung |
On optimal hyperuniversal and rearrangeable switch box designs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Faran Rafiq, Malgorzata Chrzanowska-Jeske, Hannah Honghua Yang, Marcin Jeske, Naveed A. Sherwani |
Integrated floorplanning with buffer/channel insertion for bus-based designs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Ulrich Brenner, André Rohe |
An effective congestion-driven placement framework. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Paul Villarrubia |
Important placement considerations for modern VLSI chips. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Fan Mo, Robert K. Brayton |
Fishbone: a block-level placement and routing scheme. |
ISPD |
2003 |
DBLP DOI BibTeX RDF |
routing, placement |
11 | Saurabh N. Adya, Igor L. Markov, Paul Villarrubia |
On Whitespace and Stability in Mixed-Size Placement and Physical Synthesis. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Jason Cong, Tim Kong, Joseph R. Shinnerl, Min Xie 0004, Xin Yuan 0005 |
Large-Scale Circuit Placement: Gap and Promise. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
Optimality, Scalability, Placement, Large-Scale Optimization |
11 | Seokjin Lee, Yongseok Cheon, Martin D. F. Wong |
A Min-Cost Flow Based Detailed Router for FPGAs. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
min-cost flow algorithm, Lagrangian relaxation, FPGA routing |
11 | Joachim Pistorius, Mike Hutton |
Placement rent exponent calculation methods, temporal behaviour and FPGA architecture evaluation. |
SLIP |
2003 |
DBLP DOI BibTeX RDF |
FPGA architecture, interconnect prediction, SLIP, rent |
11 | Eli Chiprout |
Early electrical wire projections and implications. |
SLIP |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Martijn T. Bennebroek |
Validation of wire length distribution models on commercial designs. |
SLIP |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Ameya R. Agnihotri, Patrick H. Madden |
Congestion reduction in traditional and new routing architectures. |
ACM Great Lakes Symposium on VLSI |
2003 |
DBLP DOI BibTeX RDF |
non-Manhattan design, congest, steiner trees, global routing |
11 | Puneet Gupta 0001, Andrew B. Kahng, Stefanus Mantik |
A Proposal for Routing-Based Timing-Driven Scan Chain Ordering. |
ISQED |
2003 |
DBLP DOI BibTeX RDF |
|
11 | Alireza Kaviani |
Using Design Hierarchy to Improve Quality of Results in FPGAs. |
FPL |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung |
On Optimum Designs of Universal Switch Blocks. |
FPL |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Xiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh |
Timing-driven placement using design hierarchy guided constraint generation. |
ICCAD |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Shankar Balachandran, PariVallal Kannan, Dinesh Bhatia |
On Routing Demand and Congestion Estimation for FPGAs. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita |
Chip size estimation based on wiring area. |
APCCAS (2) |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Shuenn-Shi Chen, Wang-Dauh Tseng, Jin-Tai Yan, Sao-Jie Chen |
Printed circuit board routing and package layout codesign. |
APCCAS (1) |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Haihua Su, Jiang Hu, Sachin S. Sapatnekar, Sani R. Nassif |
Congestion-driven codesign of power and signal networks. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
signal routing, wire congestion, codesign, power grid noise |
11 | Abhishek Ranjan, Kia Bazargan, Seda Ogrenci, Majid Sarrafzadeh |
Fast floorplanning for effective prediction and construction. |
IEEE Trans. Very Large Scale Integr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Prashant Saxena, C. L. Liu 0001 |
Optimization of the maximum delay of global interconnects duringlayer assignment. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Jason Cong, Jie Fang, Kei-Yong Khoo |
DUNE-a multilayer gridless routing system. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Shih-Chieh Chang, Zhong-Zhen Wu |
Theorems and extensions of single wire replacement. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Yao-Wen Chang, Jai-Ming Lin, Martin D. F. Wong |
Matching-based algorithm for FPGA channel segmentation design. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Guy G. Lemieux, David M. Lewis |
Using sparse crossbars within LUT. |
FPGA |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Hongbing Fan, Jiping Liu, Yu-Liang Wu |
Combinatorial routing analysis and design of universal switch blocks. |
ASP-DAC |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Wenting Hou, Hong Yu, Xianlong Hong, Yici Cai, Weimin Wu, Jun Gu, William H. Kao |
A new congestion-driven placement algorithm based on cell inflation. |
ASP-DAC |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Frank Wolz, Reiner Kolla |
Bubble Partitioning for LUT-Based Sequential Circuits. |
FPL |
2001 |
DBLP DOI BibTeX RDF |
|
11 | PariVallal Kannan, Dinesh Bhatia |
Tightly Integrated Placement and Routing for FPGAs. |
FPL |
2001 |
DBLP DOI BibTeX RDF |
|
11 | PariVallal Kannan, Shankar Balachandran, Dinesh Bhatia |
fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits. |
FPL |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Ganapathy Parthasarathy, Malgorzata Marek-Sadowska, Arindam Mukherjee 0001, Amit Singh 0001 |
Interconnect complexity-aware FPGA placement using Rent's rule. |
SLIP |
2001 |
DBLP DOI BibTeX RDF |
Rent's exponent, interconnect, placement |
11 | Mario Träber |
A novel ACS-feedback scheme for generic, sequential Viterbi-decoder macros. |
ISCAS (4) |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Sabyasachi Sengupta, Somavalli Ramanathan, Biswadeep Chatterjee, Dibyendu Goswami |
Minimizing Area and Maximizing Porosity for Cell Layouts Using Innovative Routing Strategies. |
VLSI Design |
2001 |
DBLP DOI BibTeX RDF |
|
11 | Michael Shyu, Guang-Ming Wu, Yu-Dong Chang, Yao-Wen Chang |
Generic Universal Switch Blocks. |
IEEE Trans. Computers |
2000 |
DBLP DOI BibTeX RDF |
design, architecture, Analysis, digital, programmable logic array, gate array |
11 | Maogang Wang, Xiaojian Yang, Majid Sarrafzadeh |
Congestion minimization during placement. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
11 | John Marty Emmert, Dinesh K. Bhatia |
A Fault Tolerant Technique for FPGAs. |
J. Electron. Test. |
2000 |
DBLP DOI BibTeX RDF |
incremental reconfiguration, incremental routing, incremental placement, fault tolerance, FPGA |
11 | Guy G. Lemieux, Paul Leventis, David M. Lewis |
Generating highly-routable sparse crossbars for PLDs. |
FPGA |
2000 |
DBLP DOI BibTeX RDF |
|
11 | Sushil Chandra Jain, Shashi Kumar, Anshul Kumar |
Evaluation of Various Routing Architectures for Multi-FPGA Boards. |
VLSI Design |
2000 |
DBLP DOI BibTeX RDF |
FPGA, Reconfigurable Computing, Rapid Prototyping |
11 | Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov |
Can recursive bisection alone produce routable placements? |
DAC |
2000 |
DBLP DOI BibTeX RDF |
|
11 | Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic |
The memory/logic interface in FPGAs with large embedded memory arrays. |
IEEE Trans. Very Large Scale Integr. Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
11 | Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky |
On wirelength estimations for row-based placement. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
11 | M. Kivioja, Jouni Isoaho, L. Vänskä |
Design and Implementation of Viterbi Decoder with FPGAs. |
J. VLSI Signal Process. |
1999 |
DBLP DOI BibTeX RDF |
|
11 | Sree Ganesan, Ranga Vemuri |
A Methodology for Rapid Prototyping of Analog Systems. |
ICCD |
1999 |
DBLP DOI BibTeX RDF |
rapid prototyping, technology mapping, placement and routing, FPAA, field-programmable analog arrays |
11 | Frank Schmiedle, Rolf Drechsler, Bernd Becker 0001 |
Exact channel routing using symbolic representation. |
ISCAS (6) |
1999 |
DBLP DOI BibTeX RDF |
|
11 | David M. Lewis, David R. Galloway, Marcus van Ierssel, Jonathan Rose, Paul Chow |
The Transmogrifier-2: a 1 million gate rapid-prototyping system. |
IEEE Trans. Very Large Scale Integr. Syst. |
1998 |
DBLP DOI BibTeX RDF |
|
11 | Emil S. Ochotta, Patrick J. Crotty, Charles R. Erickson, Chih-Tsung Huang, Rajeev Jayaraman, Richard C. Li, Joseph D. Linoff, Luan Ngo, Hy V. Nguyen, Kerry M. Pierce, Douglas P. Wieland, Jennifer Zhuang, Scott S. Nance |
A Novel Predictable Segmented FPGA Routing Architecture. |
FPGA |
1998 |
DBLP DOI BibTeX RDF |
FPGA, routing, programmable logic |
11 | Steven Trimberger |
Scheduling Designs into a Time-Multiplexed FPGA. |
FPGA |
1998 |
DBLP DOI BibTeX RDF |
|
11 | John Marty Emmert, Akash Randhar, Dinesh Bhatia |
Fast Floorplanning for FPGAs. |
FPL |
1998 |
DBLP DOI BibTeX RDF |
|
11 | Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mantik, Igor L. Markov, Alexander Zelikovsky |
On wirelength estimations for row-based placement. |
ISPD |
1998 |
DBLP DOI BibTeX RDF |
|