Search results for "register"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
21	I-Chyn Wey, Lung-Hao Chang, You-Gang Chen, Shih-Hung Chang, An-Yeu Wu	A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
21	William Zhu 0001, Clark D. Thomborson	Algorithms to Watermark Software Through Register Allocation.	DRMTICS	2005	DBLP DOI BibTeX RDF
21	Dominik Jochinger, Franz Pichler	A New Pseudo-Random Generator Based on Gollmann Cascades of Baker-Register-Machines.	EUROCAST	2005	DBLP DOI BibTeX RDF
21	Hua Yang, Gang Cui, Xiaozong Yang	Eliminating Inter-Thread Interference in Register File for SMT Processors.	PDCAT	2005	DBLP DOI BibTeX RDF
21	Tuomas Järvinen, Jarmo Takala	Register-Based Permutation Networks for Stride Permutations.	SAMOS	2004	DBLP DOI BibTeX RDF
21	Andreas Leininger, Michael Gössel, Peter Muhmenthaler	Diagnosis of Scan-Chains by Use of a Configurable Signature Register and Error-Correcting Code.	DATE	2004	DBLP DOI BibTeX RDF
21	Tetsuya Sueyoshi, Hiroshi Uchida, Hans Jürgen Mattausch, Tetsushi Koide, Yosuke Mitani, Tetsuo Hironaka	Compact 12-port multi-bank register file test-chip in 0.35µm CMOS for highly parallel processors.	ASP-DAC	2004	DBLP DOI BibTeX RDF
21	Chantana Chantrapornchai, Wanlop Surakumpolthorn, Edwin Hsing-Mean Sha	Efficient Scheduling for Design Exploration with Imprecise Latency and Register Constraints.	EUC	2004	DBLP DOI BibTeX RDF
21	Bernard Goossens	The Instruction Register File.	PaCT	2003	DBLP DOI BibTeX RDF
21	Aneesh Aggarwal, Manoj Franklin	Energy Efficient Asymmetrically Ported Register Files.	ICCD	2003	DBLP DOI BibTeX RDF
21	Jia Guo, María Jesús Garzarán, David A. Padua	The Power of Belady?s Algorithm in Register Allocation for Long Basic Blocks.	LCPC	2003	DBLP DOI BibTeX RDF
21	Rogério Xavier de Azambuja, Luiz C. V. dos Santos	Global scheduling and register allocation based on predicated execution.	ISCAS (3)	2003	DBLP DOI BibTeX RDF
21	Marek Wróblewski, Matthias Müller 0002, Andreas Wortmann 0002, Sven Simon 0001, Wilhelm Pieper, Josef A. Nossek	A power efficient register file architecture using master latch sharing.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
21	Kevin Fan, Nathan Clark, Michael L. Chu, K. V. Manjunath, Rajiv A. Ravindran, Mikhail Smelyanskiy, Scott A. Mahlke	Systematic Register Bypass Customization for Application-Specific Processors.	ASAP	2003	DBLP DOI BibTeX RDF
21	Qiang Xu 0001, Nicola Nicolici	On Reducing Wrapper Boundary Register Cells in Modular SOC Testing.	ITC	2003	DBLP DOI BibTeX RDF
21	Kelvin Lin, Jean Jyh-Jiun Shann, Chung-Ping Chung	Code Compression by Register Operand Dependency.	Interaction between Compilers and Computer Architectures	2002	DBLP DOI BibTeX RDF	Dictionary-based compression, Code compression
21	Yuhei Kaneko, Nobuhiko Sugino, Akinori Nishihara	Memory allocation method for indirect addressing with an index register.	APCCAS (1)	2002	DBLP DOI BibTeX RDF
21	Eun-Jin Im, Katherine A. Yelick	Optimizing Sparse Matrix Computations for Register Reuse in SPARSITY.	International Conference on Computational Science (1)	2001	DBLP DOI BibTeX RDF
21	Dezsö Sima	The Design Space of Register Renaming Techniques.	IEEE Micro	2000	DBLP DOI BibTeX RDF
21	Thomas Bräunl	Register-Transfer Level Simulation.	MASCOTS	2000	DBLP DOI BibTeX RDF
21	R. Anand, Margarida F. Jacome, Gustavo de Veciana	Heuristic tradeoffs between latency and energy consumption in register assignment.	CODES	2000	DBLP DOI BibTeX RDF
21	Bart Mesman, Carlos A. Alba Pinto, Koen van Eijk	Efficient Scheduling of DSP Code on Processors with Distributed Register Files.	ISSS	1999	DBLP DOI BibTeX RDF
21	Chaeryung Park, Taewhan Kim, C. L. Liu 0001	Register Allocation - A Hierarchical Reduction Approach.	J. VLSI Signal Process.	1998	DBLP DOI BibTeX RDF
21	Katzalin Olcoz, Francisco Tirado	Register Allocation with Simultaneous BIST Intrusio.	EUROMICRO	1998	DBLP DOI BibTeX RDF
21	Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.	Incorporating interconnect, register, and clock distribution delays into the retiming process.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
21	Mikkel Thorup	Structured Programs have Small Tree-Width and Good Register Allocation (Extended Abstract).	WG	1997	DBLP DOI BibTeX RDF
21	Zebo Peng, Krzysztof Kuchcinski	Automated transformation of algorithms into register-transfer level implementations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
21	Juin-Yeu Lu, Shiu-Kai Chin	Generating Designs Using an Algorithmic Register Transfer Language with Formal Semantics.	TPHOLs	1994	DBLP DOI BibTeX RDF
21	Waleed Meleis, Edward S. Davidson	Optimal local register allocation for a multiple-issue machine.	International Conference on Supercomputing	1994	DBLP DOI BibTeX RDF
21	Tolga Soyata, Eby G. Friedman	Retiming with non-zero clock skew, variable register, and interconnect delay.	ICCAD	1994	DBLP DOI BibTeX RDF
21	Rainer Göttfert, Harald Niederreiter	General Lower Bound for the Linear Complexity of the Product of Shift-Register Sequences.	EUROCRYPT	1994	DBLP DOI BibTeX RDF
21	Rainer Göttfert, Harald Niederreiter	On the Linear Complexity of Products of Shift-Register Sequences.	EUROCRYPT	1993	DBLP DOI BibTeX RDF
21	Thomas Müller-Wipperfürth, Josef Scharinger, Franz Pichler	FSM Shift Register Realization for Improved Testability.	EUROCAST	1993	DBLP DOI BibTeX RDF
21	C. Leonard Berman	Circuit width, register allocation, and ordered binary decision diagrams.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
21	Christoph W. Keßler, Wolfgang J. Paul, Thomas Rauber	A Randomized Heuristic Approach to Register Allocation	PLILP	1991	DBLP DOI BibTeX RDF
21	Fred C. Chow, John L. Hennessy	The Priority-Based Coloring Approach to Register Allocation.	ACM Trans. Program. Lang. Syst.	1990	DBLP DOI BibTeX RDF
21	Arvin Park, Matthew K. Farrens	Address compression through base register caching.	MICRO	1990	DBLP BibTeX RDF	CPU performance, microprocessor systems, locality, bandwidth
21	Rajiv Gupta 0001	Employing Register Channels for the Exploitation of Instruction Level Parallelism.	PPoPP	1990	DBLP DOI BibTeX RDF
21	Bruce Jay Collings, G. Barry Hembree	Initializing generalized feedback shift register pseudorandom number generators.	J. ACM	1986	DBLP DOI BibTeX RDF
21	Semyon Shteingart, Andrew W. Nagle, John Grason	RTG: automatic register level test generator.	DAC	1985	DBLP DOI BibTeX RDF
21	Andrew Klapper	Expected pi-Adic Security Measures of Sequences.	SETA	2008	DBLP DOI BibTeX RDF	algebraic feedback shift register, sequence, pseudo-randomness, security measure, feedback with carry shift register
21	Alodeep Sanyal, Sandip Kundu	A Built-in Test and Characterization Method for Circuit Marginality Related Failures.	ISQED	2008	DBLP DOI BibTeX RDF	Circuit Marginality, Pseudorandom Pattern Generator (PRPG), Multiple Input Signature Register (MISR), Fmax testing based on frequency shmoo, Built-In Self-Test (BIST), Design-for-Testability (DFT), Linear Feedback Shift Register (LFSR)
21	Yi-Bing Lin	Eliminating Overflow for Large-Scale Mobility Databases in Cellular Telephone Networks.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Cellular telephone network, database overflow, visitor location register, home location register, large-scale database
21	Steven R. Vegdahl	Using Node Merging to Enhance Graph Coloring.	PLDI	1999	DBLP DOI BibTeX RDF	graph coloring, register allocation, register coalescing
21	Yi-Bing Lin	Reducing location update cost in a PCS network.	IEEE/ACM Trans. Netw.	1997	DBLP DOI BibTeX RDF	roaming management, visitor location register, mobility management, personal communications services, home location register
21	Michal Kopec	Can Nonlinear Compactors Be Better than Linear Ones.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	built-in self-test, linear feedback shift register, signature analysis, Aliasing probability, data compaction, nonlinear feedback shift register
21	Josep Llosa, Mateo Valero, Eduard Ayguadé, Antonio González 0001	Hypernode reduction modulo scheduling.	MICRO	1995	DBLP DOI BibTeX RDF	register allocation, software pipelining, instruction scheduling, loop scheduling, register spilling
21	Joseph S. M. Ho, Ian F. Akyildiz	Local Anchor Scheme for Reducing Location Tracking Costs in PCNs.	MobiCom	1995	DBLP DOI BibTeX RDF	call delivery, local anchoring, location registration, visitor location register, home location register
21	Svetlana P. Kartashev, Steven I. Kartashev	Analysis and Synthesis of Dynamic Multicomputer Networks that Reconfigure into Rings, Trees, and Stars.	IEEE Trans. Computers	1987	DBLP DOI BibTeX RDF	stars?single and multirooted, Binary tree?single and multirooted, composite ring structures, reconfiguration code, reconfiguration of dynamic multicomputer networks, ring period, set of rings, shift- register theory, shift register with variable bias, single ring structures
21	Jacob Savir	The Bidirectional Double Latch (BDDL).	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	shift register latch, shift register failure diagnostics, Design for testability, hardware overhead, LSSD
21	Tatsuo Higuchi 0001, Michitaka Kameyama	Static-Hazard-Free T-Gate for Ternary Memory Element and Its Application to Ternary Counters.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	Counter based on shift register, emitter coupled logic (ECL), feedback shift register (FSR), signed ternary number representation, static-hazard-free T-gate, symmetrical modulo-M counter, synchronous and asynchronous signed ternary counter, ternary memory element, up-down counting
20	Roberto Baldoni, Silvia Bonomi, Michel Raynal	Joining a Distributed Shared Memory Computation in a Dynamic Distributed System.	SEUS	2009	DBLP DOI BibTeX RDF	Provable guarantee, Regular register, Set object, Dynamic system, Synchronous system, Churn
20	Joon-Sung Yang, Nur A. Touba	Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture.	VTS	2008	DBLP DOI BibTeX RDF	Trace Buffer Observation Window, Two-Dimensional (2-D) Compaction, Cycling Register, Silicon Debug, MISR
20	Shao-Yang Wang, Rong-Guey Chang	Code size reduction by compressing repeated instruction sequences.	J. Supercomput.	2007	DBLP DOI BibTeX RDF	Repeated instruction sequence, Index table, Instruction table, Register bank, Code compression, Decompression, Instruction prefetching
20	Florent Bouchez, Alain Darte, Fabrice Rastello	On the complexity of spill everywhere under SSA form.	LCTES	2007	DBLP DOI BibTeX RDF	spill, complexity, register allocation, SSA form
20	Tadayoshi Enomoto, Suguru Nagayama, Nobuaki Kobayashi	Low-Power High-Speed 180-nm CMOS Clock Drivers.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.640 ns, CMOS clock drivers, register array, delay flip-flops, 251 muW, CMOS technology, power dissipation, delay time, 0.18 micron
20	Bin Zhang 0003, Dengguo Feng	Multi-pass Fast Correlation Attack on Stream Ciphers.	Selected Areas in Cryptography	2006	DBLP DOI BibTeX RDF	Stream cipher, Linear feedback shift register (LFSR), Fast correlation attack, Parity-check
20	Tor Helleseth, Cees J. A. Jansen, Shahram Khazaei, Alexander Kholosha	Security of Jump Controlled Sequence Generators for Stream Ciphers.	SETA	2006	DBLP DOI BibTeX RDF	jump register, key-stream generator, linear relations, Cryptanalysis, stream cipher, Pomaranch
20	Mark Goresky, Andrew Klapper	Periodicity and Distribution Properties of Combined FCSR Sequences.	SETA	2006	DBLP DOI BibTeX RDF	stream cipher, pseudorandom sequence, Feedback with carry shift register
20	Takuya Nakaike, Tatsushi Inagaki, Hideaki Komatsu, Toshio Nakatani	Profile-based global live-range splitting.	PLDI	2006	DBLP DOI BibTeX RDF	live-range splitting, graph coloring, register allocation
20	Stephen Hines, David B. Whalley, Gary S. Tyson	Adapting compilation techniques to enhance the packing of instructions into registers.	CASES	2006	DBLP DOI BibTeX RDF	instruction packing, instruction register file, compiler optimizations
20	Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev 0001, Kanad Ghose	Selective writeback: exploiting transient values for energy-efficiency and performance.	ISLPED	2006	DBLP DOI BibTeX RDF	energy-efficiency, register files
20	Priya Iyer, Shailendra Jain, Bryan Casper, Jason Howard	Testing High-Speed IO Links Using On-Die Circuitry.	VLSI Design	2006	DBLP DOI BibTeX RDF	link characterization, on-die oscilloscope, BER, register file, JTAG, IO
20	Alex Aletà, Josep M. Codina, Antonio González 0001, David R. Kaeli	Demystifying on-the-fly spill code.	PLDI	2005	DBLP DOI BibTeX RDF	register allocation, modulo scheduling, spill code
20	Ruo Ando, Yoshiyasu Takefuji	Self Debugging Mode for Patch-Independent Nullification of Unknown Remote Process Infection.	CANS	2005	DBLP DOI BibTeX RDF	self-debugging mode, real-time nullification, debug register, improved debug exception handler, branchIP recorder
20	Kevin Chen, Matthew Henricksen, William Millan, Joanne Fuller, Leonie Ruth Simpson, Ed Dawson, Hoon-Jae Lee 0001, Sang-Jae Moon	Dragon: A Fast Word Based Stream Cipher.	ICISC	2004	DBLP DOI BibTeX RDF	word based stream cipher, nonlinear filter, nonlinear feedback shift register
20	Yun-Nan Chang	An Efficient In-Place VLSI Architecture for Viterbi Algorithm.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	register-exchange, trace-back, ACS unit, Viterbi decoder
20	Manoranjan Satpathy, Rabi N. Mahapatra, Siddharth Choudhuri, Sachin V. Chitnis	High Performance Code Generation through Lazy Activation Records.	Interaction between Compilers and Computer Architectures	2003	DBLP DOI BibTeX RDF	Register Utilization, Activation Records, Low Power Optimization, Embedded Systems
20	Christoph W. Keßler, Andrzej Bednarski	Optimal integrated code generation for clustered VLIW architectures.	LCTES-SCOPES	2002	DBLP DOI BibTeX RDF	integrated code generation, space profile, dynamic programming, register allocation, instruction scheduling, instruction selection
20	Zoran Budimlic, Keith D. Cooper, Timothy J. Harvey, Ken Kennedy, Timothy S. Oberg, Steven W. Reeves	Fast Copy Coalescing and Live-Range Identification.	PLDI	2002	DBLP DOI BibTeX RDF	copy coalescing, live-range identification, code generation, register allocation, interference graph
20	Milenko Drinic, Darko Kirovski	Behavioral synthesis via engineering change.	DAC	2002	DBLP DOI BibTeX RDF	engineering change, scheduling, transformations, register assignment
20	Guang Gong, Lein Harn, Huapeng Wu	The GH Public-Key Cryptosystem.	Selected Areas in Cryptography	2001	DBLP DOI BibTeX RDF	third-order linear feedback shift register sequences over finite fields, digital signature, Public-key cryptosystem
20	Alexander Kholosha	Clock-Controlled Shift Registers and Generalized Geffe Key-Stream Generator.	INDOCRYPT	2001	DBLP DOI BibTeX RDF	key-stream generator, clock-controlled shift register, Geffe generator, cryptography
20	Koen van Eijk, Bart Mesman, Carlos A. Alba Pinto, Qin Zhao, Marco Bekooij, Jef L. van Meerbergen, Jochen A. G. Jess	Constraint analysis for code generation: basic techniques and applications in FACTS.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	foreground memory, phase coupling, scheduling, DSP, constraint analysis, register binding
20	Rastislav Bodík, Rajiv Gupta 0001, Mary Lou Soffa	Load-Reuse Analysis: Design and Evaluation.	PLDI	1999	DBLP DOI BibTeX RDF	data-flow analysis, program representations, profile-guided optimizations, register promotion
20	Dingchao Li, Yuji Iwahori, Tatsuya Hayashi, Naohiro Ishii	A Spill Code Placement Framework for Code Scheduling.	LCPC	1998	DBLP DOI BibTeX RDF	Fine grain parallel architectures, program behavior analysis, compiler optimization, register spilling, code scheduling
20	Oliver Rüthing	Optimal Code Motion in the Presence of Large Expressions.	ICCL	1998	DBLP DOI BibTeX RDF	partial redundancy, graph theory, register allocation, graph matching, program optimization, code motion, elimination
20	M. Anton Ertl, Andreas Krall	Removing Anti Dependences by Repairing.	CC	1996	DBLP DOI BibTeX RDF	anti dependence, instruction-level parallelism, speculative execution, repairing, register renaming
20	Larry Carter, Jeanne Ferrante, Susan Flynn Hummel	Hierarchical tiling for improved superscalar performance.	IPPS	1995	DBLP DOI BibTeX RDF	hierarchical tiling, superscalar performance, inner-loop performance, compiler phases, scalar replacement, storage mapping, superscalar pipelined processors, automatic preprocessor, performance evaluation, parallel processing, parallelization, message passing, message passing, register allocation, instruction scheduling, optimizing compiler, data locality, archival storage
20	Jay K. Adams, John Alan Miller, Donald E. Thomas	Execution-time profiling for multiple-process behavioral synthesis.	ICCD	1995	DBLP DOI BibTeX RDF	execution-time profiling, multiple-process behavioral synthesis, back-annotating, source description, behavioral simulation model, annotated behavioral simulation, high level synthesis, high-level synthesis, timing, timing, logic CAD, digital simulation, circuit analysis computing, hardware design, software profiling, register-transfer level model
20	Gerd Maderlechner, Helmut Mayer 0001	Conversion of high level information from scanned maps into geographic information systems.	ICDAR	1995	DBLP DOI BibTeX RDF	frame based representation, high level information conversion, scanned maps, land register maps, feedback cycles, legal information extraction, parcels, boundary stones, topographic information, feature extraction, geographic information systems, geographic information systems, knowledge representation, frames, semantic networks, semantic networks, cartography, explicit knowledge, automatic extraction, law administration
20	Peter Dahl, Matthew T. O'Keefe	Reducing memory traffic with CRegs.	MICRO	1994	DBLP DOI BibTeX RDF	CRegs, ambiguous alias, live range, graph coloring, register allocation
20	Preston Briggs, Linda Torczon	An Efficient Representation for Sparse Sets.	LOPLAS	1993	DBLP DOI BibTeX RDF	compiler implementation, set representations, register allocation, set operations
20	Ajay Kumar Verma, Philip Brisk, Paolo Ienne	Fast, quasi-optimal, and pipelined instruction-set extensions.	ASP-DAC	2008	DBLP DOI BibTeX RDF
20	Yang Xiao 0001, Hui Chen 0001, Hsiao-Hwa Chen, Bo Sun 0001, C. L. Philip Chen	Optimal Utilization and Effects of Inaccurate Estimation in Mobile Database Failure Restoration.	IEEE Trans. Wirel. Commun.	2007	DBLP DOI BibTeX RDF
20	Guillermo Payá Vayá, Javier Martín-Langerwerf, Piriya Taptimthong, Peter Pirsch	Design Space Exploration of Media Processors: A Parameterized Scheduler.	ICSAMOS	2007	DBLP DOI BibTeX RDF
20	Gregory V. Chockler, Rachid Guerraoui, Idit Keidar	Amnesic Distributed Storage.	DISC	2007	DBLP DOI BibTeX RDF
20	Xiaotong Zhuang, Santosh Pande	Parallelizing load/stores on dual-bank memory embedded processors.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	memory bank allocation, parallel load/stores, profile driven optimization, DSP architectures
20	Ge Jin, Sang-Joon Lee, James K. Hahn, Steven Bielamowicz, Rajat Mittal 0002, Raymond Walsh	3D Surface Reconstruction and Registration for Image Guided Medialization Laryngoplasty.	ISVC (1)	2006	DBLP DOI BibTeX RDF	3D Reconstruction, Registration, Image Guided Surgery
20	Lisa Higham, Colette Johnen	Relationships between communication models in networks using atomic registers.	IPDPS	2006	DBLP DOI BibTeX RDF
20	Ryan Collins, Fernando Alegre, Xiaotong Zhuang, Santosh Pande	Compiler assisted dynamic management of registers for network processors.	IPDPS	2006	DBLP DOI BibTeX RDF
20	Chang-Jin Choi, Sang-Hun Yoon, Jong-Wha Chong, Shouyin Liu	A New Low-Power and High Speed Viterbi Decoder Architecture.	ICUCT	2006	DBLP DOI BibTeX RDF	RE-exchange, low-power, look-ahead, viterbi
20	Yongxiang Liu, Gokhan Memik, Glenn Reinman	Reducing the Energy of Speculative Instruction Schedulers.	ICCD	2005	DBLP DOI BibTeX RDF
20	Lei Wang 0003	Error-tolerance memory Microarchitecture via Dynamic Multithreading.	ICCD	2005	DBLP DOI BibTeX RDF
20	Hongbo Rong, Alban Douillet, Ramaswamy Govindarajan, Guang R. Gao	Code Generation for Single-Dimension Software Pipelining of Multi-Dimensional Loops.	CGO	2004	DBLP DOI BibTeX RDF
20	Byoungro So, Mary W. Hall	Increasing the Applicability of Scalar Replacement.	CC	2004	DBLP DOI BibTeX RDF
20	Solomon W. Golomb, Pey-Feng Lee	Which Irreducible Polynomials Divide Trinomials over GF(2)?	SETA	2004	DBLP DOI BibTeX RDF
20	Wenlong Li, Haibo Lin, Yu Chen, Zhizhong Tang	Increasing Software-Pipelined Loops in the Itanium-Like Architecture.	ISPA	2004	DBLP DOI BibTeX RDF
20	Dmitry Ponomarev 0001, Gurhan Kucuk, Oguz Ergin, Kanad Ghose	Reducing Datapath Energy through the Isolation of Short-Lived Operands.	IEEE PACT	2003	DBLP DOI BibTeX RDF
20	Peter Suaris, Dongsheng Wang 0012, Pei-Ning Guo, Nan-Chi Chou	A physical retiming algorithm for field programmable gate arrays.	FPGA	2003	DBLP DOI BibTeX RDF