Search results for "ARC"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	David Boland, George A. Constantinides	Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods.	ARC	2010	DBLP DOI BibTeX RDF
1	Kyungwook Chang, Kiyoung Choi	Memory-Centric Communication Architecture for Reconfigurable Computing.	ARC	2010	DBLP DOI BibTeX RDF
1	Esam El-Araby, Vikram K. Narayana, Tarek A. El-Ghazawi	Space and Time Sharing of Reconfigurable Hardware for Accelerated Parallel Processing.	ARC	2010	DBLP DOI BibTeX RDF
1	Karel Bruneel, Dirk Stroobandt	TROUTE: A Reconfigurability-Aware FPGA Router.	ARC	2010	DBLP DOI BibTeX RDF
1	Mouna Baklouti, Philippe Marquet, Jean-Luc Dekeyser, Mohamed Abid	Reconfigurable Communication Networks in a Parametric SIMD Parallel System on Chip.	ARC	2010	DBLP DOI BibTeX RDF
1	Antonio Roldao Lopes, George A. Constantinides	A Fused Hybrid Floating-Point and Fixed-Point Dot-Product for FPGAs.	ARC	2010	DBLP DOI BibTeX RDF
1	Bijan Alizadeh, Amir Masoud Gharehbaghi, Masahiro Fujita	Pipelined Microprocessors Optimization and Debugging.	ARC	2010	DBLP DOI BibTeX RDF
1	Abdulhadi Shoufan	An FPGA Accelerator for Hash Tree Generation in the Merkle Signature Scheme.	ARC	2010	DBLP DOI BibTeX RDF
1	Ram Krishnamurthy 0001	High-Performance Energy-Efficient Reconfigurable Accelerators/Co-processors for Tera-Scale Multi-core Microprocessors.	ARC	2010	DBLP DOI BibTeX RDF
1	Lilian Janin, Shoujie Li, Doug Edwards	Integrated Design Environment for Reconfigurable HPC.	ARC	2010	DBLP DOI BibTeX RDF
1	Yu Zhang, Dan Feng 0001	Reconfigurable Computing and Task Scheduling for Active Storage Service Processing.	ARC	2010	DBLP DOI BibTeX RDF
1	Sergey Morozov 0001, Abhranil Maiti, Patrick Schaumont	An Analysis of Delay Based PUF Implementations on FPGA.	ARC	2010	DBLP DOI BibTeX RDF
1	Peter Y. K. Cheung	Process Variability and Degradation: New Frontier for Reconfigurable.	ARC	2010	DBLP DOI BibTeX RDF
1	Weibo Pan, William P. Marnane	A Reconfigurable Implementation of the Tate Pairing Computation over GF(2m).	ARC	2010	DBLP DOI BibTeX RDF
1	Phaophak Sirisuk, Fearghal Morgan, Tarek A. El-Ghazawi, Hideharu Amano (eds.)	Reconfigurable Computing: Architectures, Tools and Applications, 6th International Symposium, ARC 2010, Bangkok, Thailand, March 17-19, 2010. Proceedings	ARC	2010	DBLP DOI BibTeX RDF
1	Thomas Marconi, Yi Lu 0004, Koen Bertels, Georgi Gaydadjiev	3D Compaction: A Novel Blocking-Aware Algorithm for Online Hardware Task Scheduling and Placement on 2D Partially Reconfigurable Devices.	ARC	2010	DBLP DOI BibTeX RDF
1	Sayyed Arash Ostadzadeh, Roel Meeuws, Carlo Galuzzi, Koen Bertels	QUAD - A Memory Access Pattern Analyser.	ARC	2010	DBLP DOI BibTeX RDF
1	Husain Parvez, Zied Marrakchi, Habib Mehrez	Application Specific FPGA Using Heterogeneous Logic Blocks.	ARC	2010	DBLP DOI BibTeX RDF
1	Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Lars Braun, Michael Hübner 0001, Jürgen Becker 0001	FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing.	ARC	2009	DBLP DOI BibTeX RDF	design assurance, bitstream debugging, security, FPGA, Reconfigurable Computing, design verification, EDA tools
1	Xu Guo 0001, Patrick Schaumont	Optimizing the Control Hierarchy of an ECC Coprocessor Design on an FPGA Based SoC Platform.	ARC	2009	DBLP DOI BibTeX RDF
1	Yoshihiro Ichinomiya, Shiro Tanoue, Tomoyuki Ishida, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi	Memory Sharing Approach for TMR Softcore Processor.	ARC	2009	DBLP DOI BibTeX RDF
1	Andreas Heinig, Jochen Strunk, Wolfgang Rehm, Heiko Schick	ACCFS - Operating System Integration of Computational Accelerators Using a VFS Approach.	ARC	2009	DBLP DOI BibTeX RDF
1	Brian Baldwin, Richard Moloney, Andrew Byrne, Gary McGuire, William P. Marnane	A Hardware Analysis of Twisted Edwards Curves for an Elliptic Curve Cryptosystem.	ARC	2009	DBLP DOI BibTeX RDF
1	José Manuel Moya, Javier Rodríguez Escolar, Julio Martín, Juan Carlos Vallejo, Pedro Malagón, Álvaro Araujo, Juan-Mariano de Goyeneche, Agustín Rubio, Elena Romero, Daniel Villanueva, Octavio Nieto-Taladriz, Carlos A. López-Barrio	SORU: A Reconfigurable Vector Unit for Adaptable Embedded Systems.	ARC	2009	DBLP DOI BibTeX RDF	Application-transparent adaptation, Ubiquitous computing, Reconfigurable hardware, Adaptable architectures
1	Mahmood Fazlali, Mohammad K. Fallah, Mahdy Zolghadr, Ali Zakerolhosseini	A New Datapath Merging Method for Reconfigurable System.	ARC	2009	DBLP DOI BibTeX RDF	Datapath Merging, Maximum Weighted Clique Algorithm, High Level Synthesis, Reconfigurable Computing
1	Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi	A Novel Local Interconnect Architecture for Variable Grain Logic Cell.	ARC	2009	DBLP DOI BibTeX RDF
1	Brent E. Nelson	FPGA Design Productivity - A Discussion of the State of the Art and a Research Agenda.	ARC	2009	DBLP DOI BibTeX RDF
1	Luca Sterpone	Timing Driven Placement for Fault Tolerant Circuits Implemented on SRAM-Based FPGAs.	ARC	2009	DBLP DOI BibTeX RDF	fault tolerance, FPGA, Single Event Upset, Triple Modular Redundancy, Timing-driven Placement
1	Yi Lu 0004, Thomas Marconi, Koen Bertels, Georgi Gaydadjiev	Online Task Scheduling for the FPGA-Based Partially Reconfigurable Systems.	ARC	2009	DBLP DOI BibTeX RDF
1	Jaeyoung Yi, Karam Park, Joonseok Park, Won Woo Ro	Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm.	ARC	2009	DBLP DOI BibTeX RDF	Block Cipher Algorithm, Field Programmable Gate Arrays (FPGA), Cryptography, SEED
1	Brendan P. Glackin, Jim Harkin, T. Martin McGinnity, Liam P. Maguire	A Hardware Accelerated Simulation Environment for Spiking Neural Networks.	ARC	2009	DBLP DOI BibTeX RDF	FPGAs, reconfiguration, spiking neural networks, online training
1	Maciej Wielgosz, Ernest Jamro, Kazimierz Wiatr	Accelerating Calculations on the RASC Platform: A Case Study of the Exponential Function.	ARC	2009	DBLP DOI BibTeX RDF	HPRC (High Performance Reconfigurable Computing), exponent function, FPGA
1	Daniel Ménard, Emmanuel Casseau, Shafqat Khan, Olivier Sentieys, Stéphane Chevobbe, Stéphane Guyetant, Raphaël David	Reconfigurable Operator Based Multimedia Embedded Processor.	ARC	2009	DBLP DOI BibTeX RDF
1	Tomoya Ishimori, Hideki Yamada, Yuichiro Shibata, Yasunori Osana, Masato Yoshimi, Yuri Nishikawa, Hideharu Amano, Akira Funahashi, Noriko Hiroi, Kiyoshi Oguri	Pipeline Scheduling with Input Port Constraints for an FPGA-Based Biochemical Simulator.	ARC	2009	DBLP DOI BibTeX RDF
1	Mateus B. Rutzig, Antonio Carlos Schneider Beck, Luigi Carro	Dynamically Adapted Low Power ASIPs.	ARC	2009	DBLP DOI BibTeX RDF
1	Tobias Becker, Wayne Luk, Peter Y. K. Cheung	Parametric Design for Reconfigurable Software-Defined Radio.	ARC	2009	DBLP DOI BibTeX RDF
1	Joseph Hassoun	Resiliency in Elemental Computing.	ARC	2009	DBLP DOI BibTeX RDF
1	Jürgen Becker 0001, Roger F. Woods, Peter M. Athanas, Fearghal Morgan (eds.)	Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings	ARC	2009	DBLP DOI BibTeX RDF
1	Raphael Weber, Achim Rettberg	Implementation of the AES Algorithm for a Reconfigurable, Bit Serial, Fully Pipelined Architecture.	ARC	2009	DBLP DOI BibTeX RDF
1	Debora Matos, Caroline Concatto, Luigi Carro, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin	The Need for Reconfigurable Routers in Networks-on-Chip.	ARC	2009	DBLP DOI BibTeX RDF	heterogeneous NoC, reconfigurable router, buffer, FIFO
1	Fernando Rincón, Jesús Barba, Francisco Moya, Juan Carlos López 0001, Julio Dondo	Transparent Dynamic Reconfiguration as a Service of a System-Level Middleware.	ARC	2009	DBLP DOI BibTeX RDF
1	Hiroki Nakahara, Tsutomu Sasao, Munehiro Matsuura, Yoshifumi Kawamura	A Parallel Branching Program Machine for Emulation of Sequential Circuits.	ARC	2009	DBLP DOI BibTeX RDF
1	Ian Phillips	The Colour of Embedded Computation.	ARC	2009	DBLP DOI BibTeX RDF
1	Juan Carlos Moctezuma Eugenio, Miguel Arias-Estrada	Hardware/Software FPGA Architecture for Robotics Applications.	ARC	2009	DBLP DOI BibTeX RDF
1	Gang Zhou, Harald Michalik, László Hinsenkamp	Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAs.	ARC	2009	DBLP DOI BibTeX RDF	AES-GCM, pipelined Karatsuba multiplier, FPGAs, finite field arithmetic
1	Heiner Litz, Holger Fröning, Ulrich Brüning 0001	A HyperTransport 3 Physical Layer Interface for FPGAs.	ARC	2009	DBLP DOI BibTeX RDF
1	Beniamin Apopei, Andy Mills, Tony J. Dodd, Haydn Thompson	Real Time Simulation in Floating Point Precision Using FPGA Computing.	ARC	2009	DBLP DOI BibTeX RDF
1	Jesús Lázaro 0001, Armando Astarloa, Unai Bidarte, Jaime Jimenez, Aitzol Zuloaga	AES-Galois Counter Mode Encryption/Decryption FPGA Core for Industrial and Residential Gigabit Ethernet Communications.	ARC	2009	DBLP DOI BibTeX RDF
1	Sirisak Leephokhanon, Theerayod Wiangtong	Object Tracking and Motion Capturing in Hardware-Accelerated Multi-camera System.	ARC	2009	DBLP DOI BibTeX RDF
1	Samar Yazdani, Thierry Goubier, Bernard Pottier, Catherine Dezan	Optimizing Memory Access Latencies on a Reconfigurable Multimedia Accelerator: A Case of a Turbo Product Codes Decoder.	ARC	2009	DBLP DOI BibTeX RDF
1	Dimitris Theodoropoulos, Alexandros Siskos, Dionisios N. Pnevmatikatos	CCproc: A Custom VLIW Cryptography Co-processor for Symmetric-Key Ciphers.	ARC	2009	DBLP DOI BibTeX RDF	Cryptography, VLIW, reconfigurable processors
1	Mao Nakajima, Minoru Watanabe	Fast Optical Reconfiguration of a Nine-Context DORGA.	ARC	2009	DBLP DOI BibTeX RDF
1	Saar Drimer, Markus G. Kuhn	A Protocol for Secure Remote Updates of FPGA Configurations.	ARC	2009	DBLP DOI BibTeX RDF
1	Mythri Alle, Keshavan Varadarajan, Alexander Fell, S. K. Nandy 0001, Ranjani Narayan	Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures.	ARC	2009	DBLP DOI BibTeX RDF
1	Rainer Buchty, David Kramer, Fabian Nowak, Wolfgang Karl	A Seamless Virtualization Approach for Transparent Dynamical Function Mapping Targeting Heterogeneous and Reconfigurable Systems.	ARC	2009	DBLP DOI BibTeX RDF
1	Markus Happe, Enno Lübbers, Marco Platzner	A Multithreaded Framework for Sequential Monte Carlo Methods on CPU/FPGA Platforms.	ARC	2009	DBLP DOI BibTeX RDF
1	Marco Lanuzza, Paolo Zicari, Fabio Frustaci, Stefania Perri, Pasquale Corsonello	An Efficient and Low-Cost Design Methodology to Improve SRAM-Based FPGA Robustness in Space and Avionics Applications.	ARC	2009	DBLP DOI BibTeX RDF	FPGA, Space, Reconfigurable System, Single Event Upsets, Avionics
1	Atsuhiro Kanamaru, Hiroyuki Kawai, Yoshiki Yamaguchi, Morisothi Yasunaga	Tile-Based Fault Tolerant Approach Using Partial Reconfiguration.	ARC	2009	DBLP DOI BibTeX RDF
1	Ricardo S. Ferreira 0001, Alex Damiany, Julio C. Goldner Vendramini, Tiago Teixeira, João M. P. Cardoso	On Simplifying Placement and Routing by Extending Coarse-Grained Reconfigurable Arrays with Omega Networks.	ARC	2009	DBLP DOI BibTeX RDF
1	Yahya Jan, Lech Józwiak	Survey of Advanced CABAC Accelerator Architectures for Future Multimedia.	ARC	2009	DBLP DOI BibTeX RDF	RC hardware architectures, UHDTV, H.264/AVC, video compression, accelerators, multimedia processing, CABAC
1	Asma Kahoul, George A. Constantinides, Alastair M. Smith, Peter Y. K. Cheung	Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep.	ARC	2009	DBLP DOI BibTeX RDF	FPGA, Reconfigurable architectures, Floorplanning, integer linear programming (ILP)
1	Kofi Appiah, Andrew Hunter, Tino Kluge, Philip Aiken, Patrick Dickinson	FPGA-Based Anomalous Trajectory Detection Using SOFM.	ARC	2009	DBLP DOI BibTeX RDF
1	SangKyun Yun, KyuHee Lee	Regular Expression Pattern Matching Supporting Constrained Repetitions.	ARC	2009	DBLP DOI BibTeX RDF
1	Chalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides	Word-Length Optimization and Error Analysis of a Multivariate Gaussian Random Number Generator.	ARC	2009	DBLP DOI BibTeX RDF	Word-length optimization, FPGA, Multivariate Gaussian Distribution
1	Maciej Wielgosz, Ernest Jamro, Kazimierz Wiatr	Highly efficient structure of 64-bit exponential function implemented in FPGAs.	ARC	2008	DBLP DOI BibTeX RDF	HPRC (High Performance Reconfigurable Computing), exponent function, FPGA, elementary function
1	Masaki Nakanishi	An FPGA Configuration Scheme for Bitstream Protection.	ARC	2008	DBLP DOI BibTeX RDF	FPGA configuration, bitstream protection, bitstream encryption, bitstream authentication
1	Vítor Silva, Rui Policarpo Duarte, Mário P. Véstias, Horácio C. Neto	Multiplier-based double precision floating point divider according to the IEEE-754 standard.	ARC	2008	DBLP DOI BibTeX RDF
1	Antonio Carlos Schneider Beck, Mateus B. Rutzig, Georgi Gaydadjiev, Luigi Carro	Run-time Adaptable Architectures for Heterogeneous Behavior Embedded Systems.	ARC	2008	DBLP DOI BibTeX RDF
1	Steffen Köhler, Jan Schirok, Jens Braunes, Rainer G. Spallek	Efficiency of Dynamic Reconfigurable Datapath Extensions -- A Case Study.	ARC	2008	DBLP DOI BibTeX RDF
1	Piotr Dziurzanski, Tomasz Maka	Stream Transfer Balancing Scheme Utilizing Multi-Path Routing in Networks on Chip.	ARC	2008	DBLP DOI BibTeX RDF	stream-based processing, tapeworm routing, Ford-Fulkerson method, Networks on Chip, wormhole routing
1	Yo-Hsien Lin, Jong-Chen Chen	Neuromolecularware -- A Bio-inspired Evolvable Hardware and Its Application to Medical Diagnosis.	ARC	2008	DBLP DOI BibTeX RDF	Artificial Brain, Adaptability, Evolvable Hardware, Medical Diagnosis, Evolutionary Learning
1	Slavisa Jovanovic, Camel Tanougast, Serge Weber	A New Self-Managing Hardware Design Approach for FPGA-based Reconfigurable Systems.	ARC	2008	DBLP DOI BibTeX RDF
1	Vu Manh Tuan, Hideharu Amano	A Preemption Algorithm for a Multitasking Environment on Dynamically Reconfigurable Processor.	ARC	2008	DBLP DOI BibTeX RDF
1	Shane Santner, Wesley Peck, Jason Agron, David Andrews 0001	Symmetric Multiprocessor Design for Hybrid CPU/FPGA SoCs.	ARC	2008	DBLP DOI BibTeX RDF
1	Xiaolin Chen, Cedric Nishan Canagarajah, Raffaele Vitulli, José L. Núñez-Yáñez	Lossless Compression for Space Imagery in a Dynamically Reconfigurable Architecture.	ARC	2008	DBLP DOI BibTeX RDF
1	Carlo Galuzzi, Koen Bertels	A Framework for the Automatic Generation of Instruction-Set Extensions for Reconfigurable Architectures.	ARC	2008	DBLP DOI BibTeX RDF
1	Adriano Idalgo, Nahri Moreano	DNA Physical Mapping on a Reconfigurable Platform.	ARC	2008	DBLP DOI BibTeX RDF	Consecutive ones problem, Software/hardware partitioning, Reconfigurable architectures
1	Qiwei Jin, David B. Thomas, Wayne Luk, Benjamin Cope	Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models.	ARC	2008	DBLP DOI BibTeX RDF
1	Sumanta Chaudhuri, Sylvain Guilley, Philippe Hoogvorst, Jean-Luc Danger, Taha Beyrouthy, Alin Razafindraibe, Laurent Fesquet, Marc Renaudin	Physical Design of FPGA Interconnect to Prevent Information Leakage.	ARC	2008	DBLP DOI BibTeX RDF
1	Josef Angermeier, Ulrich Batzer, Mateusz Majer, Jürgen Teich, Christopher Claus, Walter Stechele	Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System.	ARC	2008	DBLP DOI BibTeX RDF
1	Ozana Silvia Dragomir, Elena Moscu Panainte, Koen Bertels, Stephan Wong	Optimal Unroll Factor for Reconfigurable Architectures.	ARC	2008	DBLP DOI BibTeX RDF
1	Pedro Echeverría, David B. Thomas, Marisa López-Vallejo, Wayne Luk	An FPGA run-time parameterisable Log-Normal Random Number Generator.	ARC	2008	DBLP DOI BibTeX RDF
1	Jie Zhou 0007, Yong Dou, Yuanwu Lei, Yazhuo Dong	Hybrid-Mode Floating-Point FPGA CORDIC Co-processor.	ARC	2008	DBLP DOI BibTeX RDF
1	Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung, George A. Constantinides	FPGA-based Real-time Super-Resolution on an Adaptive Image Sensor.	ARC	2008	DBLP DOI BibTeX RDF
1	Roger F. Woods, Katherine Compton, Christos-Savvas Bouganis, Pedro C. Diniz (eds.)	Reconfigurable Computing: Architectures, Tools and Applications, 4th International Workshop, ARC 2008, London, UK, March 26-28, 2008. Proceedings	ARC	2008	DBLP DOI BibTeX RDF
1	Antonio Roldao Lopes, George A. Constantinides	A High Throughput FPGA-based Floating Point Conjugate Gradient Implementation.	ARC	2008	DBLP DOI BibTeX RDF
1	Haruna Cofer, Matthias Fouquet-Lapar, Timothy Gamerdinger, Christopher Lindahl, Bruce Losure, Alan Mayer, James Swoboda, Teruo Utsumi	Creating the World's Largest Reconfigurable Supercomputing System Based on the Scalable ALTIX System Infrastructure and Benchmarking Life-Science Applications.	ARC	2008	DBLP DOI BibTeX RDF
1	Thomas Marconi, Yi Lu 0004, Koen Bertels, Georgi Gaydadjiev	Online Hardware Task Scheduling and Placement Algorithm on Partially Reconfigurable Devices.	ARC	2008	DBLP DOI BibTeX RDF
1	Hagen Gädke, Andreas Koch 0001	Accelerating Speculative Execution in High-Level Synthesis with Cancel Tokens.	ARC	2008	DBLP DOI BibTeX RDF
1	Chia-Tien Dan Lo, Yi-Gang Tai	Highly Space Efficient Counters for Perl Compatible Regular Expressions in FPGAs.	ARC	2008	DBLP DOI BibTeX RDF
1	Satnam Singh, David J. Greaves	Synthesizing FPGA Circuits from Parallel Programs.	ARC	2008	DBLP DOI BibTeX RDF
1	Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis 0001	ARISE Machines: Extending Processors with Hybrid Accelerators.	ARC	2008	DBLP DOI BibTeX RDF	reconfigurable instruction set processor, custom unit, FPGA, coprocessor
1	Frank Hannig, Holger Ruckdeschel, Hritam Dutta, Jürgen Teich	PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications.	ARC	2008	DBLP DOI BibTeX RDF
1	Filipe Oliveira, Castro M. P. Silva Santos, Fernando A. Castro, José Carlos Alves	A Custom Processor for a TDMA Solver in a CFD Application.	ARC	2008	DBLP DOI BibTeX RDF
1	Chalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides	Multivariate Gaussian Random Number Generator Targeting Specific Resource Utilization in an FPGA.	ARC	2008	DBLP DOI BibTeX RDF	FPGA, Resource Constraint, Random Numbers, Multivariate Gaussian Distribution
1	Keith D. Underwood	From Silicon to Science: The Long Road to Production Reconfigurable Supercomputing.	ARC	2008	DBLP DOI BibTeX RDF
1	Oliver Sander, Lars Braun, Michael Hübner 0001, Jürgen Becker 0001	Data reallocation by exploiting FPGA configuration mechanisms.	ARC	2008	DBLP DOI BibTeX RDF
1	Pierre Bomel, Guy Gogniat, Jean-Philippe Diguet	A Networked, Lightweight and Partially Reconfigurable Platform.	ARC	2008	DBLP DOI BibTeX RDF	bitstream server, FPGA, partial reconfiguration, link layer
1	Reiner W. Hartenstein	The von Neumann Syndrome and the CS Education Dilemma.	ARC	2008	DBLP DOI BibTeX RDF
1	Samar Yazdani, Joel Cambonie, Bernard Pottier	Programming Reconfigurable Decoupled Application Control Accelerator For Mobile Systems.	ARC	2008	DBLP DOI BibTeX RDF	coarse-grain architecture, shared-memory programming model, embedded systems, multimedia applications

Publications at "ARC"( http://dblp.L3S.de/Venues/ARC )