Search results for "VHDL"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
15	Kwang-Ting Cheng, A. S. Krishnakumar	Automatic generation of functional vectors using the extended finite state machine model.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	functional testing, automatic test generation, design verification, extended finite state machines
15	Bengt Svantesson, Ahmed Hemani, Peeter Ellervee, Adam Postula, Johnny Öberg, Axel Jantsch, Hannu Tenhunen	A Novell Allocation Strategy for Control and Memory Intensive Telecommunication Circiuts.	VLSI Design	1996	DBLP DOI BibTeX RDF	Application specific High-Level Synthesis, High-Level Synthesis for telecommunication, ATM
15	Gérard Ramstein, Olivier Déforges, P. Bakowski	A Design Tool for the Specification and the Simulation of Array Processors Architectures - Application to Image Processing: The Extraction of Regions of Interests.	ASAP	1995	DBLP DOI BibTeX RDF
15	Markus Theißinger, Paul Stravers, Holger Veit	CASTLE: an interactive environment for HW-SW Co-Design.	CODES	1994	DBLP DOI BibTeX RDF
15	Jayaram Bhasker, Huan-Chih Lee	An Optimizer for Hardware Synthesis.	IEEE Des. Test Comput.	1990	DBLP DOI BibTeX RDF
15	Nikil D. Dutt, Tedd Hadley, Daniel Gajski	An Intermediate Representation for Behavioral Synthesis.	DAC	1990	DBLP DOI BibTeX RDF
14	Mohamed Ali Hajjaji, Adnen Albouchi	Study and VHDL implementation of a novel chaos-based block cipher algorithm for digital image security.	J. Electronic Imaging	2024	DBLP DOI BibTeX RDF
14	Heba M. Abdel-Atty, Saly S. Hassaneen, Heba Y. M. Soliman	VHDL implementation of circular shifting-partial transmit sequence in MIMO OFDM systems.	Int. J. Commun. Syst.	2023	DBLP DOI BibTeX RDF
14	Cristinel Ababei, Susan C. Schneider	Hardware Description of Event-driven Systems by Translation of UML Statecharts to VHDL.	eIT	2023	DBLP DOI BibTeX RDF
14	Noah Mogensen, Daniel DeFreez	Transpiling Nand2Tetris to VHDL for Teaching Digital Logic.	ITiCSE (2)	2023	DBLP DOI BibTeX RDF
14	Rafael Corsi Ferrão, Igor dos Santos Montagner, Renan Trevisoli	Moving Beyond VHDL in Introductory Computer Architecture Courses: An Exploration of MyHDL as a Modern Alternative.	FIE	2023	DBLP DOI BibTeX RDF
14	Kaveh Sadeghikhah, Lei Zhang 0092, Raman Paranjape	An Efficient VHDL Implementation of two Artificial Neural Networks on Zynq-7000 FPGA.	CCECE	2023	DBLP DOI BibTeX RDF
14	Ivan Zholubak, Valeriy Hlukhov	Validation of Multipliers for Elements of Extended Galois Fields GF(pn) and Multipliers VHDL-descriptions Generator.	CSIT	2023	DBLP DOI BibTeX RDF
14	Wilayat Khan, Zhe Hou, David Sanán, Jamel Nebhen, Yang Liu 0003, Alwen Tiu	An Executable Formal Model of the VHDL in Isabelle/HOL.	CoRR	2022	DBLP BibTeX RDF
14	Kazuyuki Kojima	Automatic VHDL Description for Mechatronics System by Using Evolutionary Computation.	ICCCM	2022	DBLP DOI BibTeX RDF
14	Luciano Silva, Marcel Oliveira	Automatic Generation of Verified Concurrent Hardware Using VHDL.	SBMF	2022	DBLP DOI BibTeX RDF
14	Parisa Mashreghi-Moghadam, Tarek Ould-Bachir, Yvon Savaria	A Templated VHDL Architecture for Terabit/s P4-programmable FPGA-based Packet Parsing.	ISCAS	2022	DBLP DOI BibTeX RDF
14	Taofiki Saliyu, Xingang Fu, Chanakya Hingu	VHDL Schematic Design and FPGA Simulation of Neural Network Activation Function using Continued Fractions.	UEMCON	2022	DBLP DOI BibTeX RDF
14	Martín N. Menéndez, Santiago Germino, Facundo S. Larosa, Ariel Lutenberg	Automatic generation of VHDL code for a railway interlocking system.	Int. J. Embed. Syst.	2021	DBLP DOI BibTeX RDF
14	Talal Bonny	Chaotic or Hyper-chaotic Oscillator? Numerical Solution, Circuit Design, MATLAB HDL-Coder Implementation, VHDL Code, Security Analysis, and FPGA Realization.	Circuits Syst. Signal Process.	2021	DBLP DOI BibTeX RDF
14	Sachin Maheshwari, Viv A. Bartlett, Izzet Kale	A VHDL-Based Modeling Approach for Rapid Functional Simulation and Verification of Adiabatic Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2021	DBLP DOI BibTeX RDF
14	Md Arefin Rabbi Emon, Hasan Jamil Apon, Fahim Faisal, Mirza Muntasir Nishat, Khandakar Adil Morshed, Ahmed Mujtaba Al Naser, Fatema Zerin Jaba, Fariha Anzum	Advanced Encryption Standard for embedded applications: An FPGA-based implementation using VHDL.	MENACOMM	2021	DBLP DOI BibTeX RDF
14	Jakub Lojda, Richard Panek, Zdenek Kotásek	Automatic Design of Fault-Tolerant Systems for VHDL and SRAM-based FPGAs.	DSD	2021	DBLP DOI BibTeX RDF
14	Sara Ricci, Petr Jedlicka, Peter Cíbik, Petr Dzurenda, Lukas Malina, Jan Hajny	Towards CRYSTALS-Kyber VHDL Implementation.	SECRYPT	2021	DBLP DOI BibTeX RDF
14	Viktor V. Zhukovskyy, Dmytro Dmitriev, Nataliia A. Zhukovska, Andriy Safonyk, Andrij Sydor	VHDL Compiler with Natural Parallel Comands Execution.	EUROCON	2021	DBLP DOI BibTeX RDF
14	Nejmeddine Sifi, Raja Maghrebi	Design and Implementation of a Band-Pass SD Modulator Model with Non-Idealities using Simplorer VHDL.	SSD	2021	DBLP DOI BibTeX RDF
14	John A. Kalomiros, John V. Vourvoulakis	The Robin Soft-Core: A Paradigm for Studying VHDL and Computer Architecture.	IDAACS	2021	DBLP DOI BibTeX RDF
14	Vyacheslav Kharchenko, Sergey F. Tyurin, Herman Fesenko, Oleg Goncharovskij	The Fault Tolerant Černý Finite State Machine: a Concept and VHDL Models.	IDAACS	2021	DBLP DOI BibTeX RDF
14	Pablo Rubio-Ibáñez, J. Javier Martínez-Álvarez, Ginés Doménech-Asensi	A library-based tool to translate high level DNN models into hierarchical VHDL descriptions.	DCIS	2021	DBLP DOI BibTeX RDF
14	Botond Sándor Kirei, Calin Adrian Farcas, Marina Dana Topa	PAElib 2.0: Power&Area Aware Modeling of CMOS Digital Circuits in VHDL.	TSP	2020	DBLP DOI BibTeX RDF
14	Sachin Maheshwari, Vivian A. Bartlett, Izzet Kale	Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach.	Integr.	2019	DBLP DOI BibTeX RDF
14	Alessandro Leoni, Pietro Nannipieri, Luca Fanucci	VHDL Design of a SpaceFibre Routing Switch.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2019	DBLP DOI BibTeX RDF
14	David Aledo, Benjamin Carrión Schäfer, Félix Moreno	VHDL vs. SystemC: Design of Highly Parameterizable Artificial Neural Networks.	IEICE Trans. Inf. Syst.	2019	DBLP DOI BibTeX RDF
14	Jordan M. Gilbert, Catherine Robbins, Waseem Sheikh	FPGA implementation of error control codes in VHDL: An undergraduate research project.	Comput. Appl. Eng. Educ.	2019	DBLP DOI BibTeX RDF
14	Godofredo R. Garay, Andrei Tchernykh, Alexander Yu. Drozdov, Sergey N. Garichev, Sergio Nesmachnow, Moisés Torres-Martinez	Visualization of VHDL-based simulations as a pedagogical tool for supporting computer science education.	J. Comput. Sci.	2019	DBLP DOI BibTeX RDF
14	Frank Martínez-Suárez, Carlos Alvarado-Serrano	VHDL Module for the R Wave Detection in Real Time Using Continuous Wavelet Transform.	CCE	2019	DBLP DOI BibTeX RDF
14	Andrej Trost, Andrej Zemva	Online VHDL Generator and Analysis Tool.	MECO	2019	DBLP DOI BibTeX RDF
14	Pablo Rubio-Ibáñez, J. Javier Martínez-Álvarez, Ginés Doménech-Asensi	Efficient VHDL Implementation of an Upscaling Function for Real Time Video Applications.	ISCAS	2019	DBLP DOI BibTeX RDF
14	Hannelore Filipescu, Petru Papazian	VHDL-AMS Modelling And FPGA Implementation Of Electrodermal Centers Analyzer.	TSP	2019	DBLP DOI BibTeX RDF
14	Marcin Chojnacki, Przemyslaw Sekalski	Stage-oriented, Mixed Design Methodology for Image Processing Using VHDL and Python.	MIXDES	2019	DBLP DOI BibTeX RDF
14	Raja Muthalagu, Rahul Sudheer, Seyed Ibrahim	FPGA Implementation of Optimized QPSK and OQPSK Using VHDL.	J. Commun.	2018	DBLP DOI BibTeX RDF
14	Pavel Benácek, Viktor Pus, Hana Kubátová, Tomás Cejka	P4-To-VHDL: Automatic generation of high-speed input and output network blocks.	Microprocess. Microsystems	2018	DBLP DOI BibTeX RDF
14	Sachin Maheshwari, Vivian A. Bartlett, Izzet Kale	VHDL-Based Modelling Approach for the Digital Simulation of 4-Phase Adiabatic Logic Design.	PATMOS	2018	DBLP DOI BibTeX RDF
14	Martin Mosbeck, Daniel Hauer, Axel Jantsch	VELS: VHDL E-Learning System for Automatic Generation and Evaluation of Per-Student Randomized Assignments.	NORCAS	2018	DBLP DOI BibTeX RDF
14	Sang Un Park, Tae Pyeong Kim, Mee Zee Lee, Yong Beom Cho	Method of RTL Debugging When Using HLS for HW Design : Different Simulation Result of Verilog & VHDL.	ISOCC	2018	DBLP DOI BibTeX RDF
14	Zaid Al-Wardi, Robert Wille, Rolf Drechsler	Towards VHDL-Based Design of Reversible Circuits - Work in Progress Report.	RC	2017	DBLP DOI BibTeX RDF
14	Rached Zrafi, Sami Ghedira, Yassin Dhahri, Kamel Besbes	Bond graph based automated modeling of switch-mode power converters using VHDL-AMS.	ICCAD	2017	DBLP DOI BibTeX RDF
14	Muhammad K. A. Hamdan, Diane T. Rover	VHDL generator for a high performance convolutional neural network FPGA-based accelerator.	ReConFig	2017	DBLP DOI BibTeX RDF
14	Davide Bellizia, Pietro Monsurrò, Alessandro Trifiletti	VHDL implementation of FWL RLS algorithm.	ECCTD	2017	DBLP DOI BibTeX RDF
14	Sabah Al-Fedaghi, Sari Sultan	Flow machine diagrams for VHDL code.	ICC	2017	DBLP DOI BibTeX RDF
14	Ilya Tuzov, Juan Carlos Ruiz, David de Andrés	Accurately Simulating the Effects of Faults in VHDL Models Described at the Implementation-Level.	EDCC	2017	DBLP DOI BibTeX RDF
14	Lei Zhang 0092	Hénon map chaotic system analysis and VHDL-based fixed-point FPGA implementation for brain stimulation.	CCECE	2017	DBLP DOI BibTeX RDF
14	Beauti Khataniar, Manoj Kumar	VHDL Implementation of NOC Architecture for UART Using Round Robin Arbiter.	CICBA (1)	2017	DBLP DOI BibTeX RDF
14	Irfan A. Landge, B. K. Mishra	Comparing VHDL Based Hardware Implementation of Blowfish and Twofish Algorithms for Designing Secured Embedded System.	CICBA (1)	2017	DBLP DOI BibTeX RDF
14	Hanene Rouabeh, Chokri Abdelmoula, Mohamed Masmoudi	A new efficient connected component labeling algorithm and its VHDL circuit.	ICM	2016	DBLP DOI BibTeX RDF
14	Flavilene S. Souza, Nobuo Oki, Jozue V. Filho, Richard Loendersloot, Arthur P. Berkhoff	Accuracy and multi domain piezoelectric power harvesting model using VHDL-AMS and SPICE.	IEEE SENSORS	2016	DBLP DOI BibTeX RDF
14	Luis Gustavo Perpetuo Costa Marques, Max Hering de Queiroz, Jean-Marie Farines	Improving a design methodology of synthesizable VHDL with formal verification.	LASCAS	2016	DBLP DOI BibTeX RDF
14	Pavel Benácek, Viktor Pus, Hana Kubátová	P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers.	FCCM	2016	DBLP DOI BibTeX RDF
14	Okan Zafer Batur, Günhan Dündar, Mutlu Koca	MATLAB & VHDL-AMS co-simulation environment for IR-UWB transceiver design.	SMACD	2016	DBLP DOI BibTeX RDF
14	Jennifer L. Bonniwell, Susan C. Schneider	Using the Basys-3 Trainer to support VHDL in Digital Logic Fundamentals course.	FIE	2016	DBLP DOI BibTeX RDF
14	Ayoub Nouri, Rahma Ben Atitallah, Anca Molnos, Christian Fabre, Frédéric Heitzmann, Olivier Debicki	Transforming VHDL descriptions into formal component-based models.	RSP	2016	DBLP DOI BibTeX RDF
14	Kausik Datta, Goutam Kumar Bhaumik, Rohit Goel	An Introduction to VHDL 2008.	VLSID	2016	DBLP DOI BibTeX RDF
14	Afsaneh Shahim-Aeen, Gholamreza Karimi	Triplet-based spike timing dependent plasticity (TSTDP) modeling using VHDL-AMS.	Neurocomputing	2015	DBLP DOI BibTeX RDF
14	Wojciech M. Zabolotny	Automatic latency balancing in VHDL-implemented complex pipelined systems.	CoRR	2015	DBLP BibTeX RDF
14	Roberto Urban, Mario Schölzel, Heinrich Theodor Vierhaus, Enrico Altmann, Horst Seelig	Compiler-Centred Microprocessor Design (CoMet) - From C-Code to a VHDL Model of an ASIP.	DDECS	2015	DBLP DOI BibTeX RDF
14	Ahmed A. Rezk, Amr Helmy, Yehea Ismail	VHDL implementation of a power management algorithm for PV-battery system.	ICEAC	2015	DBLP DOI BibTeX RDF
14	José Miguel Montañana, Lenin-G. Lemus-Zúñiga, Arnulfo Alanis Garza, José-Vicente Benlloch-Dualde	Teaching strategy on VHDL course based on participative learning.	ITHET	2015	DBLP DOI BibTeX RDF
14	Tolga Ayav, Tugkan Tuglular, Fevzi Belli	Model Based Testing of VHDL Programs.	COMPSAC Workshops	2015	DBLP DOI BibTeX RDF
14	Renato Baldini Filho, Unias de Lucena Antonio	A Study on VHDL Implementation of a Class of Irregular Structured LDPC Codes applied to 100 Gbps Optical Networks.	LAWC@LATINCOM	2015	DBLP BibTeX RDF
14	Qianqian Ha, Yannick Maret, Juan Sebastian Rodriguez Estupinan, Alain Vachoux	VHDL-AMS virtual prototyping of a generator circuit breaker ablation monitoring system.	ISCAS	2015	DBLP DOI BibTeX RDF
14	Muhammad Husni Santriaji, Arif Sasongko	Optimized VHDL-based Karatsuba polynomial multiplier generator for GF(2n).	ISPACS	2015	DBLP DOI BibTeX RDF
14	Hüseyin Oktay Erkol, Hüseyin Demirel	A VHDL application for kinematic equation solutions of multi-degree-of-freedom systems.	J. Zhejiang Univ. Sci. C	2014	DBLP DOI BibTeX RDF
14	Patrice Micouin	Property-Model Methodology: A Model-Based Systems Engineering Approach Using VHDL-AMS.	Syst. Eng.	2014	DBLP DOI BibTeX RDF
14	Tomás Balderas-Contreras, René Cumplido, Gustavo Rodríguez Gómez	Synthesizing VHDL from Activity Models in UML 2.	Int. J. Circuit Theory Appl.	2014	DBLP DOI BibTeX RDF
14	Tanusree Chatterjee, Abhishek Bhattacharya	VHDL Modeling of Intrusion Detection & Prevention System (IDPS) A Neural Network Approach.	CoRR	2014	DBLP BibTeX RDF
14	Vacius Jusas, Tomas Neverdauskas	Stimuli generation framework for testing multiple processes in VHDL.	Inf. Technol. Control.	2014	DBLP DOI BibTeX RDF
14	Pavel Fiala, Richard Linhart	Efficient VHDL implementation of symbol synchronization for software radio based on FPGA.	DDECS	2014	DBLP DOI BibTeX RDF
14	Kousik Dan	Evolution of conventional antilogarithmic approach and implementation in FPGA through VHDL.	ICACCI	2014	DBLP DOI BibTeX RDF
14	Marcela Leite, Marco Aurélio Wehrmeister	Aspect-Oriented Model-Driven Engineering for FPGA/VHDL Based Embedded Real-Time Systems.	ISORC	2014	DBLP DOI BibTeX RDF
14	Minas Dasygenis	A distributed VHDL compiler and simulator accessible from the web.	PATMOS	2014	DBLP DOI BibTeX RDF
14	Michal Melosik, Wieslaw Marszalek	A hybrid chaos-based pseudo-random bit generator in VHDL-AMS.	MWSCAS	2014	DBLP DOI BibTeX RDF
14	Dat Tran, Kiet Duong, Ujjal K. Bhowmik	A VHDL Based Controller Design for Non-contact Temperature and Breathing Sensors Suitable for Crib.	BIBE	2014	DBLP DOI BibTeX RDF
14	Vacius Jusas, Tomas Neverdauskas	Stimuli generator for testing processes in VHDL.	NORCHIP	2014	DBLP DOI BibTeX RDF
14	Marco Aurélio Wehrmeister, Marcela Leite	On Generating VHDL Descriptions from Aspect-Oriented UML/MARTE Models.	SBESC	2014	DBLP DOI BibTeX RDF
14	Mickael Lanoe, Matteo Bordin, Dominique Heller, Philippe Coussy, Cyrille Chavet	A modeling and code generation framework for critical embedded systems design: From Simulink down to VHDL and Ada/C code.	ICECS	2014	DBLP DOI BibTeX RDF
14	Toufik Merdjana, Abdelhafid Chaabi, Sawsen Rouabah	VHDL-AMS and PSPICE modeling of ultrasonic piezoelectric transducer for biological mediums application.	ATSIP	2014	DBLP DOI BibTeX RDF
14	Sahbi Baccar, Timothée Levi, Dominique Dallet, François Barbara	Modeling and simulation of an instrumentation amplifier in high temperature using a VHDL-AMS op-amp model.	NEWCAS	2014	DBLP DOI BibTeX RDF
14	José Daniel Muñoz Frías, Sadot Alexandres Fernandez	A first year, VHDL based, digital electronics course.	FIE	2014	DBLP DOI BibTeX RDF
14	Marcelo de Oliveira Rosa, Wyllian Bezerra da Silva, Keiko Verônica Ono Fonseca, Alexandre de Almeida Prado Pohl	VHDL implementation of a No-Reference video quality metric using the Levenberg-Marquardt method.	BMSB	2014	DBLP DOI BibTeX RDF
14	Todd E. Schmuland, Mohsin M. Jamali	Generation of fixed-point VHDL MIMO-OFDM QR pre-processor for Spherical Detectors.	ISCAS	2014	DBLP DOI BibTeX RDF
14	Daniel Chaves Cafe, Cécile Hardebolle, Christophe Jacquet, Filipe Vinci dos Santos, Frédéric Boulanger	Discrete-Continuous Semantic Adaptations for Simulating SysML Models in VHDL-AMS.	MPM@MoDELS	2014	DBLP BibTeX RDF
14	Blagoj Jovanov, Aristotel Tentov	Modeling Intel 8085A in VHDL.	CSOC	2014	DBLP DOI BibTeX RDF
14	Daniel-Eugen Butoianu, Doru Todinca	Performance Evaluation of Fuzzy Automata Using VHDL Simulation.	SYNASC	2014	DBLP DOI BibTeX RDF
14	Minas Dasygenis	A web EDA tool for the automatic generation of synthesizable VHDL architectures for a rapid design space exploration.	DTIS	2014	DBLP DOI BibTeX RDF
14	Marcela Leite, Cristiano D. Vasconcellos, Marco Aurélio Wehrmeister	Enhancing automatic generation of VHDL descriptions from UML/MARTE models.	INDIN	2014	DBLP DOI BibTeX RDF
14	Agnieszka Dabrowska-Boruch, Grzegorz Gancarczyk, Kazimierz Wiatr	Implementation of a RANLUX Based Pseudo-Random Number Generator in FPGA Using VHDL and Impulse C.	Comput. Informatics	2013	DBLP BibTeX RDF
14	Pedro Martín, Emilio José Bueno, Francisco J. Rodríguez 0001, Osmell Machado, Branislav Vuksanovic	An FPGA-based approach to the automatic generation of VHDL code for industrial control systems applications: A case study of MSOGIs implementation.	Math. Comput. Simul.	2013	DBLP DOI BibTeX RDF
14	Abir Rezgui, Laurent Gerbaud, Benoit Delinchant	Unified modeling technique using VHDL-AMS and software components.	Math. Comput. Simul.	2013	DBLP DOI BibTeX RDF
14	Patrice Micouin	Model Based Systems Engineering using VHDL-AMS.	CSER	2013	DBLP DOI BibTeX RDF
14	Ginés Doménech-Asensi, José Ángel Díaz-Madrid, Ramón Ruiz Merino	Synthesis of CMOS analog circuit VHDL-AMS descriptions using parameterizable macromodels.	Int. J. Circuit Theory Appl.	2013	DBLP DOI BibTeX RDF