Search results for "finfet"

Hits ?▲	Authors	Title	Venue	Year	Link
14	Bhuvana B. P., V. S. Kanchana Bhaaskaran	Design of FinFET-based Energy Efficient Pass-Transistor Adiabatic Logic for ultra-low power applications.	Microelectron. J.	2019	DBLP DOI BibTeX RDF
14	Reena Sonkusare, Omkar Joshi, Surendra S. Rathod	SOI FinFET based instrumentation amplifier for biomedical applications.	Microelectron. J.	2019	DBLP DOI BibTeX RDF
14	Mir Muntasir Hossain, Satyendra N. Biswas	Analysis and Design of a 32nm FinFET Dynamic Latch Comparator.	CoRR	2019	DBLP BibTeX RDF
14	Sohaib Majzoub, Mottaqiallah Taouil, Said Hamdioui	System-Level Sub-20 nm Planar and FinFET CMOS Delay Modelling for Supply and Threshold Voltage Scaling Under Process Variation.	J. Low Power Electron.	2019	DBLP DOI BibTeX RDF
14	Kayode A. Sanni, Andreas G. Andreou	A Historical Perspective on Hardware AI Inference, Charge-Based Computational Circuits and an 8 bit Charge-Based Multiply-Add Core in 16 nm FinFET CMOS.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2019	DBLP DOI BibTeX RDF
14	Chien-Ping Wang, Ying-Chun Shen, Peng-Chun Liou, Yu-Lun Chueh, Yue-Der Chih, Jonathan Chang, Chrong Jung Lin, Ya-Chin King	Dynamic pH Sensor with Embedded Calibration Scheme by Advanced CMOS FinFET Technology.	Sensors	2019	DBLP DOI BibTeX RDF
14	Matthias Eberlein, Harald Pretl, Z. Georgiev	Time-Controlled and FinFET Compatible Sub-Bandgap References Using Bulk-Diodes.	IEEE Trans. Circuits Syst. II Express Briefs	2019	DBLP DOI BibTeX RDF
14	Jaekwon Kim, Woojin Jang, Yanghoon Lee, Wan Kim, Seunghyun Oh, Jongwoo Lee, Jaehyuk Choi 0001, Jung-Hoon Chun, Thomas Byunghak Cho	Design and Analysis of a 12-b Current-Steering DAC in a 14-nm FinFET Technology for 2G/3G/4G Cellular Applications.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
14	Farid Kenarangi, Inna Partin-Vaisband	Leveraging Independent Double-Gate FinFET Devices for Machine Learning Classification.	IEEE Trans. Circuits Syst. I Regul. Pap.	2019	DBLP DOI BibTeX RDF
14	Jieqiong Du, Chien-Heng Wong, Yo-Hao Tu, Wei-Han Cho, Yilei Li, Yuan Du, Po-Tsang Huang, Sheau Jiung Lee, Mau-Chung Frank Chang	A 7.5-mW 10-Gb/s 16-QAM wireline transceiver with carrier synchronization and threshold calibration for mobile inter-chip communications in 16-nm FinFET.	NOCS	2019	DBLP DOI BibTeX RDF
14	Kangqi Chen, Erdal Oruklu	Side-Channel Attack Resilient Design of a 10T SRAM Cell in 7nm FinFET Technology.	MWSCAS	2019	DBLP DOI BibTeX RDF
14	Bakr Hesham, El-Sayed A. M. Hasaneen, Hesham F. A. Hamed	Design Procedure for Two-Stage CMOS Opamp using gm/ID design Methodology in 16 nm FinFET Technology.	ICM	2019	DBLP DOI BibTeX RDF
14	Amin A. Zayed, Hanady Hussien Issa, Khaled A. Shehata	FinFET Based Low Power Ring Oscillator Physical Unclonable Functions.	ICM	2019	DBLP DOI BibTeX RDF
14	Leonardo B. Moraes, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Augusto da Luz Reis	Robustness and Minimum Energy-Oriented FinFET Design.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
14	Leonardo Heitich Brendler, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Reis 0001	Process Variability Impact on the SET Response of FinFET Multi-level Design.	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
14	Alexandra L. Zimpeck, Cristina Meinhardt, Laurent Artola, Guillaume Hubert, Fernanda Lima Kastensmidt, Ricardo Augusto da Luz Reis	Circuit-Level Techniques to Mitigate Process Variability and Soft Errors in FinFET Designs.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
14	Leonardo Heitich Brendler, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo A. L. Reis	Evaluation of SET under Process Variability on FinFET Multi-level Design.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
14	Leonardo B. Moraes, Alexandra Lackmann Zimpeck, Cristina Meinhardt, Ricardo A. L. Reis	Robust FinFET Schmitt Trigger Designs for Low Power Applications.	VLSI-SoC (Selected Papers)	2019	DBLP DOI BibTeX RDF
14	Leonardo B. Moraes, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Augusto da Luz Reis	Minimum Energy FinFET Schmitt Trigger Design Considering Process Variability.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
14	Leonardo Heitich Brendler, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo A. L. Reis	Impact of Process Variability and Single Event Transient on FinFET Technology.	VLSI-SoC	2019	DBLP DOI BibTeX RDF
14	Taiki Uemura, Soonyoung Lee, Dahye Min, Ihlhwa Moon, Seungbae Lee, Sangwoo Pae	SEIFF: Soft Error Immune Flip-Flop for Mitigating Single Event Upset and Single Event Transient in 10 nm FinFET.	IRPS	2019	DBLP DOI BibTeX RDF
14	Gaspard Hiblot, Yefan Liu, Geert Hellings, Geert Van der Plas	Comparative Analysis of the Degradation Mechanisms in Logic and I/O FinFET Devices Induced by Plasma Damage.	IRPS	2019	DBLP DOI BibTeX RDF
14	Bonnie E. Weir, Vani Prasad, Shahriar Moinian, SangJune Park, Joseph Blasko, Jason Brown, Jayanthi Pallinti	Utilizing a Thorough Understanding of Critical Aging and Failure Mechanisms in finFET Technologies to Enable Reliable High Performance Circuits.	IRPS	2019	DBLP DOI BibTeX RDF
14	Jingchen Cao, Lyuan Xu, Bharat L. Bhuva, Shi-Jie Wen, Richard Wong, Balaji Narasimham, Lloyd W. Massengill	Alpha Particle Soft-Error Rates for D-FF Designs in 16-Nm and 7-Nm Bulk FinFET Technologies.	IRPS	2019	DBLP DOI BibTeX RDF
14	Benyuan Zhu, E. M. Bazizi, J. H. M. Tng, Z. Li, E. K. Banghart, M. K. Hassan, Y. Hu, D. Zhou, D. Choi, L. Qin, Xuan Wan	TCAD Simulation on FinFET n-type Power Device HCI Reliability Improvement.	IRPS	2019	DBLP DOI BibTeX RDF
14	Shih-Hung Chen, Dimitri Linten, Geert Hellings, Marko Simicic, Ben Kaczer, Thomas Chiarella, Hans Mertens, Jérôme Mitard, Anda Mocuta, N. Horiguchi	CDM-Time Domain Turn-on Transient of ESD Diodes in Bulk FinFET and GAA NW Technologies.	IRPS	2019	DBLP DOI BibTeX RDF
14	Lyuan Xu, Jingchen Cao, Bharat L. Bhuva, Indranil Chatterjee, Shi-Jie Wen, Richard Wong, Lloyd W. Massengill	Single-Event Upset Responses of Dual- and Triple-Well D Flip-Flop Designs in 7-nm Bulk FinFET Technology.	IRPS	2019	DBLP DOI BibTeX RDF
14	Xinggon Wan, Baofu Zhu, Meera Mohan, Keija Wu, Dongil Choi, Arfa Gondal	HCI Improvement on 14nm FinFET IO Device by Optimization of 3D Junction Profile.	IRPS	2019	DBLP DOI BibTeX RDF
14	Balaji Narasimham, K. Chandrasekharan, J. K. Wang, Bharat L. Bhuva	Soft Error Performance of High-Speed Pulsed-DICE-Latch Design in 16 nm and 7 nm FinFET Processes.	IRPS	2019	DBLP DOI BibTeX RDF
14	James A. O'Donnell, Chris Connor, Tanmoy Pramanik, Jeff Hicks, Juan G. Alzate, Fatih Hamzaoglu, Justin Brockman, Oleg Golonzka, Kevin Fischer	eNVM MRAM Retention Reliability Modeling in 22FFL FinFET Technology.	IRPS	2019	DBLP DOI BibTeX RDF
14	Frank Sill Torres, Hussam Amrouch, Jörg Henkel, Rolf Drechsler	Impact of NBTI on Increasing the Susceptibility of FinFET to Radiation.	IRPS	2019	DBLP DOI BibTeX RDF
14	Guilherme Cardoso Medeiros, Mottaqiallah Taouil, Moritz Fieback, Leticia Bolzani Poehls, Said Hamdioui	DFT Scheme for Hard-to-Detect Faults in FinFET SRAMs.	ETS	2019	DBLP DOI BibTeX RDF
14	Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Stephen G. Tell, Brian Zimmer, Tezaswi Raja, Kevin Zhou, William J. Dally, Brucek Khailany	A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET.	ASYNC	2019	DBLP DOI BibTeX RDF
14	Konstantinos Maragos 0001, Endri Taka, George Lentaris, Ioannis Stratakos, Dimitrios Soudris	Analysis of Performance Variation in 16nm FinFET FPGA Devices.	FPL	2019	DBLP DOI BibTeX RDF
14	Adriana Arevalo, Romain Liautard, Daniel Romero, Lionel Trojman, Luis-Miguel Procel	New insight for next generation SRAM: tunnel FET versus FinFET for different topologies.	SBCCI	2019	DBLP DOI BibTeX RDF
14	Fabio G. Rossato G. da Silva, Cristina Meinhardt, Ricardo Augusto da Luz Reis	FinFET Variability and Near-threshold operation: Impact on Full Adders design using XOR Blocks.	ICECS	2019	DBLP DOI BibTeX RDF
14	Rafael N. M. Oliveira, Alan D. Lüdke, Cristina Meinhardt	Radiation Effects in XOR Logic Gates at 16nm CMOS and FinFET Technology.	ICECS	2019	DBLP DOI BibTeX RDF
14	Federico Fary, Marcello De Matteis, Luciano Rota, Martina Arosio, Andrea Baschirotto	A 16 nm-FinFET 100 MHz 4th-order Fully-Differential Super-Source-Follower Analog Filter.	ICECS	2019	DBLP DOI BibTeX RDF
14	Hsin-Chia Yang, Kai-Hung Hsieh, Hsiu-Hsien Yu, Chun-Yian Chang, Kun-Hong Liao, Yu-Jung Liao, Sung-Ching Chi	An Alternative Algorithm to Fit All-Aspect Current-Voltage Characteristics Curves on FinFET Devices.	ICKII	2019	DBLP DOI BibTeX RDF
14	Yorgos Palaskas, Peter Plechinger, Ashoke Ravi, Ofir Degani, Rotem Banin, Eshel Gordon, Zdravko Boos, Paolo Madoglio, Jörn Angel, Jakob M. Tomasik, Sven Hampel, Petra Schubert, Peter Preyler, Thomas Mayer 0003, Thomas Bauernfeind	A Cellular Multiband DTC-Based Digital Polar Transmitter With -153 dBc/Hz Noise in 14-nm FinFET.	ESSCIRC	2019	DBLP DOI BibTeX RDF
14	Matthias Eberlein, Harald Pretl	A No-Trim, Scaling-Friendly Thermal Sensor in 16nm FinFET Using Bulk Diodes as Sensing Elements.	ESSCIRC	2019	DBLP DOI BibTeX RDF
14	Yuriy M. Greshishchev, Tingjun Wen, Naim Ben-Hamida, Jorge Aguirre, Sadok Aouini, Marinette Besson, Robert Gibbins, Young Gouk Cho, Jerry Lam, Douglas McPherson, Mahdi Parvizi	A 60 GS/s 8-b DAC with > 29.5dB SINAD up to Nyquist frequency in 7nm FinFET CMOS.	BCICTS	2019	DBLP DOI BibTeX RDF
14	Marc Erett, Declan Carey, Ronan Casey, James Hudner, Kevin Geary, Ted Lee, Mayank Raj, Hongtao Zhang 0002, Arianne Roldan, Hongyuan Zhao, Ping-Chuan Chiang, Haibing Zhao, Nakul Narang, Pedro Neto 0001, Bruce Xu, Winson Lin, Kee Hian Tan, Yohan Frans, Ken Chang	A 2.25pJ/bit Multi-lane Transceiver for Short Reach Intra-package and Inter-package Communication in 16nm FinFET.	CICC	2019	DBLP DOI BibTeX RDF
14	Sanquan Song, John Poulton, Xi Chen 0033, Brian Zimmer, Stephen G. Tell, Walker J. Turner, Sudhir S. Kudva, Nikola Nedovic, John M. Wilson 0002, C. Thomas Gray, William J. Dally	A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET.	CICC	2019	DBLP DOI BibTeX RDF
14	Xi Chen 0033, Sanquan Song, John Poulton, Nikola Nedovic, Brian Zimmer, Stephen G. Tell, C. Thomas Gray	Voltage-Follower Coupling Quadrature Oscillator with Embedded Phase-Interpolator in 16nm FinFET.	CICC	2019	DBLP DOI BibTeX RDF
14	Dirk Pfaff, Robert Abbott, Xin-Jie Wang, Babak Zamanlooy, Shahaboddin Moazzeni, Raleigh Smith, Chih-Chang Lin	A 14-GHz Bang-Bang Digital PLL with sub-150fs Integrated Jitter for Wireline Applications in 7nm FinFET.	CICC	2019	DBLP DOI BibTeX RDF
14	Shih-Hung Chen	Esd Challenges in Advanced Finfet and Gaa Nanowire cmos Technologies: Designing Diode Based ESD Protection in Advanced State of the Art Technologies.	CICC	2019	DBLP DOI BibTeX RDF
14	Jaeduk Han, Eric Chang, Stevo Bailey, Zhongkai Wang, Woo-Rham Bae, Angie Wang, Nathan Narevsky, Amy Whitcombe, Pengpeng Lu, Borivoje Nikolic, Elad Alon	A Generated 7GS/s 8b Time-Interleaved SAR ADC with 38.2dB SNDR at Nyquist in 16nm CMOS FinFET.	CICC	2019	DBLP DOI BibTeX RDF
14	Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Hazar Yueksel, Cosimo Aprile, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Andreas Burg, Thomas Toifl, Yusuf Leblebici	A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET.	ISSCC	2019	DBLP DOI BibTeX RDF
14	Pulkit Jain, Umut Arslan, Meenakshi Sekhar, Blake C. Lin, Liqiong Wei, Tanaya Sahu, Juan Alzate-vinasco, Ajay Vangapaty, Mesut Meterelliyoz, Nathan Strutt, Albert B. Chen, Patrick Hentges, Pedro A. Quintero, Chris Connor, Oleg Golonzka, Kevin Fischer, Fatih Hamzaoglu	A 3.6Mb 10.1Mb/mm2 Embedded Non-Volatile ReRAM Macro in 22nm FinFET Technology with Adaptive Forming/Set/Reset Schemes Yielding Down to 0.5V with Sensing Time of 5ns at 0.7V.	ISSCC	2019	DBLP DOI BibTeX RDF
14	Stefano Pellerano, Steven Callender, Woorim Shin, Yanjie Wang, Somnath Kundu, Abhishek Agrawal, Peter Sagazio, Brent R. Carlton, Farhana Sheikh, Arnaud Amadjikpe, William J. Lambert, Divya Shree Vemparala, Mark Chakravorti, Satoshi Suzuki, Robert Flory, Chris Hull 0001	A Scalable 71-to-76GHz 64-Element Phased-Array Transceiver Module with 2×2 Direct-Conversion IC in 22nm FinFET CMOS Technology.	ISSCC	2019	DBLP DOI BibTeX RDF
14	Inhak Lee, Hanwool Jeong, Sangyeop Baeck, Siddharth Gupta 0008, Changnam Park, Dongwook Seo, Jaeseung Choi 0001, Jaeyoung Kim, Hoon Kim, Jungmyung Kang, Sunyung Jang, Daeyoung Moon, Sangshin Han, Taehyung Kim, Jaehyun Lim, Younghwan Park, Hyejin Hwang, Jeonseung Kang, Taejoong Song	A Voltage and Temperature Tracking SRAM Assist Supporting 740mV Dual-Rail Offset for Low-Power and High-Performance Applications in 7nm EUV FinFET Technology.	ISSCC	2019	DBLP DOI BibTeX RDF
14	Chang-Feng Loi, A. Mellati, Amber Tan, A. Farhoodfar, Arun Tiruvur, Belal Helal, Bob Killips, Farshid Rafiee Rad, Jamal Riani, Jorge Pernillo, J. Sun, J. Wong, K. Abdelhalim, K. Gopalakrishnan, Kwang Young Kim, Lawrence Tse, M. Davoodi, Michael Q. Le, M. Zhang, M. Talegaonkar, P. Prabha, Ravindran Mohanavelu, S. Chong, Simon Forey, S. Netto, Sudeep Bhoja, W. Liew, Y. Duan, Y. Liao	A 400Gb/s Transceiver for PAM-4 Optical Direct-Detect Application in 16nm FinFET.	ISSCC	2019	DBLP DOI BibTeX RDF
14	Jongwoo Lee, Sangwook Han, Joonhee Lee, Byoungjoong Kang, Jeongyeol Bae, Jaehyuk Jang, Seunghyun Oh, Su-Seob Ahn, Sanghoon Kang, Quang-Diep Bui, Kiyong Son, Hyungsun Lim, Daechul Jeong, Ronghua Ni, Yongrong Zuo, Ilyong Jong, Chih-Wei Yao, Seungchan Heo, Thomas Byunghak Cho, Inyup Kang	A Sub-6GHz 5G New Radio RF Transceiver Supporting EN-DC with 3.15Gb/s DL and 1.27Gb/s UL in 14nm FinFET CMOS.	ISSCC	2019	DBLP DOI BibTeX RDF
14	Tamer A. Ali 0001, Ramy Yousry, Henry Park, Ehung Chen, Po-Shuan Weng, Yi-Chieh Huang, Chun-Cheng Liu, Chien-Hua Wu, Shih-Hao Huang, Chungshi Lin, Ke-Chung Wu, Kun-Hung Tsai, Kai-Wen Tan, Ahmed ElShater, Kuang-Ren Chen, Wei-Hao Tsai, Huan-Sheng Chen, Weiyu Leng, Mazen Soliman	A 180mW 56Gb/s DSP-Based Transceiver for High Density IOs in Data Center Switches in 7nm FinFET Technology.	ISSCC	2019	DBLP DOI BibTeX RDF
14	Tien-Yu Lo, Chan-Hsiang Weng, Hung-Yi Hsieh, Yun-Shiang Shu, Pao-Cheng Chiu	An 8 × - OSR 25MHz-BW 79.4dB/74dB DR/SNDR CT Δ σ Modulator Using 7b Linearized Segmented DACs with Digital Noise-Coupling-Compensation Filter in 7nm FinFET CMOS.	ISSCC	2019	DBLP DOI BibTeX RDF
14	Matteo Pisati, Fernando De Bernardinis, Paolo Pascale, Claudio Nani, Marco Sosio, Enrico Pozzati, Nicola Ghittori, Federico Magni, Marco Garampazzi, Giacomino Bollati, Antonio Milani, Alberto Minuti, Fabio Giunco, Paola Uggetti, Ivan Fabiano, Nicola Codega, Alessandro Bosi, Nicola Carta, Demetrio Pellicone, Giorgio Spelgatti, Massimo Cutrupi, Andrea Rossini, Roberto G. Massolini, Giovanni Cesura, Ivan Bietti	A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET.	ISSCC	2019	DBLP DOI BibTeX RDF
14	Alessandro Cevrero, Ilter Özkaya, Pier Andrea Francese, Matthias Brändli, Christian Menolfi, Thomas Morf, Marcel A. Kossel, Lukas Kull, Danny Luu, Martino Dazzi, Thomas Toifl	A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFET.	ISSCC	2019	DBLP DOI BibTeX RDF
14	Yongping Fan, Bo Xiang, Dan Zhang, James S. Ayers, Kuan-Yueh James Shen, Andrey Mezhiba	Digital Leakage Compensation for a Low-Power and Low-Jitter 0.5-to-5GHz PLL in 10nm FinFET CMOS Technology.	ISSCC	2019	DBLP DOI BibTeX RDF
14	Liqiong Wei, Juan G. Alzate, Umut Arslan, Justin Brockman, Nilanjan Das, Kevin Fischer, Tahir Ghani, Oleg Golonzka, Patrick Hentges, Rawshan Jahan, Pulkit Jain, Blake C. Lin, Mesut Meterelliyoz, Jim O'Donnell, Conor Puls, Pedro A. Quintero, Tanaya Sahu, Meenakshi Sekhar, Ajay Vangapaty, Chris Wiegand, Fatih Hamzaoglu	A 7Mb STT-MRAM in 22FFL FinFET Technology with 4ns Read Sensing Time at 0.9V Using Write-Verify-Write Scheme and Offset-Cancellation Sensing Technique.	ISSCC	2019	DBLP DOI BibTeX RDF
14	Ying-Zu Lin, Chin-Yu Lin, Shan-Chih Tsou, Chih-Hou Tsai, Chao-Hsin Lu	A 40MHz-BW 320MS/s Passive Noise-Shaping SAR ADC With Passive Signal-Residue Summation in 14nm FinFET.	ISSCC	2019	DBLP DOI BibTeX RDF
14	Dirk Pfaff, Shahaboddin Moazzeni, Leisheng Gao, Mei-Chen Chuang, Xin-Jie Wang, Chai Palusa, Robert Abbott, Rolando Ramirez, Maher Amer, Ming-Chieh Huang, Chih-Chang Lin, Fred Kuo, Wei-Li Chen, Tae Young Goh, Kenny Hsieh	A 56Gb/s Long Reach Fully Adaptive Wireline PAM-4 Transceiver in 7nm FinFET.	VLSI Circuits	2019	DBLP DOI BibTeX RDF
14	Chen-Ting Ko, Ting-Kuei Kuan, Ruei-Pin Shen, Chih-Hsien Chang, Kenny Hsieh, Mark Chen 0001	A 387.6fs Integrated Jitter and -80dBc Reference Spurs Ring based PLL with Track- and-Hold Charge Pump and Automatic Loop Gain Control in 7nm FinFET CMOS.	VLSI Circuits	2019	DBLP DOI BibTeX RDF
14	Armin Tajalli, Mani Bastani Parizi, Dario Albino Carnelli, Chen Cao, John Fox, Kiarash Gharibdoust, Davide Gorret, Amit Gupta, Christopher Hall, Ahmed Hassanin, Klaas L. Hofstra, Brian Holden, Ali Hormati, John Keay, Yohann Mogentale, G. Paul, Victor Perrin, John Phillips, Sumathi Raparthy, Amin Shokrollahi, David Stauffer, Richard Simpson, Andrew Stewart, Giuseppe Surace, Omid Talebi Amiri, Emanuele Truffa, Anton Tschank, Roger Ulrich, Christoph Walter, Anant Singh	A 1.02pJ/b 417Gb/s/mm USR Link in 16nm FinFET.	VLSI Circuits	2019	DBLP DOI BibTeX RDF
14	Wei-Chih Chen, Shu-Chun Yang, Yu-Nan Shih, Wen-Hung Huang, Chien-Chun Tsai, Kenny Cheng-Hsiang Hsieh	A 56Gb/s PAM-4 Receiver with Voltage Pre-Shift CTLE and 10-Tap DFE of Tap-1 Speculation in 7nm FinFET.	VLSI Circuits	2019	DBLP DOI BibTeX RDF
14	Mayank Raj, Yohan Frans, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Peter De Heyn, Sadhishkumar Balakrishnan, Joris Van Campenhout, Jimmy Grayson, Marc Epitaux, Ken Chang	A 50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET.	VLSI Circuits	2019	DBLP DOI BibTeX RDF
14	Kayode Sanni, Andreas G. Andreou	A Mixed-Signal Successive Approximation Architecture for Energy-Efficient Fixed-Point Arithmetic in 16nm FinFET.	ISCAS	2019	DBLP DOI BibTeX RDF
14	Harjap Singh Saini, Anu Gupta	Differential Power Analysis Immune Design of FinFET Based Novel Differential Logic Gate.	ISCAS	2019	DBLP DOI BibTeX RDF
14	Zhe-An Zheng, Vita Pi-Ho Hu	Improved Read Stability and Writability of Negative Capacitance FinFET SRAM Cell for Subthreshold Operation.	ISCAS	2019	DBLP DOI BibTeX RDF
14	Hussam Amrouch, Victor M. van Santen, Om Prakash 0007, Hammam Kattan, Sami Salamin, Simon Thomann, Jörg Henkel	Reliability Challenges with Self-Heating and Aging in FinFET Technology.	IOLTS	2019	DBLP DOI BibTeX RDF
14	Chen Sun 0010, Kaizhen Han, Xiao Gong	Performance Evaluation of Static Random Access Memory (SRAM) based on Negative Capacitance FinFET.	ICICDT	2019	DBLP DOI BibTeX RDF
14	Thiago Santos Copetti, Tiago R. Balen, E. Brum, C. Aquistapace, Leticia Bolzani Poehls	A Comparative Study Between FinFET and CMOS-Based SRAMs under Resistive Defects.	LATS	2019	DBLP DOI BibTeX RDF
14	Freddy Forero, Jean-Marc Gallière, Michel Renovell, Víctor H. Champac	A Semi-analytical Model for Interconnect Open Defects in FinFET Logic Cells.	LATS	2019	DBLP DOI BibTeX RDF
14	Jayashree K. G, Lois Priscilla S, Bhuvana B. P., V. S. Kanchana Bhaaskaran	Design and Analysis of FinFET Based CSCPAL Low Power Adder.	iSES	2019	DBLP DOI BibTeX RDF
14	Vidya A. Chhabria, Sachin S. Sapatnekar	Impact of Self-heating on Performance and Reliability in FinFET and GAAFET Designs.	ISQED	2019	DBLP DOI BibTeX RDF
14	Ming Xiao, Ruizhe Zhang 0003, Garrett Schlenvogt, Thomas Jokinen, Han Wang, Yuhao Zhang	Vertical GaN Superjunction FinFET: A Novel Device Enabling Multi-Kilovolt and Megahertz Power Switching.	DRC	2019	DBLP DOI BibTeX RDF
14	Vinay Kumar, Neeraj Kapoor, Sudhir Kumar 0002, Monila Juneja, Amit Khanuja	Area Efficient & High Performance Word Line Segmented Architecture in 7nm FinFET SRAM Compiler.	VLSID	2019	DBLP DOI BibTeX RDF
14	Shu-Han Hsu, Kexin Yang 0001, Linda Milor	Reliability and Accelerated Testing of 14nm FinFET Ring Oscillators.	DCIS	2019	DBLP DOI BibTeX RDF
14	Gain Kim, Lukas Kull, Danny Luu, Matthias Braendli, Christian Menolfi, Pier Andrea Francese, Hazar Yueksel, Cosimo Aprile, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Hyeon-Min Bae, Andreas Burg, Thomas Toifl, Yusuf Leblebici	A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET.	A-SSCC	2019	DBLP DOI BibTeX RDF
14	Barosaim Sung, Chilun Lo, Jaehoon Lee 0005, Sangdon Jung, Seungjin Kim, Jaehong Jung, Seungyong Bae, Youngsea Cho, Yong Lim, Dooseok Choi, Myeongcheol Shin, Soonwoo Choi, Byungki Han, Seunghyun Oh, Jongwoo Lee	A Blocker-Tolerant Direct Sampling Receiver for Wireless Multi-Channel Communication in 14nm FinFET CMOS.	A-SSCC	2019	DBLP DOI BibTeX RDF
14	Sangdon Jung, Jaehong Jung, Byungki Han, Seunghyun Oh, Jongwoo Lee	A 9.4MHz-to-2.4GHz Jitter-Power Reconfigurable Fractional-N Ring PLL for Multi-Standard Applications in 7nm FinFET CMOS Technology.	A-SSCC	2019	DBLP DOI BibTeX RDF
14	Matthias Eberlein, Harald Pretl	A Low-Noise Sub-Bandgap Reference with a ±0.64% Untrimmed Precision in 16nm FinFET.	A-SSCC	2019	DBLP DOI BibTeX RDF
14	Arkadiusz Malinowski, James Chen, Shiv Kumar Mishra, Srikanth Samavedam, Dong Kyun Sohn	What is Killing Moore's Law? Challenges in Advanced FinFET Technology Integration.	MIXDES	2019	DBLP DOI BibTeX RDF
14	Anushka Singh, Yash Sharma 0005, Arvind Sharma, Archana Pandey	A Novel 20nm FinFET Based 10T SRAM Cell Design for Improved Performance.	VDAT	2019	DBLP DOI BibTeX RDF
14	Shirisha Gourishetty, Harshini Mandadapu, Andleeb Zahra, Zia Abbas	A Highly Accurate Machine Learning Approach to Modelling PVT Variation Aware Leakage Power in FinFET Digital Circuits.	APCCAS	2019	DBLP DOI BibTeX RDF
14	Trong Huynh Bao, Anabela Veloso, Sushil Sakhare, Philippe Matagne, Julien Ryckaert, Manu Perumkunnil, Davide Crotti, Farrukh Yasin, Alessio Spessot, Arnaud Furnémont, Gouri Sankar Kar, Anda Mocuta	Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications.	DAC	2019	DBLP DOI BibTeX RDF
14	Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hong-Yan Su, Ming-Jie Fong, Oscar Chen, Hidetoshi Onodera	NCTUcell: A DDA-Aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid Map.	DAC	2019	DBLP DOI BibTeX RDF
14	Danny Luu, Lukas Kull, Thomas Toifl, Christian Menolfi, Matthias Braendli, Pier Andrea Francese, Thomas Morf, Marcel A. Kossel, Hazar Yueksel, Alessandro Cevrero, Ilter Özkaya, Qiuting Huang	A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
14	Ilter Özkaya, Alessandro Cevrero, Pier Andrea Francese, Christian Menolfi, Thomas Morf, Matthias Braendli, Daniel M. Kuchta, Lukas Kull, Christian W. Baks, Jonathan E. Proesel, Marcel A. Kossel, Danny Luu, Benjamin G. Lee, Fuad E. Doany, Mounir Meghelli, Yusuf Leblebici, Thomas Toifl	A 60-Gb/s 1.9-pJ/bit NRZ Optical Receiver With Low-Latency Digital CDR in 14-nm CMOS FinFET.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
14	Lukas Kull, Danny Luu, Christian Menolfi, Matthias Brändli, Pier Andrea Francese, Thomas Morf, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Thomas Toifl	A 24-72-GS/s 8-b Time-Interleaved SAR ADC With 2.0-3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
14	Mohammad Mahdi Khafaji, Guido Belfiore, Jan Plíva, Ronny Henker, Frank Ellinger	A 4×45 Gb/s Two-Tap FFE VCSEL Driver in 14-nm FinFET CMOS Suitable for Burst Mode Operation.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
14	Erkan Alpman, Ahmad Khairi, Richard Dorrance, Minyoung Park, V. Srinivasa Somayazulu, Jeffrey R. Foerster, Ashoke Ravi, Jeyanandh Paramesh, Stefano Pellerano	802.11g/n Compliant Fully Integrated Wake-Up Receiver With -72-dBm Sensitivity in 14-nm FinFET CMOS.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
14	Ewout Martens, Benjamin P. Hershberg, Jan Craninckx	A 69-dB SNDR 300-MS/s Two-Time Interleaved Pipelined SAR ADC in 16-nm CMOS FinFET With Capacitive Reference Stabilization.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
14	Jonathan E. Proesel, Zeynep Toprak Deniz, Alessandro Cevrero, Ilter Özkaya, Seongwon Kim, Daniel M. Kuchta, Sungjae Lee, Sergey V. Rylov, Herschel A. Ainspan, Timothy O. Dickson, John F. Bulzacchelli, Mounir Meghelli	A 32 Gb/s, 4.7 pJ/bit Optical Link With -11.7 dBm Sensitivity in 14-nm FinFET CMOS.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
14	Ioannis Intzes, Hongying Meng, John Paul Cosmas	High Data Rate FinFET On-Off Keying Transmitter for Wireless Capsule Endoscopy.	VLSI Design	2018	DBLP DOI BibTeX RDF
14	Kan Xu, Ravi Patel 0001, Praveen Raghavan, Eby G. Friedman	Exploratory design of on-chip power delivery for 14, 10, and 7 nm and beyond FinFET ICs.	Integr.	2018	DBLP DOI BibTeX RDF
14	Mitesh Limachia, Dixit Vyas, Rajesh Amratlal Thakker, Nikhil Kothari	Hybrid offset compensated latch-type sense amplifier for tri-gated FinFET technology.	Integr.	2018	DBLP DOI BibTeX RDF
14	Mitesh Limachia, Rajesh Amratlal Thakker, Nikhil Kothari	A near-threshold 10T differential SRAM cell with high read and write margins for tri-gated FinFET technology.	Integr.	2018	DBLP DOI BibTeX RDF
14	Hitesh Pahuja, Mintu Tyagi, Sudhakar Panday, Balwinder Singh	A novel single-ended 9T FinFET sub-threshold SRAM cell with high operating margins and low write power for low voltage operations.	Integr.	2018	DBLP DOI BibTeX RDF
14	Aili Wang 0002, Chuanjin Richard Shi	A 10-bit 50-MS/s SAR ADC with 1 fJ/Conversion in 14 nm SOI FinFET CMOS.	Integr.	2018	DBLP DOI BibTeX RDF