Search results for "flip-flops"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
30	Md. Ashfaquzzaman Khan, Naoto Miyamoto, Takeshi Ohkawa, Amir Jamak, Soichiro Kita, Koji Kotani, Tadahiro Ohmi	An approach to realize time-sharing of flip-flops in time-multiplexed FPGAs.	FPT	2004	DBLP DOI BibTeX RDF
30	Hamid Mahmoodi-Meimand, Kaushik Roy 0001	Data-retention flip-flops for power-down applications.	ISCAS (2)	2004	DBLP BibTeX RDF
30	Hamid Mahmoodi-Meimand, Kaushik Roy 0001	Dual-edge triggered level converting flip-flops.	ISCAS (2)	2004	DBLP BibTeX RDF
30	Peiyi Zhao, Pradeep Kumar Golconda, Magdy A. Bayoumi	Contention reduced/conditional discharge flip-flops for level conversion in CVS systems.	ISCAS (2)	2004	DBLP BibTeX RDF
30	Cecilia Metra, Stefano Di Francescantonio, Michele Favalli, Bruno Riccò	Scan flip-flops with on-line testing ability with respect to input delay and crosstalk faults.	Microelectron. J.	2003	DBLP DOI BibTeX RDF
30	Ali Iranli, Peyman Rezvani, Massoud Pedram	Low power synthesis of finite state machines with mixed D and T flip-flops.	ASP-DAC	2003	DBLP DOI BibTeX RDF
30	Peiyi Zhao, Tarek Darwish, Magdy A. Bayoumi	Low Power Conditional-Discharge Pulsed Flip-Flops.	Embedded Systems and Applications	2003	DBLP BibTeX RDF
30	Robert Bai, Dennis Sylvester	Analysis and design of level-converting flip-flops for dual-Vdd/Vth integrated circuits.	SoC	2003	DBLP DOI BibTeX RDF
30	Shang Xue, Bengt Oelmann	Comparative study of low-voltage performance of standard-cell flip-flops.	ICECS	2001	DBLP DOI BibTeX RDF
30	Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija	Conditional techniques for low power consumption flip-flops.	ICECS	2001	DBLP DOI BibTeX RDF
30	Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija	Timing Characterization of Dual-edge Triggered Flip-flops.	ICCD	2001	DBLP DOI BibTeX RDF
30	Ki-Hyuk Sung, Lee-Sup Kim	Comments on "New dynamic flip-flops for high-speed dual-modulus prescaler".	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
30	Jinn-Shyan Wang, Po-Hui Yang, Duo Sheng	Design of a 3-V 300-MHz low-power 8-b×8-b pipelined multiplier using pulse-triggered TSPC flip-flops.	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
30	Shin-ichi Yoshida, Yasufumi Takama, Kaoru Hirota	Fuzzy Flip-Flops and their Applications to Fuzzy Memory Element and Circuit Design using FPGA.	J. Adv. Comput. Intell. Intell. Informatics	2000	DBLP DOI BibTeX RDF
30	Yoichiro Sato, Yoshinobu Yamasoto, Masanori Saito, Hiroto Kagotani, Takuji Okamoto, Masahiro Kawai	Systematic reducing of metastable operations in CMOS D flip-flops.	Syst. Comput. Jpn.	2000	DBLP DOI BibTeX RDF
30	Tomasz Garbolino, Andrzej Hlawiczka, Adam Kristof	Fast and low-area TPGs based on T-type flip-flops can be easily integrated to the scan path.	ETW	2000	DBLP DOI BibTeX RDF
30	Po-Hui Yang, Jinn-Shyan Wang, Yi-Ming Wang	A 1-GHz low-power transposition memory using new pulse-clocked D flip-flops.	ISCAS	2000	DBLP DOI BibTeX RDF
30	Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara, Atsushi Murakami, Sadami Takeoka, Mitsuyasu Ohta	On validating data hold times for flip-flops in sequential circuits.	ITC	2000	DBLP DOI BibTeX RDF
30	Fabian Klass, Chaim Amir, Ashutosh Das, Kathirgamar Aingaran, Cindy Truong, Richard Wang, Anup Mehta, Raymond A. Heald, Gin Yee	A new family of semidynamic and dynamic flip-flops with embedded logic for high-performance processors.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
30	Vladimir Stojanovic, Vojin G. Oklobdzija	Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
30	Marie-Lise Flottes, Christian Landrault, A. Petitqueux	Partial set for flip-flops based on state requirement for non-scan BIST scheme.	ETW	1999	DBLP DOI BibTeX RDF
30	Antonio G. M. Strollo, Carlo Cimino, Ettore Napoli	Power dissipation in one-latch and two-latch double edge triggered flip-flops.	ICECS	1999	DBLP DOI BibTeX RDF
30	Ching-Yuan Yang, Guang-Kaai Dehng, June-Ming Hsu, Shen-Iuan Liu	New dynamic flip-flops for high-speed dual-modulus prescaler.	IEEE J. Solid State Circuits	1998	DBLP DOI BibTeX RDF
30	Leslaw Gniewek, Jacek Kluska	Family of fuzzy J-K flip-flops based on bounded product, bounded sum and complementation.	IEEE Trans. Syst. Man Cybern. Part B	1998	DBLP DOI BibTeX RDF
30	Massoud Pedram, Qing Wu 0002, Xunwei Wu	A New Design for Double Edge Triggered Flip-flops.	ASP-DAC	1998	DBLP BibTeX RDF
30	Vladimir Stojanovic, Vojin G. Oklobdzija, Raminder Singh Bajwa	Comparative analysis of latches and flip-flops for high-performance systems.	ICCD	1998	DBLP DOI BibTeX RDF
30	Hsing-Chung Liang, Chung-Len Lee 0001, Jwu E. Chen	Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation.	VTS	1998	DBLP DOI BibTeX RDF
30	Samy Makar	A layout-based approach for ordering scan chain flip-flops.	ITC	1998	DBLP DOI BibTeX RDF
30	Gerard M. Blair	Comments on "New single-clock CMOS latches and flip-flops with improved speed and power savings".	IEEE J. Solid State Circuits	1997	DBLP DOI BibTeX RDF
30	Robert Rogenmoser, Qiuting Huang	An 800-MHz 1-μm CMOS pipelined 8-b adder using true single-phase clocked logic-flip-flops.	IEEE J. Solid State Circuits	1996	DBLP DOI BibTeX RDF
30	Byungsoo Chang, Joonbae Park, Wonchan Kim	A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops.	IEEE J. Solid State Circuits	1996	DBLP DOI BibTeX RDF
30	Samiha Mourad	Digital design with minimal number of scan flip-flops.	ICECS	1996	DBLP DOI BibTeX RDF
30	Youn-Long Lin, Tsung-Yi Wu	Storage optimization by replacing some flip-flops with latches.	EURO-DAC	1996	DBLP DOI BibTeX RDF
30	Rafael Llopis, Manoj Sachdev	Low power, testable dual edge triggered flip-flops.	ISLPED	1996	DBLP DOI BibTeX RDF
30	Kiyoshi Ishii, Haruhiko Ichino, Minoru Togashi, Yoshiji Kobayashi, Chikara Yamaguchi	Very-high-speed Si bipolar static frequency dividers with new T-type flip-flops.	IEEE J. Solid State Circuits	1995	DBLP DOI BibTeX RDF
30	Kaoru Hirota, Witold Pedrycz	Design of fuzzy systems with fuzzy flip-flops.	IEEE Trans. Syst. Man Cybern.	1995	DBLP DOI BibTeX RDF
30	Albrecht P. Stroele, Hans-Joachim Wunderlich	Configuring Flip-Flops to BIST Registers.	ITC	1994	DBLP DOI BibTeX RDF
30	Srimat T. Chakradhar, Arun Balakrishnan, Vishwani D. Agrawal	An Exact Algorithm for Selecting Partial Scan Flip-Flops.	DAC	1994	DBLP DOI BibTeX RDF
30	Gerd Rietsche	State assignment for finite state machines using T flip-flops.	EURO-DAC	1993	DBLP DOI BibTeX RDF
30	Qiuting Huang	Speed Optimization of Edge-Triggered Nine-Transistor D-Flip-Flops for Gigahertz Single-Phase Clocks.	ISCAS	1993	DBLP BibTeX RDF
30	Miron Abramovici, Prashant S. Parikh, Ben Mathew, Daniel G. Saab	On Selecting Flip-Flops for Partial Reset.	ITC	1993	DBLP DOI BibTeX RDF
30	Doowon Paik, Sudhakar M. Reddy, Sartaj Sahni	Heuristics for the Placement of Flip-Flops in Partial Scan Designs and the Placement of Signal Boosters in Lossy Circuits.	VLSI Design	1993	DBLP DOI BibTeX RDF
30	Miron Abramovici, James J. Kulikowski, Rabindra K. Roy	The Best Flip-Flops to Scan.	ITC	1991	DBLP DOI BibTeX RDF
30	Dong-Ho Lee, Sudhakar M. Reddy	On Determining Scan Flip-Flops in Partial-Scan Designs.	ICCAD	1990	DBLP DOI BibTeX RDF
30	Sudhakar M. Reddy, Ramaswami Dandapani	Scan Design Using Standard Flip-Flops.	IEEE Des. Test	1987	DBLP DOI BibTeX RDF
30	Madhukar K. Reddy, Sudhakar M. Reddy	Detecting FET Stuck-Open Faults in CMOS Latches and Flip-Flops.	IEEE Des. Test	1986	DBLP DOI BibTeX RDF
30	Dilip K. Bhavsar	A New Economical Implementation for Scannable Flip-Flops in MOS.	IEEE Des. Test	1986	DBLP DOI BibTeX RDF
30	G. Lacroix, Philippe Marchegay, G. Piel	Comments on "The Anomalous Behavior of Flip-Flops in Synchronizer Circuits".	IEEE Trans. Computers	1982	DBLP DOI BibTeX RDF	uncertainty interval, Anomalous response of flip-flop, flip-flop metastable state, asynchronous interactions, synchronizer failures
30	Frank Rubin	Decrypting a Stream Cipher Based on j-k Flip-Flops.	Cryptologia	1981	DBLP DOI BibTeX RDF
30	Stephen H. Unger	Double-Edge-Triggered Flip-Flops.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF
30	Werner Fleischhammer, Osman Dörtok	The Anomalous Behavior of Flip-Flops in Synchronizer Circuits.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF
30	Thurman A. Irving Jr., Sajjan G. Shiva, H. Troy Nagle Jr.	Flip-Flops for Multiple-Valued Logic.	IEEE Trans. Computers	1976	DBLP DOI BibTeX RDF
30	Frank B. Manning, Robert Fenichel	Synchronous Counters Constructed Entirely of J-K Flip-Flops.	IEEE Trans. Computers	1976	DBLP DOI BibTeX RDF
30	Vera Pless	Mathematical Foundations of Interconnected J-K Flip-Flops	Inf. Control.	1976	DBLP DOI BibTeX RDF
30	Jon G. Bredeson	Comments on "Synthesis of Multiple-Input Change Asynchronous Machines Using Controlled Excitation and Flip-Flops".	IEEE Trans. Computers	1975	DBLP DOI BibTeX RDF	Asynchronous machine, controlled excitation, edge sensitive flip-flop, multiple-input changes, sequential circuit, self-synchronization
30	Yoshihiro Tohma	Design Technique of Fail-Safe Sequential Circuits Using Flip-Flops For Internal Memory.	IEEE Trans. Computers	1974	DBLP DOI BibTeX RDF
30	G. L. Tumbush, James E. Brandeberry	A State Assignment Technique for Sequential Machines Using J-K Flip-Flops.	IEEE Trans. Computers	1974	DBLP DOI BibTeX RDF
30	Henry Y. H. Chuang, Santanu Das	Synthesis of Multiple-Input Change Asynchronous Machines Using Controlled Excitation and Flip-Flops.	IEEE Trans. Computers	1973	DBLP DOI BibTeX RDF
30	Jon G. Bredeson, Paul T. Hulina	Synthesis of Multiple-Input Change Asynchronous Circuits Using Transition-Sensitive Flip-Flops.	IEEE Trans. Computers	1973	DBLP DOI BibTeX RDF
30	Henry Y. H. Chuang, Santanu Das	Multiple-Input Change Asynchronous Machines Using Controlled Excitation and Flip-Flops	SWAT	1973	DBLP DOI BibTeX RDF
30	Janusz A. Brzozowski	About Feedback and SR Flip-Flops.	IEEE Trans. Computers	1971	DBLP DOI BibTeX RDF
30	John R. Smith Jr., Charles H. Roth Jr.	Analysis and Synthesis of Asynchronous Sequential Networks Using Edge-Sensitive Flip-Flops.	IEEE Trans. Computers	1971	DBLP DOI BibTeX RDF
30	James T. Cain, Marlin H. Mickle, Lawrence P. McNamee	Compiler level simulation of edge sensitive flip-flops.	AFIPS Spring Joint Computing Conference	1967	DBLP DOI BibTeX RDF
30	Edwin S. Lee	Associative techniques with complementing flip-flops.	AFIPS Spring Joint Computing Conference	1963	DBLP DOI BibTeX RDF
30	Vasil Uzunoglu	Circuits Using Tunnel Diode Flip-Flops and PNPN Diodes.	IRE Trans. Electron. Comput.	1962	DBLP DOI BibTeX RDF
30	Z. Bay, N. T. Grisamore	High-Speed Flip-Flops for the Millimicrosecond Region.	IRE Trans. Electron. Comput.	1956	DBLP DOI BibTeX RDF
30	John O. Paivinen, Isaac L. Auerbach	Design of triode flip-flops for long-term stability.	Trans. I R E Prof. Group Electron. Comput.	1953	DBLP DOI BibTeX RDF
27	Rajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell	Zero Cost Test Point Insertion Technique for Structured ASICs.	VLSI Design	2007	DBLP DOI BibTeX RDF
27	Arun Balakrishnan, Srimat T. Chakradhar	Sequential Circuits with combinational Test Generation Complexity.	VLSI Design	1996	DBLP DOI BibTeX RDF
25	Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Ali Peiravi, Snorre Aunet, Tuan Vu Cao	New subthreshold concepts in 65nm CMOS technology.	ISQED	2009	DBLP DOI BibTeX RDF
25	Stephan Henzler, Siegmar Koeppe	Design and Application of Power Optimized High-Speed CMOS Frequency Dividers.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
25	Chao-Wen Tzeng, Jheng-Syun Yang, Shi-Yu Huang	A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	profiling, design for testability, Diagnosis, fault, scan chain
25	Simone Medardoni, Marcello Lajolo, Davide Bertozzi	Variation tolerant NoC design by means of self-calibrating links.	DATE	2008	DBLP DOI BibTeX RDF
25	Hyein Lee 0003, Seungwhun Paik, Youngsoo Shin	Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits.	ICCAD	2008	DBLP DOI BibTeX RDF
25	Jia Wang 0003, Hai Zhou 0001	An efficient incremental algorithm for min-area retiming.	DAC	2008	DBLP DOI BibTeX RDF	retiming
25	Peiyi Zhao, Jason McNeely, Pradeep Golconda, Magdy A. Bayoumi, Robert A. Barcenas, Weidong Kuang	Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
25	Gustavo Neuberger, Fernanda Gusmão de Lima Kastensmidt, Ricardo Reis 0001, Gilson I. Wirth, Ralf Brederlow, Christian Pacha	Statistical analysis of systematic and random variability of flip-flop race immunity in 130nm and 90nm CMOS technologies.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
25	Subhasish Mitra	Circuit Failure Prediction Enables Robust System Design Resilient to Aging and Wearout.	IOLTS	2007	DBLP DOI BibTeX RDF
25	Praveen Elakkumanan, Kishan Prasad, Ramalingam Sridhar	Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic.	ISQED	2006	DBLP DOI BibTeX RDF
25	Peiyi Zhao, Pradeep Kumar Golconda, C. Archana, Magdy A. Bayoumi	A Double-Edge Implicit-Pulsed Level Convert Flip-Flop.	ISVLSI	2004	DBLP DOI BibTeX RDF
25	Lucanus J. Simonson, King Ho Tam, Nataraj Akkiraju, Mosur Mohan, Lei He 0001	Leveraging Delay Slack in Flip-Flop and Buffer Insertion for Power Reduction.	ISQED	2004	DBLP DOI BibTeX RDF
25	Timothy Wheeler, Paul S. Graham, Brent E. Nelson, Brad L. Hutchings	Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification.	FPL	2001	DBLP DOI BibTeX RDF
25	Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng	On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set.	VTS	2000	DBLP DOI BibTeX RDF	Microprocessor self-testing, Path delay fault classification, Functionally testable paths, Functional tests, Delay fault testing
25	Wenyi Feng, Fred J. Meyer, Wei-Kang Huang, Fabrizio Lombardi	On the Complexity of Sequential Testing in Configurable FPGAs.	DFT	1998	DBLP DOI BibTeX RDF	FPGA, pipeline, PLD, sequential testing, iterative array
17	Husain Parvez, Zied Marrakchi, Habib Mehrez	Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	asif, fpga, architecture, application specific, cad
17	Nagaraj Ns, Juan C. Rey, Jamil Kawa, Robert C. Aitken, Christian Lütkemeyer, Vijay Pitchumani, Andrzej J. Strojwas, Steve Trimberger	Who solves the variability problem?	DAC	2010	DBLP DOI BibTeX RDF	IC variability
17	Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang	Pulsed-latch aware placement for timing-integrity optimization.	DAC	2010	DBLP DOI BibTeX RDF	pulsed latch, placement, physical design
17	Youngsoo Shin, Seungwhun Paik, Hyung-Ock Kim	Semicustom Design of Zigzag Power-Gated Circuits in Standard Cell Elements.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
17	Xiaoxia Wu, Paul Falkenstern, Krishnendu Chakrabarty, Yuan Xie 0001	Scan-chain design and optimization for three-dimensional integrated circuits.	ACM J. Emerg. Technol. Comput. Syst.	2009	DBLP DOI BibTeX RDF	scan-chain design, genetic algorithm, integer linear programming, randomized rounding, LP relaxation, 3D ICs
17	Tomasz Rudnicki, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka	Effective BIST for crosstalk faults in interconnects.	DDECS	2009	DBLP DOI BibTeX RDF
17	Qiang Wang, Subodh Gupta, Jason Helge Anderson	Clock power reduction for virtex-5 FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	optimization, field-programmable gate arrays, fpgas, low-power design, power, clocking
17	Jia Wang 0003, Hai Zhou 0001	Risk aversion min-period retiming under process variations.	ASP-DAC	2009	DBLP DOI BibTeX RDF
17	Bernd Finkbeiner, Lars Kuhtz	Monitor Circuits for LTL with Bounded and Unbounded Future.	RV	2009	DBLP DOI BibTeX RDF
17	Mahta Haghi, Jeff Draper	The effect of design parameters on single-event upset sensitivity of MOS current mode logic.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	mos current mode logic (mcml), single event upset (seu), design parameters, radiation hardening
17	Abhranil Maiti, Raghunandan Nagesh, Anand Reddy, Patrick Schaumont	Physical unclonable function and true random number generator: a compact and scalable implementation.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	ring oscillators (ro), trng, fpga, scalable, jitter, macro, puf
17	Satish Sivaswamy, Kia Bazargan	Statistical Analysis and Process Variation-Aware Routing and Skew Assignment for FPGAs.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	skew assignment, routing, Statistical timing analysis
17	Ho Fai Ko, Nicola Nicolici	Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
17	Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi	A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
17	Dong Xiang, Mingjing Chen, Jia-Guang Sun	Scan BIST with biased scan test signals.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	random testability, test signal, biased random testing, scan-based BIST
17	Saeed Sharifi Tehrani, Shie Mannor, Warren J. Gross	Fully Parallel Stochastic LDPC Decoders.	IEEE Trans. Signal Process.	2008	DBLP DOI BibTeX RDF