Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
30 | Md. Ashfaquzzaman Khan, Naoto Miyamoto, Takeshi Ohkawa, Amir Jamak, Soichiro Kita, Koji Kotani, Tadahiro Ohmi |
An approach to realize time-sharing of flip-flops in time-multiplexed FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, Brisbane, Australia, December 6-8, 2004, pp. 351-354, 2004, IEEE. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
30 | Hamid Mahmoodi-Meimand, Kaushik Roy 0001 |
Data-retention flip-flops for power-down applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 677-680, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
30 | Hamid Mahmoodi-Meimand, Kaushik Roy 0001 |
Dual-edge triggered level converting flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 661-664, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
30 | Peiyi Zhao, Pradeep Kumar Golconda, Magdy A. Bayoumi |
Contention reduced/conditional discharge flip-flops for level conversion in CVS systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2004 International Symposium on Circuits and Systems, ISCAS 2004, Vancouver, BC, Canada, May 23-26, 2004, pp. 669-672, 2004, IEEE, 0-7803-8251-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
30 | Cecilia Metra, Stefano Di Francescantonio, Michele Favalli, Bruno Riccò |
Scan flip-flops with on-line testing ability with respect to input delay and crosstalk faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 34(1), pp. 23-29, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
30 | Ali Iranli, Peyman Rezvani, Massoud Pedram |
Low power synthesis of finite state machines with mixed D and T flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2003 Asia and South Pacific Design Automation Conference, ASP-DAC '03, Kitakyushu, Japan, January 21-24, 2003, pp. 803-808, 2003, ACM, 0-7803-7660-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
30 | Peiyi Zhao, Tarek Darwish, Magdy A. Bayoumi |
Low Power Conditional-Discharge Pulsed Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Embedded Systems and Applications ![In: Proceedings of the International Conference on Embedded Systems and Applications, ESA '03, June 23 - 26, 2003, Las Vegas, Nevada, USA, pp. 204-209, 2003, CSREA Press. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
|
30 | Robert Bai, Dennis Sylvester |
Analysis and design of level-converting flip-flops for dual-Vdd/Vth integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoC ![In: Proceedings of the 2003 International Symposium on System-on-Chip, Tampere, Finland, November 19-21, 2003, pp. 151-154, 2003, IEEE, 0-7803-8160-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
30 | Shang Xue, Bengt Oelmann |
Comparative study of low-voltage performance of standard-cell flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2001 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001, Malta, September 2-5, 2001, pp. 953-957, 2001, IEEE, 0-7803-7057-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
30 | Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija |
Conditional techniques for low power consumption flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of the 2001 8th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2001, Malta, September 2-5, 2001, pp. 803-806, 2001, IEEE, 0-7803-7057-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
30 | Nikola Nedovic, Marko Aleksic, Vojin G. Oklobdzija |
Timing Characterization of Dual-edge Triggered Flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 19th International Conference on Computer Design (ICCD 2001), VLSI in Computers and Processors, 23-26 September 2001, Austin, TX, USA, Proceedings, pp. 538-541, 2001, IEEE Computer Society, 0-7695-1200-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
30 | Ki-Hyuk Sung, Lee-Sup Kim |
Comments on "New dynamic flip-flops for high-speed dual-modulus prescaler". ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 35(6), pp. 919-920, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
30 | Jinn-Shyan Wang, Po-Hui Yang, Duo Sheng |
Design of a 3-V 300-MHz low-power 8-b×8-b pipelined multiplier using pulse-triggered TSPC flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 35(4), pp. 583-592, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
30 | Shin-ichi Yoshida, Yasufumi Takama, Kaoru Hirota |
Fuzzy Flip-Flops and their Applications to Fuzzy Memory Element and Circuit Design using FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Adv. Comput. Intell. Intell. Informatics ![In: J. Adv. Comput. Intell. Intell. Informatics 4(5), pp. 380-386, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
30 | Yoichiro Sato, Yoshinobu Yamasoto, Masanori Saito, Hiroto Kagotani, Takuji Okamoto, Masahiro Kawai |
Systematic reducing of metastable operations in CMOS D flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Syst. Comput. Jpn. ![In: Syst. Comput. Jpn. 31(3), pp. 20-28, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
30 | Tomasz Garbolino, Andrzej Hlawiczka, Adam Kristof |
Fast and low-area TPGs based on T-type flip-flops can be easily integrated to the scan path. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETW ![In: 5th European Test Workshop, ETW 2000, Cascais, Portugal, May 23-26, 2000, pp. 161-166, 2000, IEEE Computer Society, 0-7695-0701-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
30 | Po-Hui Yang, Jinn-Shyan Wang, Yi-Ming Wang |
A 1-GHz low-power transposition memory using new pulse-clocked D flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2000, Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31 May 2000, Proceedings, pp. 665-668, 2000, IEEE. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
30 | Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara, Atsushi Murakami, Sadami Takeoka, Mitsuyasu Ohta |
On validating data hold times for flip-flops in sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2000, Atlantic City, NJ, USA, October 2000, pp. 317-325, 2000, IEEE Computer Society, 0-7803-6546-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
30 | Fabian Klass, Chaim Amir, Ashutosh Das, Kathirgamar Aingaran, Cindy Truong, Richard Wang, Anup Mehta, Raymond A. Heald, Gin Yee |
A new family of semidynamic and dynamic flip-flops with embedded logic for high-performance processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 34(5), pp. 712-716, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
30 | Vladimir Stojanovic, Vojin G. Oklobdzija |
Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 34(4), pp. 536-548, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
30 | Marie-Lise Flottes, Christian Landrault, A. Petitqueux |
Partial set for flip-flops based on state requirement for non-scan BIST scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ETW ![In: 4th European Test Workshop, ETW 1999, Constance, Germany, May 25-28, 1999, pp. 104-109, 1999, IEEE Computer Society, 0-7695-0390-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
30 | Antonio G. M. Strollo, Carlo Cimino, Ettore Napoli |
Power dissipation in one-latch and two-latch double edge triggered flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 6th IEEE International Conference on Electronics, Circuits and Systems, ICECS 1999, Pafos, Cyprus, September 5-8, 1999, pp. 1419-1422, 1999, IEEE, 0-7803-5682-9. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
30 | Ching-Yuan Yang, Guang-Kaai Dehng, June-Ming Hsu, Shen-Iuan Liu |
New dynamic flip-flops for high-speed dual-modulus prescaler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 33(10), pp. 1568-1571, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
30 | Leslaw Gniewek, Jacek Kluska |
Family of fuzzy J-K flip-flops based on bounded product, bounded sum and complementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Syst. Man Cybern. Part B ![In: IEEE Trans. Syst. Man Cybern. Part B 28(6), pp. 861-868, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
30 | Massoud Pedram, Qing Wu 0002, Xunwei Wu |
A New Design for Double Edge Triggered Flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the ASP-DAC '98, Asia and South Pacific Design Automation Conference 1998, Pacifico Yokohama, Yokohama, Japan, February 10-13, 1998, pp. 417-421, 1998, IEEE, 0-7803-4425-1. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP BibTeX RDF |
|
30 | Vladimir Stojanovic, Vojin G. Oklobdzija, Raminder Singh Bajwa |
Comparative analysis of latches and flip-flops for high-performance systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: International Conference on Computer Design: VLSI in Computers and Processors, ICCD 1998, Proceedings, 5-7 October, 1998, Austin, TX, USA, pp. 264-269, 1998, IEEE Computer Society, 0-8186-9099-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
30 | Hsing-Chung Liang, Chung-Len Lee 0001, Jwu E. Chen |
Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 16th IEEE VLSI Test Symposium (VTS '98), 28 April - 1 May 1998, Princeton, NJ, USA, pp. 341-347, 1998, IEEE Computer Society, 0-8186-8436-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
30 | Samy Makar |
A layout-based approach for ordering scan chain flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 341-347, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
30 | Gerard M. Blair |
Comments on "New single-clock CMOS latches and flip-flops with improved speed and power savings". ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 32(10), pp. 1610-1611, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
30 | Robert Rogenmoser, Qiuting Huang |
An 800-MHz 1-μm CMOS pipelined 8-b adder using true single-phase clocked logic-flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 31(3), pp. 401-409, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
30 | Byungsoo Chang, Joonbae Park, Wonchan Kim |
A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 31(5), pp. 749-752, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
30 | Samiha Mourad |
Digital design with minimal number of scan flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: Proceedings of Third International Conference on Electronics, Circuits, and Systems, ICECS 1996, Rodos, Greece, October 13-16, 1996, pp. 931-934, 1996, IEEE, 0-7803-3650-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
30 | Youn-Long Lin, Tsung-Yi Wu |
Storage optimization by replacing some flip-flops with latches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings of the conference on European design automation, EURO-DAC '96/EURO-VHDL '96, Geneva, Switzerland, September 16-20, 1996, pp. 296-301, 1996, IEEE Computer Society Press, 0-8186-7573-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
30 | Rafael Llopis, Manoj Sachdev |
Low power, testable dual edge triggered flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996, Monterey, California, USA, August 12-14, 1996, pp. 341-345, 1996, IEEE, 0-7803-3571-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
30 | Kiyoshi Ishii, Haruhiko Ichino, Minoru Togashi, Yoshiji Kobayashi, Chikara Yamaguchi |
Very-high-speed Si bipolar static frequency dividers with new T-type flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 30(1), pp. 19-24, January 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
30 | Kaoru Hirota, Witold Pedrycz |
Design of fuzzy systems with fuzzy flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Syst. Man Cybern. ![In: IEEE Trans. Syst. Man Cybern. 25(1), pp. 169-176, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
30 | Albrecht P. Stroele, Hans-Joachim Wunderlich |
Configuring Flip-Flops to BIST Registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1994, TEST: The Next 25 Years, Washington, DC, USA, October 2-6, 1994, pp. 939-948, 1994, IEEE Computer Society, 0-7803-2103-0. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
30 | Srimat T. Chakradhar, Arun Balakrishnan, Vishwani D. Agrawal |
An Exact Algorithm for Selecting Partial Scan Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 31st Conference on Design Automation, San Diego, California, USA, June 6-10, 1994., pp. 81-86, 1994, ACM Press, 0-7803-1836-6. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
30 | Gerd Rietsche |
State assignment for finite state machines using T flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: Proceedings of the European Design Automation Conference 1993, EURO-DAC '93 with EURO-VHDL'93, Hamburg, Germany, September 20-24, 1993, pp. 396-401, 1993, IEEE Computer Society, 0-8186-4350-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
30 | Qiuting Huang |
Speed Optimization of Edge-Triggered Nine-Transistor D-Flip-Flops for Gigahertz Single-Phase Clocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: 1993 IEEE International Symposium on Circuits and Systems, ISCAS 1993, Chicago, Illinois, USA, May 3-6, 1993, pp. 2118-2121, 1993, IEEE, 0-7803-1281-3. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
30 | Miron Abramovici, Prashant S. Parikh, Ben Mathew, Daniel G. Saab |
On Selecting Flip-Flops for Partial Reset. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics - Join Them, Baltimore, Maryland, USA, October 17-21, 1993, pp. 1008-1012, 1993, IEEE Computer Society, 0-7803-1430-1. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
30 | Doowon Paik, Sudhakar M. Reddy, Sartaj Sahni |
Heuristics for the Placement of Flip-Flops in Partial Scan Designs and the Placement of Signal Boosters in Lossy Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: Proceedings of the Sixth International Conference on VLSI Design, VLSI Design 1993, Bombay, India, January 3-6, 1993, pp. 45-50, 1993, IEEE Computer Society, 0-8186-3180-5. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
30 | Miron Abramovici, James J. Kulikowski, Rabindra K. Roy |
The Best Flip-Flops to Scan. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1991, Test: Faster, Better, Sooner, Nashville, TN, USA, October 26-30, 1991, pp. 166-173, 1991, IEEE Computer Society, 0-8186-9156-5. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
30 | Dong-Ho Lee, Sudhakar M. Reddy |
On Determining Scan Flip-Flops in Partial-Scan Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1990, Santa Clara, CA, USA, November 11-15, 1990. Digest of Technical Papers, pp. 322-325, 1990, IEEE Computer Society, 0-8186-2055-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
30 | Sudhakar M. Reddy, Ramaswami Dandapani |
Scan Design Using Standard Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test ![In: IEEE Des. Test 4(1), pp. 52-54, 1987. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
30 | Madhukar K. Reddy, Sudhakar M. Reddy |
Detecting FET Stuck-Open Faults in CMOS Latches and Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test ![In: IEEE Des. Test 3(5), pp. 17-26, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
30 | Dilip K. Bhavsar |
A New Economical Implementation for Scannable Flip-Flops in MOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test ![In: IEEE Des. Test 3(3), pp. 52-56, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
30 | G. Lacroix, Philippe Marchegay, G. Piel |
Comments on "The Anomalous Behavior of Flip-Flops in Synchronizer Circuits". ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 31(1), pp. 77-78, 1982. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
uncertainty interval, Anomalous response of flip-flop, flip-flop metastable state, asynchronous interactions, synchronizer failures |
30 | Frank Rubin |
Decrypting a Stream Cipher Based on j-k Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Cryptologia ![In: Cryptologia 5(1), pp. 51-57, 1981. The full citation details ...](Pics/full.jpeg) |
1981 |
DBLP DOI BibTeX RDF |
|
30 | Stephen H. Unger |
Double-Edge-Triggered Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 30(6), pp. 447-451, 1981. The full citation details ...](Pics/full.jpeg) |
1981 |
DBLP DOI BibTeX RDF |
|
30 | Werner Fleischhammer, Osman Dörtok |
The Anomalous Behavior of Flip-Flops in Synchronizer Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 28(3), pp. 273-276, 1979. The full citation details ...](Pics/full.jpeg) |
1979 |
DBLP DOI BibTeX RDF |
|
30 | Thurman A. Irving Jr., Sajjan G. Shiva, H. Troy Nagle Jr. |
Flip-Flops for Multiple-Valued Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 25(3), pp. 237-246, 1976. The full citation details ...](Pics/full.jpeg) |
1976 |
DBLP DOI BibTeX RDF |
|
30 | Frank B. Manning, Robert Fenichel |
Synchronous Counters Constructed Entirely of J-K Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 25(3), pp. 300-306, 1976. The full citation details ...](Pics/full.jpeg) |
1976 |
DBLP DOI BibTeX RDF |
|
30 | Vera Pless |
Mathematical Foundations of Interconnected J-K Flip-Flops ![Search on Bibsonomy](Pics/bibsonomy.png) |
Inf. Control. ![In: Inf. Control. 30(2), pp. 128-142, February 1976. The full citation details ...](Pics/full.jpeg) |
1976 |
DBLP DOI BibTeX RDF |
|
30 | Jon G. Bredeson |
Comments on "Synthesis of Multiple-Input Change Asynchronous Machines Using Controlled Excitation and Flip-Flops". ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 24(11), pp. 1142-1143, 1975. The full citation details ...](Pics/full.jpeg) |
1975 |
DBLP DOI BibTeX RDF |
Asynchronous machine, controlled excitation, edge sensitive flip-flop, multiple-input changes, sequential circuit, self-synchronization |
30 | Yoshihiro Tohma |
Design Technique of Fail-Safe Sequential Circuits Using Flip-Flops For Internal Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 23(11), pp. 1149-1154, 1974. The full citation details ...](Pics/full.jpeg) |
1974 |
DBLP DOI BibTeX RDF |
|
30 | G. L. Tumbush, James E. Brandeberry |
A State Assignment Technique for Sequential Machines Using J-K Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 23(1), pp. 85-86, 1974. The full citation details ...](Pics/full.jpeg) |
1974 |
DBLP DOI BibTeX RDF |
|
30 | Henry Y. H. Chuang, Santanu Das |
Synthesis of Multiple-Input Change Asynchronous Machines Using Controlled Excitation and Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 22(12), pp. 1103-1109, 1973. The full citation details ...](Pics/full.jpeg) |
1973 |
DBLP DOI BibTeX RDF |
|
30 | Jon G. Bredeson, Paul T. Hulina |
Synthesis of Multiple-Input Change Asynchronous Circuits Using Transition-Sensitive Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 22(5), pp. 524-531, 1973. The full citation details ...](Pics/full.jpeg) |
1973 |
DBLP DOI BibTeX RDF |
|
30 | Henry Y. H. Chuang, Santanu Das |
Multiple-Input Change Asynchronous Machines Using Controlled Excitation and Flip-Flops ![Search on Bibsonomy](Pics/bibsonomy.png) |
SWAT ![In: 14th Annual Symposium on Switching and Automata Theory, Iowa City, Iowa, USA, October 15-17, 1973, pp. 64-69, 1973, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1973 |
DBLP DOI BibTeX RDF |
|
30 | Janusz A. Brzozowski |
About Feedback and SR Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 20(4), pp. 476, 1971. The full citation details ...](Pics/full.jpeg) |
1971 |
DBLP DOI BibTeX RDF |
|
30 | John R. Smith Jr., Charles H. Roth Jr. |
Analysis and Synthesis of Asynchronous Sequential Networks Using Edge-Sensitive Flip-Flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 20(8), pp. 847-855, 1971. The full citation details ...](Pics/full.jpeg) |
1971 |
DBLP DOI BibTeX RDF |
|
30 | James T. Cain, Marlin H. Mickle, Lawrence P. McNamee |
Compiler level simulation of edge sensitive flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AFIPS Spring Joint Computing Conference ![In: American Federation of Information Processing Societies: Proceedings of the AFIPS '67 Spring Joint Computer Conference, April 18-20, 1967, Atlantic City, New Jersey, USA, pp. 757-759, 1967, AFIPS / ACM / Thomson Book Company, Washington D.C., 978-1-4503-7895-6. The full citation details ...](Pics/full.jpeg) |
1967 |
DBLP DOI BibTeX RDF |
|
30 | Edwin S. Lee |
Associative techniques with complementing flip-flops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AFIPS Spring Joint Computing Conference ![In: Proceedings of the 1963 spring joint computer conference, AFIPS 1963 (Spring), Detroit, Michigan, USA, May 21-23, 1963, pp. 381-394, 1963, ACM, 978-1-4503-7880-2. The full citation details ...](Pics/full.jpeg) |
1963 |
DBLP DOI BibTeX RDF |
|
30 | Vasil Uzunoglu |
Circuits Using Tunnel Diode Flip-Flops and PNPN Diodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRE Trans. Electron. Comput. ![In: IRE Trans. Electron. Comput. 11(6), pp. 793-796, 1962. The full citation details ...](Pics/full.jpeg) |
1962 |
DBLP DOI BibTeX RDF |
|
30 | Z. Bay, N. T. Grisamore |
High-Speed Flip-Flops for the Millimicrosecond Region. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRE Trans. Electron. Comput. ![In: IRE Trans. Electron. Comput. 5(3), pp. 121-125, 1956. The full citation details ...](Pics/full.jpeg) |
1956 |
DBLP DOI BibTeX RDF |
|
30 | John O. Paivinen, Isaac L. Auerbach |
Design of triode flip-flops for long-term stability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Trans. I R E Prof. Group Electron. Comput. ![In: Trans. I R E Prof. Group Electron. Comput. 2(2), pp. 14-26, 1953. The full citation details ...](Pics/full.jpeg) |
1953 |
DBLP DOI BibTeX RDF |
|
27 | Rajamani Sethuram, Seongmoon Wang, Srimat T. Chakradhar, Michael L. Bushnell |
Zero Cost Test Point Insertion Technique for Structured ASICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 20th International Conference on VLSI Design (VLSI Design 2007), Sixth International Conference on Embedded Systems (ICES 2007), 6-10 January 2007, Bangalore, India, pp. 357-363, 2007, IEEE Computer Society, 0-7695-2762-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Arun Balakrishnan, Srimat T. Chakradhar |
Sequential Circuits with combinational Test Generation Complexity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 111-117, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
25 | Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Ali Peiravi, Snorre Aunet, Tuan Vu Cao |
New subthreshold concepts in 65nm CMOS technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 162-166, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
25 | Stephan Henzler, Siegmar Koeppe |
Design and Application of Power Optimized High-Speed CMOS Frequency Dividers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(11), pp. 1513-1520, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Chao-Wen Tzeng, Jheng-Syun Yang, Shi-Yu Huang |
A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(1), pp. 9:1-9:27, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
profiling, design for testability, Diagnosis, fault, scan chain |
25 | Simone Medardoni, Marcello Lajolo, Davide Bertozzi |
Variation tolerant NoC design by means of self-calibrating links. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 1402-1407, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Hyein Lee 0003, Seungwhun Paik, Youngsoo Shin |
Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 224-229, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
25 | Jia Wang 0003, Hai Zhou 0001 |
An efficient incremental algorithm for min-area retiming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 528-533, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
retiming |
25 | Peiyi Zhao, Jason McNeely, Pradeep Golconda, Magdy A. Bayoumi, Robert A. Barcenas, Weidong Kuang |
Low-Power Clock Branch Sharing Double-Edge Triggered Flip-Flop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(3), pp. 338-345, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Gustavo Neuberger, Fernanda Gusmão de Lima Kastensmidt, Ricardo Reis 0001, Gilson I. Wirth, Ralf Brederlow, Christian Pacha |
Statistical analysis of systematic and random variability of flip-flop race immunity in 130nm and 90nm CMOS technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2007, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA, 15-17 October 2007, pp. 78-83, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Subhasish Mitra |
Circuit Failure Prediction Enables Robust System Design Resilient to Aging and Wearout. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, pp. 123, 2007, IEEE Computer Society, 0-7695-2918-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
25 | Praveen Elakkumanan, Kishan Prasad, Ramalingam Sridhar |
Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 617-624, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
25 | Peiyi Zhao, Pradeep Kumar Golconda, C. Archana, Magdy A. Bayoumi |
A Double-Edge Implicit-Pulsed Level Convert Flip-Flop. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), Emerging Trends in VLSI Systems Design, 19-20 February 2004, Lafayette, LA, USA, pp. 141-144, 2004, IEEE Computer Society, 0-7695-2097-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
25 | Lucanus J. Simonson, King Ho Tam, Nataraj Akkiraju, Mosur Mohan, Lei He 0001 |
Leveraging Delay Slack in Flip-Flop and Buffer Insertion for Power Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 5th International Symposium on Quality of Electronic Design (ISQED 2004), 22-24 March 2004, San Jose, CA, USA, pp. 69-74, 2004, IEEE Computer Society, 0-7695-2093-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
25 | Timothy Wheeler, Paul S. Graham, Brent E. Nelson, Brad L. Hutchings |
Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001, Proceedings, pp. 483-492, 2001, Springer, 3-540-42499-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
25 | Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng |
On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 15-22, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Microprocessor self-testing, Path delay fault classification, Functionally testable paths, Functional tests, Delay fault testing |
25 | Wenyi Feng, Fred J. Meyer, Wei-Kang Huang, Fabrizio Lombardi |
On the Complexity of Sequential Testing in Configurable FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 2-4 November 1998, Austin, TX, USA, Proceedings, pp. 164-, 1998, IEEE Computer Society, 0-8186-8832-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
FPGA, pipeline, PLD, sequential testing, iterative array |
17 | Husain Parvez, Zied Marrakchi, Habib Mehrez |
Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 290, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
asif, fpga, architecture, application specific, cad |
17 | Nagaraj Ns, Juan C. Rey, Jamil Kawa, Robert C. Aitken, Christian Lütkemeyer, Vijay Pitchumani, Andrzej J. Strojwas, Steve Trimberger |
Who solves the variability problem? ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 218-219, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
IC variability |
17 | Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang |
Pulsed-latch aware placement for timing-integrity optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 280-285, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
pulsed latch, placement, physical design |
17 | Youngsoo Shin, Seungwhun Paik, Hyung-Ock Kim |
Semicustom Design of Zigzag Power-Gated Circuits in Standard Cell Elements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(3), pp. 327-339, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Xiaoxia Wu, Paul Falkenstern, Krishnendu Chakrabarty, Yuan Xie 0001 |
Scan-chain design and optimization for three-dimensional integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 5(2), pp. 9:1-9:26, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
scan-chain design, genetic algorithm, integer linear programming, randomized rounding, LP relaxation, 3D ICs |
17 | Tomasz Rudnicki, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka |
Effective BIST for crosstalk faults in interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, April 15-17, 2009, Liberec, Czech Republic, pp. 164-169, 2009, IEEE Computer Society, 978-1-4244-3341-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Qiang Wang, Subodh Gupta, Jason Helge Anderson |
Clock power reduction for virtex-5 FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 13-22, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
optimization, field-programmable gate arrays, fpgas, low-power design, power, clocking |
17 | Jia Wang 0003, Hai Zhou 0001 |
Risk aversion min-period retiming under process variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 480-485, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Bernd Finkbeiner, Lars Kuhtz |
Monitor Circuits for LTL with Bounded and Unbounded Future. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RV ![In: Runtime Verification, 9th International Workshop, RV 2009, Grenoble, France, June 26-28, 2009. Selected Papers, pp. 60-75, 2009, Springer, 978-3-642-04693-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Mahta Haghi, Jeff Draper |
The effect of design parameters on single-event upset sensitivity of MOS current mode logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 233-238, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
mos current mode logic (mcml), single event upset (seu), design parameters, radiation hardening |
17 | Abhranil Maiti, Raghunandan Nagesh, Anand Reddy, Patrick Schaumont |
Physical unclonable function and true random number generator: a compact and scalable implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 425-428, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
ring oscillators (ro), trng, fpga, scalable, jitter, macro, puf |
17 | Satish Sivaswamy, Kia Bazargan |
Statistical Analysis and Process Variation-Aware Routing and Skew Assignment for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 1(1), pp. 4:1-4:35, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
skew assignment, routing, Statistical timing analysis |
17 | Ho Fai Ko, Nicola Nicolici |
Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(11), pp. 2092-2097, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi |
A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9), pp. 1535-1544, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Dong Xiang, Mingjing Chen, Jia-Guang Sun |
Scan BIST with biased scan test signals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sci. China Ser. F Inf. Sci. ![In: Sci. China Ser. F Inf. Sci. 51(7), pp. 881-895, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
random testability, test signal, biased random testing, scan-based BIST |
17 | Saeed Sharifi Tehrani, Shie Mannor, Warren J. Gross |
Fully Parallel Stochastic LDPC Decoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 56(11), pp. 5692-5703, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|