Search results for "instruction"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
25	Ido Roll, Vincent Aleven, Kenneth R. Koedinger	Promoting Effective Help-Seeking Behavior Through Declarative Instruction.	Intelligent Tutoring Systems	2004	DBLP DOI BibTeX RDF
25	Vikram S. Adve, Michael Brukman, Alkis Evlogimenos, Brian Gaeke	Software Implications of Virtual Instruction Set Computers.	IPDPS Next Generation Software Program - NSFNGS - PI Workshop	2004	DBLP DOI BibTeX RDF
25	Spiridon Nikolaidis 0001, Nikolaos Kavvadias, Theodore Laopoulos, Labros Bisdounis, Spyros Blionas	Instruction Level Energy Modeling for Pipelined Processors.	PATMOS	2003	DBLP DOI BibTeX RDF
25	G. Surendra, Subhasis Banerjee, S. K. Nandy 0001	Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation.	DATE	2003	DBLP DOI BibTeX RDF
25	Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan	Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors.	MICRO	2003	DBLP DOI BibTeX RDF
25	Erik Eckstein, Oliver König, Bernhard Scholz	Code Instruction Selection Based on SSA-Graphs.	SCOPES	2003	DBLP DOI BibTeX RDF
25	Bernard Goossens	The Instruction Register File.	PaCT	2003	DBLP DOI BibTeX RDF
25	José L. Ayala, Marisa Luisa López-Vallejo, Alexander V. Veidenbaum, Carlos A. Lopez	Energy Aware Register File Implementation through Instruction Predecode.	ASAP	2003	DBLP DOI BibTeX RDF
25	Alper Buyuktosunoglu, Tejas Karkhanis, David H. Albonesi, Pradip Bose	Energy Efficient Co-Adaptive Instruction Fetch and Issue.	ISCA	2003	DBLP DOI BibTeX RDF
25	Nathan T. Slingerland, Alan Jay Smith	Measuring the Performance of Multimedia Instruction Sets.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	VIS, MVI, multimedia, benchmarking, performance measurement, SIMD, subword parallel, MMX, SSE, AltiVec
25	Johann Großschädl	Instruction Set Extension for Long Integer Modulo Arithmetic on RISC-Based Smart Cards.	SBAC-PAD	2002	DBLP DOI BibTeX RDF
25	Marios Iliopoulos, Theodore Antonakopoulos 0001	Run-Time Optimized Reconfiguration Using Instruction Forecasting.	FPL	2001	DBLP DOI BibTeX RDF
25	Kenji Watanabe, Wanming Chu, Yamin Li	Exploiting Java Instruction/Thread Level Parallelism with Horizontal Multithreading.	ACSAC	2001	DBLP DOI BibTeX RDF
25	Heui Lee, Paul Becket, Bill Appelbe	High-Performance Extendable Instruction Set Computing.	ACSAC	2001	DBLP DOI BibTeX RDF
25	Michael S. Schlansker, B. Ramakrishna Rau	EPIC: Explicititly Parallel Instruction Computing.	Computer	2000	DBLP DOI BibTeX RDF
25	James E. Smith 0001	Instruction Level Distributed Processing.	HiPC	2000	DBLP DOI BibTeX RDF
25	James E. Smith 0001	Instruction Level Distributed Processing: Adapting to Future Technology.	ISHPC	2000	DBLP DOI BibTeX RDF
25	Austin Kim, J. Morris Chang	An Advanced Instruction Folding Mechanism for a Stackless Java Processor.	ICCD	2000	DBLP DOI BibTeX RDF
25	Yuan C. Chou, John Paul Shen	Instruction path coprocessors.	ISCA	2000	DBLP DOI BibTeX RDF
25	Artur Klauser, Dirk Grunwald	Instruction Fetch Mechanisms for Multipath Execution Processors.	MICRO	1999	DBLP DOI BibTeX RDF
25	G. Arcangeli, Jürgen Assfalg, R. Tartaglia, Enrico Vicario	A Virtual Environment for Construction Workers Instruction and Training.	ICMCS, Vol. 2	1999	DBLP DOI BibTeX RDF
25	Fred G. Gustavson, José E. Moreira, Robert F. Enenkel	The fused multiply-add instruction leads to algorithms for extended-precision floating point: applications to java and high-performance computing.	CASCON	1999	DBLP BibTeX RDF	Java
25	Walter Lee, Rajeev Barua, Matthew I. Frank, Devabhaktuni Srikrishna, Jonathan Babb, Vivek Sarkar, Saman P. Amarasinghe	Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine.	ASPLOS	1998	DBLP DOI BibTeX RDF
25	Shyh-An Chi, R.-Ming Shiu, Jih-Ching Chiu, Si-En Chang, Chung-Ping Chung	Instruction Cache Prefetching with Extended BTB.	ICPADS	1997	DBLP DOI BibTeX RDF
25	Sriram Vajapeyam, Tulika Mitra	Improving Superscalar Instruction Dispatch and Issue by Exploiting Dynamic Code Sequences.	ISCA	1997	DBLP DOI BibTeX RDF
25	Ali-Reza Adl-Tabatabai, Thomas R. Gross	Detection and Recovery of Endangered Variables Caused by Instruction Scheduling.	PLDI	1993	DBLP DOI BibTeX RDF
25	Chad L. Mitchell, Michael J. Flynn	The Effects of Processor Architecture on Instruction Memory Traffic.	ACM Trans. Comput. Syst.	1990	DBLP DOI BibTeX RDF
25	Mitsuhisa Sato, Shuichi Ichikawa, Eiichi Goto	Multiple instruction streams in a highly pipelined processor.	SPDP	1990	DBLP DOI BibTeX RDF
25	Jong-Jiann Shieh, Christos A. Papachristou	On reordering instruction streams for pipelined computers.	MICRO	1989	DBLP DOI BibTeX RDF
25	John M. Mellor-Crummey, Thomas J. LeBlanc	A Software Instruction Counter.	ASPLOS	1989	DBLP DOI BibTeX RDF
25	Rajeev Kumar 0004, Dipankar Das 0002	Code compression for performance enhancement of variable-length embedded processors.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	bus switching, code decompression, instruction memory, variable-length ISAs, embedded systems, Code compression, RISC processor
25	Jun Le	The Strategy and Practice of Blended Learning in Open and Distance Learning: Experiences from GDRTVU.	ICHL	2008	DBLP DOI BibTeX RDF	distance learning, instruction design, blended learning, online learning environment
25	Xianhua Liu 0001, Jiyu Zhang, Xu Cheng 0001	Efficient code size reduction without performance loss.	SAC	2007	DBLP DOI BibTeX RDF	dual-width instruction set, mixed code generation, embedded system, code size reduction
25	Deok Jin Kim, Tae-Hyung Kim, Jong Kim 0001, Sung Je Hong	Return Address Randomization Scheme for Annuling Data-Injection Buffer Overflow Attacks.	Inscrypt	2006	DBLP DOI BibTeX RDF	Return Address, return-into-libc Attack, Data Injection Buffer Overflow Attack, Security, Randomization, Buffer Overflow, Instruction Set
25	Kazuo Sakiyama, Lejla Batina, Bart Preneel, Ingrid Verbauwhede	Superscalar Coprocessor for High-Speed Curve-Based Cryptography.	CHES	2006	DBLP DOI BibTeX RDF	curve-based cryptography, HECC, ECC, instruction-level parallelism, scalar multiplication, Superscalar, coprocessor
25	Alex Ramírez, Josep Lluís Larriba-Pey, Mateo Valero	Software Trace Cache.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	compiler optimizations, branch prediction, Pipeline processors, trace cache, instruction fetch
25	Marc L. Corliss, E. Christopher Lewis, Amir Roth	The implementation and evaluation of dynamic code decompression using DISE.	ACM Trans. Embed. Comput. Syst.	2005	DBLP DOI BibTeX RDF	DISE, code decompression, dynamic instruction stream editing, Code compression, dynamic instrumentation
25	Pan Yu, Tulika Mitra	Satisfying real-time constraints with custom instructions.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	real-time systems, execution time, instruction-set extensions, worst-case, customizable processors
25	K. Ananda Vardhan, Y. N. Srikant	Transition aware scheduling: increasing continuous idle-periods in resource units.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	leakage energy consumption, instruction scheduling, transitions, functional units, idle periods
25	Tom Wulf	Constructivist approaches for teaching computer programming.	SIGITE Conference	2005	DBLP DOI BibTeX RDF	constructivist pedagogy, programming instruction, active learning, cognitive apprenticeships
25	Yongxiang Liu, Anahita Shayesteh, Gokhan Memik, Glenn Reinman	Scaling the issue window with look-ahead latency prediction.	ICS	2004	DBLP DOI BibTeX RDF	LHT, MNM, SILO, instruction sorting, CLP
25	Tilman Glökler, Andreas Hoffmann 0002, Heinrich Meyr	Methodical Low-Power ASIP Design Space Exploration.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	ICORE, low power, ASIP, application-specific instruction set processor, low energy, LISA
25	Chunho Lee, Johnson Kin, Miodrag Potkonjak, William H. Mangione-Smith	Exploring Hypermedia Processor Design Space.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	hypermedia processor, synthesis framework, instruction-level parallelism, workload characterization
25	Alex Ramírez, Josep Lluís Larriba-Pey, Mateo Valero	Trace Cache Redundancy: Red & Blue Traces.	HPCA	2000	DBLP DOI BibTeX RDF	trace cache, instruction fetch, code reordering
25	Zhijie Shi, Ruby B. Lee	Bit Permutation Instructions for Accelerating Software Cryptography.	ASAP	2000	DBLP DOI BibTeX RDF	bit-level instructions, security, cryptography, permutations, processor architecture, Instruction Set Architecture
25	Marco Antonio Dal Poz, Jose Edinson Aedo Cobo, Wilhelmus A. M. Van Noije, Marcelo Knörich Zuffo	A Simple RISC Microprocessor Core Designed for Digital Set-Top-Box Applications.	ASAP	2000	DBLP DOI BibTeX RDF	FPGA, VHDL, Reconfigurable Computing, Microprocessor, MPEG, RISC, Co-Design, Instruction Set, HDTV, Set-Top-Box, iDCT, cable TV
25	Toshinori Sato, Itsujiro Arita	Partial Resolution in Data Value Predictors.	ICPP	2000	DBLP DOI BibTeX RDF	partial resolution, tag bitwidth, instruction level parallelism, value prediction, data speculation
25	Lori Carter, Beth Simon, Brad Calder, Larry Carter, Jeanne Ferrante	Predicated Static Single Assignment.	IEEE PACT	1999	DBLP DOI BibTeX RDF	Predicated Compiler Analysis, Instruction Scheduling
25	Narayan Ranganathan, Manoj Franklin	An Empirical Study of Decentralized ILP Execution Models.	ASPLOS	1998	DBLP DOI BibTeX RDF	execution unit dependence, hardware window, instruction-level parallelism, data dependence, dynamic scheduling, speculative execution, control dependence, decentralization
24	Suriya Subramanian, Kathryn S. McKinley	HeDGE: Hybrid Dataflow Graph Execution in the Issue Logic.	HiPEAC	2009	DBLP DOI BibTeX RDF
24	Dimitris Saougkos, George Manis, Konstantinos Blekas, Apostolos V. Zarras	Revisiting Java Bytecode Compression for Embedded and Mobile Computing Environments.	IEEE Trans. Software Eng.	2007	DBLP DOI BibTeX RDF	compression (coding), Java
24	Nathan Clark, Amir Hormati, Sami Yehia, Scott A. Mahlke, Krisztián Flautner	Liquid SIMD: Abstracting SIMD Hardware using Lightweight Dynamic Mapping.	HPCA	2007	DBLP DOI BibTeX RDF
24	Michael Andrews, Jeremy Johnson	Performance Analysis of a Family of WHT Algorithms.	IPDPS	2007	DBLP DOI BibTeX RDF
24	Benjamin Carrión Schäfer, Yongho Lee, Taewhan Kim	Temperature-Aware Compilation for VLIWProcessors.	RTCSA	2007	DBLP DOI BibTeX RDF
24	Haitham Akkary, Ravi Rajwar, Srikanth T. Srinivasan	An analysis of a resource efficient checkpoint architecture.	ACM Trans. Archit. Code Optim.	2004	DBLP DOI BibTeX RDF	checkpoint architecture, high-performance computing, Computer architecture, scalable architecture
24	Ashok Halambi, Aviral Shrivastava, Partha Biswas, Nikil D. Dutt, Alexandru Nicolau	An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs.	DATE	2002	DBLP DOI BibTeX RDF
24	Nael B. Abu-Ghazaleh, Philip A. Wilsey	On the Structure of Concurrent Interpreters.	IPDPS	2002	DBLP DOI BibTeX RDF
24	Wieland Fischer, Jean-Pierre Seifert	Increasing the Bitlength of a Crypto-Coprocessor.	CHES	2002	DBLP DOI BibTeX RDF	Arithmetical coprocessor, Hardware/Software codesign, Modular multiplication, Hardware architecture
24	Byron Cook, John Launchbury, John Matthews, Richard B. Kieburtz	Formal Verification of Explicitly Parallel Microprocessors.	CHARME	1999	DBLP DOI BibTeX RDF
24	David Channon, David Koch	Performance Analysis of Re-configurable Partitioned TLBs.	HICSS (5)	1997	DBLP DOI BibTeX RDF	Computer Architecture, Memory Management, Partitioning Algorithm, Address Translation
24	Neff Walker, John B. Smelcer	A comparison of selection time from walking and pull-down menus.	CHI	1990	DBLP DOI BibTeX RDF
24	Jakob Nielsen	Designing for international use (panel).	CHI	1990	DBLP DOI BibTeX RDF
24	Mark R. Thistle, Burton J. Smith	A processor architecture for horizon.	SC	1988	DBLP DOI BibTeX RDF
24	Peter B. Kessler	Discovering machine-specific code improvements.	SIGPLAN Symposium on Compiler Construction	1986	DBLP DOI BibTeX RDF
24	Vishv M. Malhotra, Sanjeev Kumar	Automatic Retargetable Code Generation: A New Technique.	FSTTCS	1986	DBLP DOI BibTeX RDF
22	Miao Wang, Guiming Wu, Zhiying Wang 0003	Instruction Selection for Subword Level Parallelism Optimizations for Application Specific Instruction Processors.	ISPA	2007	DBLP DOI BibTeX RDF
22	Mrinal Bose, Elizabeth M. Rudnick, Magdy S. Abadir	Automatic Bias Generation Using Pipeline Instruction State Coverage for Biased Random Instruction Generation.	IOLTW	2001	DBLP DOI BibTeX RDF
22	Gene McDaniel	An Analysis of a Mesa Instruction Set Using Dynamic Instruction Frequencies.	ASPLOS	1982	DBLP DOI BibTeX RDF	MESA
22	Minming Li, Chun Jason Xue, Tiantian Liu 0001, Yingchao Zhao 0001	Analysis and approximation for bank selection instruction minimization on partitioned memory architecture.	LCTES	2010	DBLP DOI BibTeX RDF	bank selection instruction minimization, partitioned memory architecture
22	Beth Simon, Michael Kohanfars, Jeff Lee, Karen Tamayo, Quintin I. Cutts	Experience report: peer instruction in introductory computing.	SIGCSE	2010	DBLP DOI BibTeX RDF	classroom response, clickers, prs, active learning, cs1, peer instruction
22	Pieter Devolder, Bram Pynoo, Tony Voet, Luc Adang, Jan Vercruysse, Philippe Duyck	Optimizing Physicians' Instruction of PACS Through E-Learning: Cognitive Load Theory Applied.	J. Digit. Imaging	2009	DBLP DOI BibTeX RDF	Informatics training, PACS training, clinical image viewing, cognitive load theory, e-learning, computer-assisted instruction
22	Alastair Colin Murray, Richard Vincent Bennett, Björn Franke, Nigel P. Topham	Code transformation and instruction set extension.	ACM Trans. Embed. Comput. Syst.	2009	DBLP DOI BibTeX RDF	source-level transformations, compilers, design space exploration, ASIPs, instruction set extension, Customizable processors
22	Meng-Huan Wu, Cheng-Yang Fu, Peng-Chih Wang, Ren-Song Tsay	An effective synchronization approach for fast and accurate multi-core instruction-set simulation.	EMSOFT	2009	DBLP DOI BibTeX RDF	synchronization, multi-core, binary translation, instruction-set simulator
22	Theo Kluter, Philip Brisk, Paolo Ienne, Edoardo Charbon	Way Stealing: cache-assisted automatic instruction set extensions.	DAC	2009	DBLP DOI BibTeX RDF	automatic identification, way stealing, instruction set extensions, application-specific processors, memory coherence
22	Sherry Y. Chen, Xiaohui Liu 0001	An Integrated Approach for Modeling Learning Patterns of Students in Web-Based Instruction: A Cognitive Style Perspective.	ACM Trans. Comput. Hum. Interact.	2008	DBLP DOI BibTeX RDF	learning patterns, data mining, Cognitive style, Web-based instruction
22	Clément Ballabriga, Hugues Cassé, Pascal Sainrat	An improved approach for set-associative instruction cache partial analysis.	SAC	2008	DBLP DOI BibTeX RDF	WCET computation, partial cache analysis, partial static analysis, abstract interpretation, COTS, instruction cache
22	Natalie Linnell, Richard J. Anderson, Jane Prey	Cross-cultural issues in a tutored video instruction course.	SIGCSE	2008	DBLP DOI BibTeX RDF	international course offerings, tutored video instruction, tablet pc, classroom presenter
22	Matthias Krause 0002, Dominik Englert, Oliver Bringmann 0001, Wolfgang Rosenstiel	Combination of instruction set simulation and abstract RTOS model execution for fast and accurate target software evaluation.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	RTOS modeling, embedded systems, instruction set simulation
22	Fang Song 0003, Shuanghui Hao, Minghui Hao, Zhimin Yang	Research on Acceleration and Deceleration Control Algorithm of NC Instruction Interpretations with High-Order Smooth.	ICIRA (2)	2008	DBLP DOI BibTeX RDF	NC instruction, acc/dec control, high-order smooth, moving-average algorithm
22	Xinchun Cui, Haiqing Wang	An Online Special Terminology Interpreting System for Bilingual Instruction.	WBL	2008	DBLP DOI BibTeX RDF	special terminology interpreting system, bilingual instruction, Ajax
22	Shu Xiao 0001, Edmund Ming-Kit Lai	VLIW instruction scheduling for minimal power variation.	ACM Trans. Archit. Code Optim.	2007	DBLP DOI BibTeX RDF	power variation reduction, Instruction scheduling, VLIW processors
22	Mame Maria Mbaye, Normand Bélanger, Yvon Savaria, Samuel Pierre	A Novel Application-specific Instruction-set Processor Design Approach for Video Processing Acceleration.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	data grouping and reuse, optimization, parallelism, application-specific instruction-set processor, design exploration
22	Carsten Gremzow	Compiled low-level virtual instruction set simulation and profiling for code partitioning and ASIP-synthesis in hardware/software co-design.	SCSC	2007	DBLP BibTeX RDF	hardware/software co-synthesis, instruction set architecture simulation, quantitative dataflow analysis, profiling, coarse-grained parallelism, LLVM
22	Nathan Jachimiec, Fernando Martinez-Vallina, Jafar Saniie	CReconfigurable finite field instruction set architecture.	FPGA	2007	DBLP DOI BibTeX RDF	MicroBlaze, embedded development, fast simplex links, galois fields, instruction set extensions, partial reconfiguration, finite field arithmetic, Xilinx, FSL
22	Fu-Ching Yang, Ing-Jer Huang	An Embedded Low Power/Cost 16-Bit Data/Instruction Microprocessor Compatible with ARM7 Software Tools.	ASP-DAC	2007	DBLP DOI BibTeX RDF	16 bit, ARM7 software tools, THUMB instruction set microprocessor, short-precision computing
22	L. Amaya Becvar, James D. Hollan	Transparency and technology appropriation: social impacts of a video blogging system in dental hygiene clinical instruction.	GROUP	2007	DBLP DOI BibTeX RDF	clinical instruction, technology appropriation, video blogging, design, ethnography, social impacts, professional education
22	Richard J. Anderson, Ruth E. Anderson, Katie M. Davis, Natalie Linnell, Craig Prince, Valentin Razmov	Supporting active learning and example based instruction with classroom technology.	SIGCSE	2007	DBLP DOI BibTeX RDF	example based instruction, student submissions, technology in education, algorithms, active learning, pedagogy, collaborative learning, tablet PC, digital ink
22	Alexander A. Moldovyan, Nick A. Moldovyan, Peter A. Moldovyanu	Architecture Types of the Bit Permutation Instruction for General Purpose Processors.	IF&GIS	2007	DBLP DOI BibTeX RDF	fast software encryption, controlled bit permutation, new CPU instruction, Cryptography
22	I-Wei Wu, Shih-Chia Huang, Chung-Ping Chung, Jean Jyh-Jiun Shann	Instruction Set Extension Generation with Considering Physical Constraints.	HiPEAC	2007	DBLP DOI BibTeX RDF	Pipestage Timing Constraint, ASIP, Instruction set extension, Extensible Processors
22	Timothy Furtak, José Nelson Amaral, Robert Niewiadomski	Using SIMD registers and instructions to enable instruction-level parallelism in sorting algorithms.	SPAA	2007	DBLP DOI BibTeX RDF	sorting, instruction-level parallelism, SIMD, vectorization, sorting networks, quicksort
22	Chengmo Yang, Alex Orailoglu	Power-efficient instruction delivery through trace reuse.	PACT	2006	DBLP DOI BibTeX RDF	adaptive processor, low-power design, instruction delivery
22	Oliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero	Branch predictor guided instruction decoding.	PACT	2006	DBLP DOI BibTeX RDF	complexity-effective, instruction decoding, branch predictor
22	Wei Qin, Joseph D'Errico, Xinping Zhu	A multiprocessing approach to accelerate retargetable and portable dynamic-compiled instruction-set simulation.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	retargetable, instruction set simulator, compiled simulation
22	Matthew J. Bridges, Neil Vachharajani, Guilherme Ottoni, David I. August	Automatic instruction scheduler retargeting by reverse-engineering.	PLDI	2006	DBLP DOI BibTeX RDF	automatic retargeting, structural hazard, compilers, reverse-engineering, instruction scheduling
22	Jose Rizo-Morente, Miguel Casas-Sanchez, Chris J. Bleakley	Dynamic current modeling at the instruction level.	ISLPED	2006	DBLP DOI BibTeX RDF	current and power measurement in a processor, dynamic instruction-level current model
22	Vladimir Stojanovic, R. Iris Bahar, Jennifer Dworak, Richard Weiss 0001	A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors.	DAC	2006	DBLP DOI BibTeX RDF	instruction queue, reliability, error correcting codes
22	Robert L. Bocchino Jr., Vikram S. Adve	Vector LLVA: a virtual vector instruction set for media processing.	VEE	2006	DBLP DOI BibTeX RDF	virtual instruction sets, multimedia, SIMD, vector
22	Elena Gabriela Barrantes, David H. Ackley, Stephanie Forrest, Darko Stefanovic	Randomized instruction set emulation.	ACM Trans. Inf. Syst. Secur.	2005	DBLP DOI BibTeX RDF	Automated diversity, randomized instruction sets, software diversity
22	Adrián Cristal, Oliverio J. Santana, Francisco J. Cazorla, Marco Galluzzi, Tanausú Ramírez, Miquel Pericàs, Mateo Valero	Kilo-Instruction Processors: Overcoming the Memory Wall.	IEEE Micro	2005	DBLP DOI BibTeX RDF	in-flight instructions, ROB, superscalar processors, memory wall, issue queue, Kilo-instruction processors
22	Sid Ahmed Ali Touati	Register Saturation in Instruction Level Parallelism.	Int. J. Parallel Program.	2005	DBLP DOI BibTeX RDF	Register requirement, instruction level parallelism, integer linear programming, optimizing compilation, register pressure