Search results for "processor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
18	Abhishek A. Sinkar, Nam Sung Kim	Analyzing potential power reduction with adaptive voltage positioning optimized for multicore processors.	ISLPED	2009	DBLP DOI BibTeX RDF	adaptive voltage positioning, multicore processor
18	Kunal Agrawal, Charles E. Leiserson, Yuxiong He, Wen-Jing Hsu	Adaptive work-stealing with parallelism feedback.	ACM Trans. Comput. Syst.	2008	DBLP DOI BibTeX RDF	instantaneous parallelism, parallelism feedback, trim analysis, parallel computation, randomized algorithm, job scheduling, multiprogramming, processor allocation, multiprocessing, work-stealing, Adaptive scheduling, work, thread scheduling, adversary, span, space sharing, two-level scheduling
18	Amin Asghari, Seied Ahmad Motamedi, Sepehr Attarchi	Effective RTL Method to Develop On-Line Self-Test Routine for the Processors Using the Wavelet Transform.	ACIS-ICIS	2008	DBLP DOI BibTeX RDF	On-line low-cost testing, Spectral test pattern generating, Software-based self-testing (SBST), Register transfer level (RTL), Processor testing
18	Peng Zhou, Soner Önder	Improving single-thread performance with fine-grain state maintenance.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	processor state, runahead, simultaneous multi-threading, checkpoint, recovery
18	Weiwu Hu, Ji-Ye Zhao, Shi-Qiang Zhong, Xu Yang, Elio Guidetti, Chris Wu	Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	superscalar pipeline, non-blocking cache, synthesis flow, bit-sliced placement, crafted cell, performance evaluation, physical design, out-of-order execution, general-purpose processor
18	Shih-Lien Lu, Peter Yiannacouras, Rolf Kassa, Michael Konow, Taeweon Suh	An FPGA-based Pentium in a complete desktop system.	FPGA	2007	DBLP DOI BibTeX RDF	pentium®, FPGA, emulator, accelerator, processor
18	Sandro Neves Soares, Flávio Rech Wagner	From classroom to research: providing different services for computer architecture education.	WCAE	2007	DBLP DOI BibTeX RDF	computer architecture education, processor modeling and simulation
18	Shuenn-Yuh Lee, Chia-Chyang Chen	VLSI implementation of programmable FFT architectures for OFDM communication system.	IWCMC	2006	DBLP DOI BibTeX RDF	FFT processor, low power, VLSI architecture
18	Kunal Agrawal, Yuxiong He, Wen-Jing Hsu, Charles E. Leiserson	Adaptive scheduling with parallelism feedback.	PPoPP	2006	DBLP DOI BibTeX RDF	greedy scheduling, instantaneous parallelism, parallelism feedback, trim analysis, parallel computation, task scheduling, job scheduling, multiprogramming, processor allocation, multiprocessing, critical path, adaptive scheduling, work, adversary, space sharing, data-parallel computing, two-level scheduling
18	Mihalis Psarakis, Dimitris Gizopoulos, Miltiadis Hatzimihail, Antonis M. Paschalis, Anand Raghunathan, Srivaths Ravi 0001	Systematic software-based self-test for pipelined processors.	DAC	2006	DBLP DOI BibTeX RDF	functional testing, software-based self-test, processor testing
18	Ruby B. Lee, A. Murat Fiskiran	PLX: An Instruction Set Architecture and Testbed for Multimedia Information Processing.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	multimedia, processor architecture, instruction set architecture, media processing, ISA
18	Slo-Li Chu	POERS: A Performance-Oriented Energy Reduction Scheduling Technique for a High-Performance MPSoC Architecture.	ICPADS (2)	2005	DBLP DOI BibTeX RDF	POERS, SAGE II, MPSoC, Processor-in-Memory, Energy Reduction
18	Slo-Li Chu	An Energy Reduction Scheduling Mechanism for a High-Performance SoC Architecture.	EUC	2005	DBLP DOI BibTeX RDF	EOPRS, SAGE II, SoC, Power Reduction, Processor-in-Memory
18	Julita Corbalán, Xavier Martorell, Jesús Labarta	Page Migration with Dynamic Space-Sharing Scheduling Policies: The Case of the SGI O2000.	Int. J. Parallel Program.	2004	DBLP DOI BibTeX RDF	memory page migration, dynamic processor allocation policy, multiprogrammed workload, OpenMP, CC-NUMA
18	Gehan Weerasinghe, Imad Antonios, Lester Lipsky	A Generalized Analytic Performance Model of Distributed Systems that Perform N Tasks Using P Fault-Prone Processors.	IPDPS	2002	DBLP DOI BibTeX RDF	Performance Evaluation, Fault-Tolerance, Markov Chains, Networks of Workstations, Processor Failures
18	Bogdan S. Chlebus, Roberto De Prisco, Alexander A. Shvartsman	Performing tasks on synchronous restartable message-passing processors.	Distributed Comput.	2001	DBLP DOI BibTeX RDF	Processor restarts, Fault-tolerance, Distributed systems, Load balancing, Work
18	Dirk Fimmel	Generation of Scheduling Functions Supporting LSGP-Partitioning.	ASAP	2000	DBLP DOI BibTeX RDF	processor array design, LSGP-partitioning, load balancing, linear programming, automatic parallelization, resource constraints
18	Dale E. Parson, Paul Beatty, John Glossner, Bryan Schlieder	A Framework for Simulating Heterogeneous Virtual Processors.	Annual Simulation Symposium	1999	DBLP DOI BibTeX RDF	simulation, design pattern, multiprocessor, processor, object-oriented framework, debugger
18	Moonsoo Kang, Chansu Yu	Job-Based Queue Delay Modeling in a Space-Shared Hypercube.	ICPP Workshops	1999	DBLP DOI BibTeX RDF	topological delay, processor allocation, space sharing, queue delay, Hypercube computer
18	Peggy B. K. Pang, Mark R. Greenstreet	Self-Timed Meshes Are Faster Than Synchronous.	ASYNC	1997	DBLP DOI BibTeX RDF	self-timed meshes, linear speed-up, per-processor performance, simulation, logic CAD
18	Basem A. Nayfeh, Kunle Olukotun, Jaswinder Pal Singh	The Impact of Shared-Cache Clustering in Small-Scale Shared-Memory Multiprocessors.	HPCA	1996	DBLP DOI BibTeX RDF	shared-cache clustering, small-scale shared-memory multiprocessors, shared global bus, low-latency interconnections, performance evaluation, shared memory systems, cache storage, memory system, multichip module, L2 cache, processor performance, high-bandwidth, bus contention
18	Satoshi Fujita, Masafumi Yamashita	Maintaining a Dynamic Set of Processors in a Distributed System.	WDAG	1996	DBLP DOI BibTeX RDF	processor structure, amortized message complexity, data structure, group communication, dynamic set
18	Catherine H. Gebotys, Robert J. Gebotys	Optimized mapping of video applications to hardware-software for VLSI architectures.	HICSS (1)	1995	DBLP DOI BibTeX RDF	integer optimization, video computations, video systems, optimized mapping, scheduling, VLSI, optimisation, VLSI architectures, video signal processing, VLIW processor
18	A. J. Korenjak	A practical method for constructing LR(k) processors.	Commun. ACM	1969	DBLP DOI BibTeX RDF	LR(k) grammar, deterministic language, language processor, syntax-directed compiler, ALGOL, ALGOL, parser, context-free language, syntactic analysis
18	Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt	Instruction set synthesis with efficient instruction encoding for configurable processors.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	ISA customization and specialization, bitwidth-economical, Application-specific instruction set processor (ASIP), configurable processor, instruction encoding
18	Jer-Yu Hsu, Yan-Zu Wu, Xuan-Yi Lin, Yeh-Ching Chung	SCRF - A Hybrid Register File Architecture.	PaCT	2007	DBLP DOI BibTeX RDF	cluster processor architecture, register architecture, register allocation algorithm, VLIW processor
18	Gokhan Memik, William H. Mangione-Smith	A flexible accelerator for layer 7 networking applications.	DAC	2002	DBLP DOI BibTeX RDF	pattern matching, network processor, accelerator, table lookup, application-specific processor, networking applications
18	Hyesook Lim, Vincenzo Piuri, Earl E. Swartzlander Jr.	A Serial-Parallel Architecture for Two-Dimensional Discrete Cosine and Inverse Discrete Cosine Transforms.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Application specific processor architecture, Inverse Discrete Cosine Transform, serial-parallel processor, image compression, Discrete Cosine Transform, systolic array
18	Sergej Sawitzki, Rainer G. Spallek, Jens Schönherr, Bernd Straube	Formal Verification for Microprocessors with Extendable Instruction Set.	ASAP	2000	DBLP DOI BibTeX RDF	reconfigurable processor architecture, abstraction techniques, formal verification, pipeline processor
18	Juan C. Moure, Daniel Franco 0002, Elisa Heymann, Emilio Luque	TransCom: A Communication Microkernel for Transputers.	PDP	1996	DBLP DOI BibTeX RDF	communication microkernel, TransCom, TransRouter, data transport, processor resource, parallel programming, parallel programming, parallel architecture, message passing, message passing, communication network, communication protocols, distributed memory systems, processor scheduling, network operating systems, access protocols, operating system kernels, transputers, distributed-memory multiprocessor, load distribution, communication primitives, transputer systems
18	Roger Espasa, Mateo Valero	Decoupled Vector Architectures.	HPCA	1996	DBLP DOI BibTeX RDF	decoupled vector architectures, trace driven approach, Perfect Club programs, realistic memory latencies, bypassing technique, total memory traffic, performance advantages, performance evaluation, performance, vector processor, vector processor systems, hardware cost
18	Eric A. Brewer, Paul Gauthier, Armando Fox, Angela Schuett	Software Techniques for Improving MPP Bulk-Transfer Performance.	IPPS	1996	DBLP DOI BibTeX RDF	software techniques, bulk-transfer performance, traffic interleaving, Thinking Machines CM-5, one-on-one communication, MIT Alewife machine, token-passing scheme, distributed dynamic scheduling, irregular traffic patterns, traffic massaging, near-permutations, performance evaluation, parallel machines, processor scheduling, software performance evaluation, telecommunication traffic, preprocessing, barriers, network congestion, algorithm performance, Intel Paragon, static scheduling, massively parallel processor, global state
18	Xuemin Lin 0001, Simon Fox	An effective parallelization of execution of multijoins in multiprocessor systems.	ISPAN	1996	DBLP DOI BibTeX RDF	multijoins execution, synchronous execution strategy, processor allocation problem, inter-operator parallelization problem, parallelization, relational databases, multiprocessing systems, multiprocessor systems, processor scheduling
18	Anna M. del Corral, José M. Llabería	Access order to avoid inter-vector-conflicts in complex memory systems.	IPPS	1995	DBLP DOI BibTeX RDF	access order, inter-vector-conflicts, complex memory systems, vector processor accessing vectors, concurrent memory access, inter-conflicts, performance evaluation, performance, vector processor systems, memory subsystem, memory modules
18	Filip Thoen, Marco Cornero, Gert Goossens, Hugo De Man	Real-time multi-tasking in software synthesis for information processing systems.	ISSS	1995	DBLP DOI BibTeX RDF	automatic processor mapping, automatically generated application-specific solution, concurrent process system specification, flexible execution models, hardware resource utilization, information processing systems, internal representation model, mobile satellite communication, personal terminal receiver demodulator, real-time multi-tasking, static information, time utilization, real-time systems, embedded systems, concurrency control, processor scheduling, timing constraints, computer aided software engineering, software synthesis, multiprocessing programs
18	Shuichi Oikawa, Hideyuki Tokuda	Efficient timing management for user-level real-time threads.	IEEE Real Time Technology and Applications Symposium	1995	DBLP DOI BibTeX RDF	efficient timing management, user-level real-time threads, specified time, upcalled user-level scheduler, user-level scheduler overhead, shared user-level timers, shared kernel/user structure, upcall performance, scheduling, performance evaluations, software engineering, real-time systems, resource allocation, timing, shared memory systems, kernel, processor scheduling, software performance evaluation, operating system kernels, hints, virtual processor
18	Emile Haddad	Optimal load distribution for asynchronously scheduled homogeneous multiprocessor and distributed systems.	HICSS (2)	1995	DBLP DOI BibTeX RDF	optimal load distribution, asynchronously scheduled homogeneous multiprocessor systems, interacting tasks, identical processors, job completion time minimization, execution initiation times, earliest availability, load parameters, optimal load allocation, uneven module distribution, distributed systems, resource allocation, distributed processing, multiprocessing systems, processor scheduling, minimisation, system parameters, processor assignment
18	Ben Lee, Chae Shin, Ali R. Hurson	A strategy for scheduling partially ordered program graphs onto multicomputers.	HICSS (2)	1995	DBLP DOI BibTeX RDF	partially ordered program graphs, scalar performance, user code, compile-time scheduling heuristic, SISAL programs, scheduling, performance evaluation, scalability, parallel programming, message passing, reconfigurable architectures, program compilers, processor scheduling, multicomputers, communication overhead, simulation studies, BLAS, massively parallel processing, message-passing programming, inter-processor communication, message-passing multicomputers
18	Thin-Fong Tsuei, Mary K. Vernon	A Multiprocessor Bus Design Model Validated by System Measurement.	IEEE Trans. Parallel Distributed Syst.	1992	DBLP DOI BibTeX RDF	commercial multiprocessor bus, bus design, asynchronous memorywrite operations, in-order delivery, processor read requests, memoryresponses, outstanding processor requests, two-level hierarchical model, mean value analysis techniques, measured system performance, parallel program workloads, memory access characteristics, analytic queueing models, model tractability, detailed simulation, system design tradeoffs, parallel programming, formal verification, Markov chain, Markov processes, queueing theory, multiprocessing systems, queueing networks, system buses, priority scheduling, performanceevaluation, system measurement
18	Yaohan Chu	Direct Execution In A High-Level Computer Architecture.	ACM Annual Conference (1)	1978	DBLP DOI BibTeX RDF	Control processor, Data processor, Lexical processing, Computer architecture, Interactive system, High-level architecture, Associative memory, Direct execution
18	Stijn Eyerman, Lieven Eeckhout	Probabilistic job symbiosis modeling for SMT processor scheduling.	ASPLOS	2010	DBLP DOI BibTeX RDF	simultaneous multi-threading (smt), symbiotic job scheduling, performance modeling
18	Ranjani Sridharan, Rabi N. Mahapatra	Reliability aware power management for dual-processor real-time embedded systems.	DAC	2010	DBLP DOI BibTeX RDF	dynamic fault-tolerance, dynamic power management
18	Jinwon Lee, Seungwoo Kang, Youngki Lee, Sang Jeong Lee, Junehwa Song	BMQ-Processor: A High-Performance Border-Crossing Event Detection Framework for Large-Scale Monitoring Applications.	IEEE Trans. Knowl. Data Eng.	2009	DBLP DOI BibTeX RDF
18	Bo Fu, Paul Ampadu	An Area Efficient FFT/IFFT Processor for MIMO-OFDM WLAN 802.11n.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	WLAN 802.11n, Fast fourier transform (FFT), MIMO-OFDM
18	Yong Ki Lee, Kazuo Sakiyama, Lejla Batina, Ingrid Verbauwhede	Elliptic-Curve-Based Security Processor for RFID.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
18	Bingfeng Mei, Bjorn De Sutter, Tom Vander Aa, M. Wouters, Andreas Kanstein, Steven Dupont	Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	H.264/AVC decoder, FPGA, multimedia, embedded system, reconfigurable architecture, VLIW
18	Sachin S. Sapatnekar	Adapting to the times [review of Adaptive Techniques for Dynamic Processor Optimization: Theory and Practice (Wang, A. and Naffziger, S., Eds.; 2008)].	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF
18	Izhar Zaidi, Atukem Nabina, Cedric Nishan Canagarajah, José L. Núñez-Yáñez	Power/Area Analysis of a FPGA-Based Open-Source Processor using Partial Dynamic Reconfiguration.	DSD	2008	DBLP DOI BibTeX RDF
18	Toshinori Sato, Toshimasa Funaki	Dependability, power, and performance trade-off on a multicore processor.	ASP-DAC	2008	DBLP DOI BibTeX RDF
18	Caroline Hagège, Xavier Tannier	XTM: A Robust Temporal Text Processor.	CICLing	2008	DBLP DOI BibTeX RDF
18	Martin Labrecque, Peter Yiannacouras, J. Gregory Steffan	Scaling Soft Processor Systems.	FCCM	2008	DBLP DOI BibTeX RDF
18	Jack Coyne, David Cyganski, R. James Duckworth	FPGA-Based Co-processor for Singular Value Array Reconciliation Tomography.	FCCM	2008	DBLP DOI BibTeX RDF
18	Isaac Gelado, John H. Kelm, Shane Ryoo, Steven S. Lumetta, Nacho Navarro, Wen-mei W. Hwu	CUBA: an architecture for efficient CPU/co-processor data communication.	ICS	2008	DBLP DOI BibTeX RDF	co-processors
18	Wesley Alvaro, Jakub Kurzak, Jack J. Dongarra	Fast and Small Short Vector SIMD Matrix Multiplication Kernels for the Synergistic Processing Element of the CELL Processor.	ICCS (1)	2008	DBLP DOI BibTeX RDF
18	Catherine H. Crawford, Paul Henning, Michael Kistler, Cornell Wright	Accelerating computing with the cell broadband engine processor.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	hybrid programming models, accelerators
18	Gabriel H. Loh	A modular 3d processor for flexible product design and technology migration.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	modular, superscalar, 3d-integration
18	Sankar Gurumurthy, Ramtilak Vemu, Jacob A. Abraham, Suriyaprakash Natarajan	On efficient generation of instruction sequences to test for delay defects in a processor.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	native-mode self-test, delay test, software based self-test
18	Francesco Abate, Massimo Violante	Coping with Obsolescence of Processor Cores in Critical Applications.	DFT	2008	DBLP DOI BibTeX RDF
18	Alejandro García, Oliverio J. Santana, Enrique Fernández, Pedro Medina, Mateo Valero	LPA: A First Approach to the Loop Processor Architecture.	HiPEAC	2008	DBLP DOI BibTeX RDF
18	Jianjun Guo, Ming-che Lai, Zhengyuan Pang, Libo Huang, Fangyuan Chen, Kui Dai, Zhiying Wang 0003	Memory System Design for a Multi-core Processor.	CISIS	2008	DBLP DOI BibTeX RDF
18	Tak Wah Lam, Lap-Kei Lee, Isaac Kar-Keung To, Prudence W. H. Wong	Energy Efficient Deadline Scheduling in Two Processor Systems.	ISAAC	2007	DBLP DOI BibTeX RDF
18	Taekyu Kim, Sin-Chong Park	Arctangent Processor Design for the Frequency Offset Estimation of IEEE 802.16D Wirelessman-OFDM System.	SiPS	2007	DBLP DOI BibTeX RDF
18	Katsutoshi Seki, Tomoyoshi Kobori, James Okello, Masao Ikekawa	A Cordic-Based Reconfigrable Systolic Array Processor for MIMO-OFDM Wireless Communications.	SiPS	2007	DBLP DOI BibTeX RDF
18	Gabriel Mateescu	Overcoming the processor communication overhead in MPI applications.	SpringSim (2)	2007	DBLP BibTeX RDF
18	Mehdi EffatParvar, MohammadReza EffatParvar, Akbar Bemana, Mehdi Dehghan 0001	Determining a Central Controlling Processor with Fault Tolerant Method in Distributed System.	ITNG	2007	DBLP DOI BibTeX RDF
18	Richard P. Kleihorst, Anteneh A. Abbo, Ben Schueler, Alexander Danilin	Camera mote with a high-performance parallel processor for real-time frame-based video processing.	AVSS	2007	DBLP DOI BibTeX RDF
18	Yi Qian, Ang Li, Qin Wang 0004	Design and Implementation of a General Purpose Neural Network Processor.	ISNN (2)	2007	DBLP DOI BibTeX RDF
18	Shorin Kyo, Takuya Koga, Hanno Lieske, Shouhei Nomoto, Shin'ichiro Okazaki	A low-cost mixed-mode parallel processor architecture for embedded systems.	ICS	2007	DBLP DOI BibTeX RDF	embedded systems, parallel architectures, SIMD, MIMD, multimedia processing, tile architectures, mixed-mode
18	Nicholas Vun, Wooi-Boon Goh	The design of effective low cost embedded processor development kits for supporting take-home self-practice pedagogies.	ICPADS	2007	DBLP DOI BibTeX RDF
18	Eryk Laskowski, Marek Tudruj	Inter-processor Communication Optimization in Dynamically Reconfigurable Embedded Parallel Systems.	PPAM	2007	DBLP DOI BibTeX RDF
18	Liang Liu 0002, Junyan Ren, Xuejing Wang, Fan Ye 0001	Design of Low-Power, 1GS/s Throughput FFT Processor for MIMO-OFDM UWB Communication System.	ISCAS	2007	DBLP DOI BibTeX RDF
18	Junichiro Makino, Kei Hiraki, Mary Inaba	GRAPE-DR: 2-Pflops massively-parallel computer with 512-core, 512-Gflops processor chips for scientific computing.	SC	2007	DBLP DOI BibTeX RDF
18	Hong Xiao, Di Wu	A Component Model for Network Processor Based System.	AICCSA	2007	DBLP DOI BibTeX RDF
18	Mitsuru Matsui, Junko Nakajima	On the Power of Bitslice Implementation on Intel Core2 Processor.	CHES	2007	DBLP DOI BibTeX RDF	Fast Software Encryption, Bitslice, KASUMI, Core2, AES
18	Shuifa Sun, Sam Kwong, Bang Jun Lei, Sheng Zheng	Digital Watermarking Based on Stochastic Resonance Signal Processor.	PCM	2007	DBLP DOI BibTeX RDF	signal processing, digital watermarking, stochastic resonance
18	Seyyed-Mahmood Hosseini-Moghaddam, Mahmood Naghibzadeh	A New Processor Allocation Strategy Using ESS (Expanding Square Strategy).	PDP	2006	DBLP DOI BibTeX RDF
18	Ju-Ho Sohn, Jeong-Ho Woo, Jerald Yoo, Hoi-Jun Yoo	Design and test of fixed-point multimedia co-processor for mobile applications.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
18	Alokika Dash, Peter Petrov	Energy-Efficient Cache Coherence for Embedded Multi-Processor Systems through Application-Driven Snoop Filtering.	DSD	2006	DBLP DOI BibTeX RDF
18	Yu-Hung Lee, Tzu-Hao Yu, Kuo-Ken Huang, An-Yeu Wu	Rapid IP Design of Variable-length Cached-FFT Processor for OFDM-based Communication Systems.	SiPS	2006	DBLP DOI BibTeX RDF
18	Gi-Ho Park, Sung Woo Chung, Han-Jong Kim, Jung-Bin Im, Jung-Wook Park, Shin-Dug Kim, Sung-Bae Park	Practice and Experience of an Embedded Processor Core Modeling.	HPCC	2006	DBLP DOI BibTeX RDF
18	Prabhu Rajamani, Jatan P. Shah, Vadhiraj Sankaranarayanan, Rama Sangireddy	High performance and alleviated hot-spot problem in processor frontend with enhanced instruction fetch bandwidth utilization.	IPCCC	2006	DBLP DOI BibTeX RDF
18	ZhiLei Chai, Wenbo Xu 0001, Shi-liang Tu, Zhang-long Chen	Implementing Predictable Scheduling in RTSJ-Based Java Processor.	International Conference on Computational Science (1)	2006	DBLP DOI BibTeX RDF
18	Jeesung Lee, Hanho Lee, Sang-in Cho, Sangsung Choi	A high-speed, low-complexity radix-24 FFT processor for MB-OFDM UWB systems.	ISCAS	2006	DBLP DOI BibTeX RDF
18	Rama Sangireddy	Fast and low-power processor front-end with reduced rename logic circuit complexity.	ISCAS	2006	DBLP DOI BibTeX RDF
18	Neil Smyth, Máire McLoone, John V. McCanny	An Adaptable And Scalable Asymmetric Cryptographic Processor.	ASAP	2006	DBLP DOI BibTeX RDF
18	Hui Wu 0001, Sridevan Parameswaran	Minimising the Energy Consumption of Real-Time Tasks with Precedence Constraints on a Single Processor.	EUC	2006	DBLP DOI BibTeX RDF
18	Weiwu Hu, Fuxin Zhang, Zusong Li	Microarchitecture of the Godson-2 Processor.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	superscalar pipeline, dynamic scheduling non-blocking cache, load speculation, branch prediction, out-of-order execution, register renaming
18	Yezekael Hayel, Bruno Tuffin	Pricing for Heterogeneous Services at a Discriminatory Processor Sharing Queue.	NETWORKING	2005	DBLP DOI BibTeX RDF	Queueing theory, Economics
18	Jan-Willem van de Waerdt, Stamatis Vassiliadis, Sanjeev Das, Sebastian Mirolo, Chris Yen, Bill Zhong, Carlos Basto, Jean-Paul van Itegem, Dinesh Amirtharaj, Kulbhushan Kalra, Pedro Rodriguez, Hans Van Antwerpen	The TM3270 Media-Processor.	MICRO	2005	DBLP DOI BibTeX RDF
18	Cyrus Bazeghi, Francisco J. Mesa-Martinez, Jose Renau	uComplexity: Estimating Processor Design Effort.	MICRO	2005	DBLP DOI BibTeX RDF
18	Virantha N. Ekanayake, Clinton Kelly IV, Rajit Manohar	BitSNAP: Dynamic Significance Compression for a Low-Energy Sensor Network Asynchronous Processor.	ASYNC	2005	DBLP DOI BibTeX RDF
18	Kazutoshi Kobayashi, Masao Aramoto, Yoichi Yuyama, Akihiko Higuchi, Hidetoshi Onodera	A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing.	ASP-DAC	2005	DBLP DOI BibTeX RDF
18	Chih-Pin Su, Chen-Hsing Wang, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu	Design and test of a scalable security processor.	ASP-DAC	2005	DBLP DOI BibTeX RDF
18	Akihito Takahashi, Stanislav Sedukhin	Parallel Blocked Algorithm for Solving the Algebraic Path Problem on a Matrix Processor.	HPCC	2005	DBLP DOI BibTeX RDF
18	Brian F. Veale, John K. Antonio, Monte P. Tull	Configuration Steering for a Reconfigurable Superscalar Processor.	IPDPS	2005	DBLP DOI BibTeX RDF
18	Thomas Rauber, Gudula Rünger	A Data-Re-Distribution Library for Multi-Processor Task Programming.	IPDPS	2005	DBLP DOI BibTeX RDF
18	Dong-Sun Kim 0002, Hyunsik Kim, Hong-Sik Kim, Gunhee Han, Duck-Jin Chung	A SIMD Neural Network Processor for Image Processing.	ISNN (2)	2005	DBLP DOI BibTeX RDF
18	Sibin Mohan, Frank Mueller 0001, David B. Whalley, Christopher A. Healy	Timing Analysis for Sensor Network Nodes of the Atmega Processor Family.	IEEE Real-Time and Embedded Technology and Applications Symposium	2005	DBLP DOI BibTeX RDF
18	Yutian Zhao, Ahmet T. Erdogan, Tughrul Arslan	A novel low-power reconfigurable FFT processor.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
18	Masayuki Masuda, Kazuhito Ito	Rapid and precise instruction set evaluation for application specific processor design.	ISCAS (6)	2005	DBLP DOI BibTeX RDF