Search results for "skew"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
15	Yihong Wu 0002, Youfu Li, Zhanyi Hu	Easy Calibration for Para-catadioptric-like Camera.	IROS	2006	DBLP DOI BibTeX RDF
15	Anand Rajaram, David Z. Pan	Variation tolerant buffered clock network synthesis with cross links.	ISPD	2006	DBLP DOI BibTeX RDF	non-tree clocks, physical design, VLSI CAD, clock network
15	Chia-Chun Tsai, Jan-Ou Wu, Chien-Wen Kao, Trong-Yen Lee, Rong-Shue Hsiao	Coupling aware RLC-based clock routings for crosstalk minimization.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Sitt Tontisirin, Reinhard Tielert	A Gb/s one-fourth-rate CMOS CDR circuit without external reference clock.	ISCAS	2006	DBLP DOI BibTeX RDF
15	Amir H. Ajami, Kaustav Banerjee, Massoud Pedram	Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
15	Egon Schulte	Chiral Polyhedra in Ordinary Space, II.	Discret. Comput. Geom.	2005	DBLP DOI BibTeX RDF
15	Jianping Zhou, Minh N. Do, Jelena Kovacevic	Multidimensional orthogonal filter bank characterization and design using the Cayley transform.	IEEE Trans. Image Process.	2005	DBLP DOI BibTeX RDF
15	Muhammad Sarfraz 0001, S. A. Shahab	An Efficient Scheme for Tilt Correction in Arabic OCR System.	CGIV	2005	DBLP DOI BibTeX RDF
15	Kenji Imasaki, Sivarama P. Dandamudi	A New Join Algorithm for Cluster-Based Database Systems.	ISPDC	2005	DBLP DOI BibTeX RDF
15	Juang-Ying Chueh, Marios C. Papaefthymiou, Conrad H. Ziesler	Two-Phase Resonant Clock Distribution.	ISVLSI	2005	DBLP DOI BibTeX RDF
15	Scott Fairbanks, Simon W. Moore	Self-Timed Circuitry for Global Clocking.	ASYNC	2005	DBLP DOI BibTeX RDF
15	Hao-Yueh Hsieh, Ting-Chi Wang	Simple yet effective algorithms for block and I/O buffer placement in flip-chip design.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
15	Min Pan, Chris C. N. Chu, Hai Zhou 0001	Timing yield estimation using statistical static timing analysis.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
15	Huanliang Sun, Ge Yu 0001, Yubin Bao, Faxin Zhao, Daling Wang	CDS-Tree: An Effective Index for Clustering Arbitrary Shapes in Data Streams.	RIDE	2005	DBLP DOI BibTeX RDF
15	Yongqiang Lu 0001, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou 0001, Yici Cai, Liang Huang, Jiang Hu	Navigating registers in placement for clock network minimization.	DAC	2005	DBLP DOI BibTeX RDF	low power, placement, clock network, variation tolerance
15	U. Pal 0001, Nilamadhaba Tripathy	Recognition of Indian Multi-oriented and Curved Text.	ICDAR	2005	DBLP DOI BibTeX RDF
15	Faisal Farooq, Venu Govindaraju, Michael P. Perrone	Pre-processing Methods for Handwritten Arabic Documents.	ICDAR	2005	DBLP DOI BibTeX RDF
15	Egon Schulte	Chiral Polyhedra in Ordinary Space, I.	Discret. Comput. Geom.	2004	DBLP DOI BibTeX RDF
15	Kathie Cameron, Elaine M. Eschen, Chính T. Hoàng, R. Sritharan	The list partition problem for graphs.	SODA	2004	DBLP BibTeX RDF
15	Erland Nilsson, Johnny Öberg	Reducing power and latency in 2-D mesh NoCs using globally pseudochronous locally synchronous clocking.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	hot-potato, pseudochronous, network on chip, mesh, clocking, GALS, GPLS
15	Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja	A yield improvement methodology using pre- and post-silicon statistical clock scheduling.	ICCAD	2004	DBLP DOI BibTeX RDF
15	Aaron P. Hurst, Philip Chong, Andreas Kuehlmann	Physical placement driven by sequential timing analysis.	ICCAD	2004	DBLP DOI BibTeX RDF
15	Yukiko Kubo, Hiroshi Miyashita, Yoji Kajitani, Kazuyuki Tateishi	Equidistance routing in high-speed VLSI layout design.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	box routing, equidistance routing, rectilinear route, slant symmetric grid, dynamic programming, VLSI system, channel routing
15	T. J. Thorp, G. S. Yee, Carl M. Sechen	Design and synthesis of dynamic circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
15	Ajanta Chakraborty, Mark R. Greenstreet	Efficient Self-Timed Interfaces for Crossing Clock Domains.	ASYNC	2003	DBLP DOI BibTeX RDF
15	Ho-Hyun Park	On Estimating Result Sizes of Multi-way Spatial Joins.	ICCSA (3)	2003	DBLP DOI BibTeX RDF
15	Frank O'Mahony, C. Patrick Yue, Mark Horowitz, S. Simon Wong	Design of a 10GHz clock distribution network using coupled standing-wave oscillators.	DAC	2003	DBLP DOI BibTeX RDF	distributed oscillators, on-chip phase measurement, resonant clocking, salphasic, standing wave, clock distribution, coupled oscillators
15	Kang-Won Lee, Khalil Amiri, Sambit Sahu, Chitra Venkatramani	On the sensitivity of cooperative caching performance to workload and network characteristics.	SIGMETRICS	2002	DBLP DOI BibTeX RDF
15	Stefan Lund, Lars Bengtsson	Synchronizing a High-Speed SIMD Processor Array.	DSD	2001	DBLP DOI BibTeX RDF
15	Baiying Yu, William C. Black Jr.	Error analysis for time-interleaved analog channels.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
15	Hong-Yean Hsieh, Wentai Liu, Ralph K. Cavin III	Integrated parametric timing optimization of digital systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
15	Mely Chen Chi, Shih-Hsu Huang	A Reliable Clock Tree Design Methodology for ASIC Designs.	ISQED	2000	DBLP DOI BibTeX RDF	Clock tree design, Clock tree synthesis
15	Vikas Mehrotra, Shiou Lin Sam, Duane S. Boning, Anantha P. Chandrakasan, Rakesh Vallishayee, Sani R. Nassif	A methodology for modeling the effects of systematic within-die interconnect and device variation on circuit performance.	DAC	2000	DBLP DOI BibTeX RDF
15	Jae-Tack Yoo, Ganesh Gopalakrishnan, Kent F. Smith	Timing constraints for high-speed counterflow-clocked pipelining.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
15	Mustafa Celik, Lawrence T. Pileggi	Metrics and bounds for phase delay and signal attenuation in RC(L)clock trees.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
15	J. Bruce Millar, Peter Gillingham	Two High-Bandwidth Memory Bus Structures.	IEEE Des. Test Comput.	1999	DBLP DOI BibTeX RDF	SLDRAM, Direct Rambus, DRAM, memory design
15	Soo-Chang Pei, Ji-Hwei Horng	A moment-based approach for deskewing rotationally symmetric shapes.	IEEE Trans. Image Process.	1999	DBLP DOI BibTeX RDF
15	Hamid K. Aghajan, Babak Hossein Khalaj, Thomas Kailath	Estimation of multiple 2-D uniform motions by SLIDE: subspace-based line detection.	IEEE Trans. Image Process.	1999	DBLP DOI BibTeX RDF
15	Jeong-Ki Kim, Jae-Woo Chang	VPSF: A Parallel Signature File Technique Using Vertical Partitioning and Extendable Hashing.	DEXA	1999	DBLP DOI BibTeX RDF
15	Tyler Thorp, Gin Yee, Carl Sechen	Design and Synthesis of Monotonic Circuits.	ICCD	1999	DBLP DOI BibTeX RDF
15	Matthew E. Becker, Thomas F. Knight Jr.	Transmission Line Clock Driver.	ICCD	1999	DBLP DOI BibTeX RDF
15	Josef Schmid, Joachim Knäblein	Advanced Synchronous Scan Test Methodology for Multi Clock Domain ASICs.	VTS	1999	DBLP DOI BibTeX RDF
15	Anil K. Jain 0001, Bin Yu 0002	Document Representation and Its Application to Page Decomposition.	IEEE Trans. Pattern Anal. Mach. Intell.	1998	DBLP DOI BibTeX RDF	document storage and retrieval, region identification, document image analysis, Document model, page segmentation
15	Chandrajit L. Bajaj, Robert J. Holt, Arun N. Netravali	Rational Parametrizations of Nonsingular Real Cubic Surfaces.	ACM Trans. Graph.	1998	DBLP DOI BibTeX RDF	cubic surface modeling, dual form representations, numeric and symbolic computation, rational parametrization, graphics display
15	Vern Paxson	On Calibrating Measurements of Packet Transit Times.	SIGMETRICS	1998	DBLP DOI BibTeX RDF
15	Takahiko Shintani, Masaru Kitsuregawa	Parallel Mining Algorithms for Generalized Association Rules with Classification Hierarchy.	SIGMOD Conference	1998	DBLP DOI BibTeX RDF
15	Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu	Design of minimum and uniform bipartites for optimum connection blocks of FPGA.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
15	Ashok Vittal, Malgorzata Marek-Sadowska	Low-power buffered clock tree design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
15	Keith M. Carrig, Albert M. Chu, Frank D. Ferraiolo, John G. Petrovick, P. Andrew Scott, Richard J. Weiss	A Clock Methodology for High-Performance Microprocessors.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
15	Yuzhong Sun, Zhiwei Xu 0002, Mingfa Zhu	A Hybrid Time Synchronization Implemented Through Special Ring Array for Mesh or Torus.	IPPS	1997	DBLP DOI BibTeX RDF
15	Les Hall, Mark Clements, Wentai Liu, Griff L. Bilbro	Clock Distribution Using Cooperative Ring Oscillators.	ARVLSI	1997	DBLP DOI BibTeX RDF
15	Ravichandran Ramachandran, Shih-Lien Lu	Efficient arithmetic using self-timing.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
15	Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi	Post-processing of clock trees via wiresizing and buffering for robust design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
15	Bin Yu 0002, Anil K. Jain 0001	A Generic System for Form Dropout.	IEEE Trans. Pattern Anal. Mach. Intell.	1996	DBLP DOI BibTeX RDF	learning form structure, character reconstruction, block adjacency graph, segmentation, document image analysis, Form processing
15	Guy Even, Ami Litman	Overcoming chip-to-chip delays and clock skews.	ASAP	1996	DBLP DOI BibTeX RDF	chip-to-chip delays, chip-to-chip interconnections, feasible clock period, large systolic linear arrays, systolic two-dimensional arrays, logic duplication, delays, logic design, systolic arrays, systolic array, functionality, retiming, clock skews
15	Bernard A. McCoy, Gabriel Robins	Non-tree routing [VLSI layout].	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
15	C. Thomas Gray, Wentai Liu, Ralph K. Cavin III	Timing constraints for wave-pipelined systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
15	Scott T. Leutenegger, Daniel M. Dias	A Modeling Study of the TPC-C Benchmark.	SIGMOD Conference	1993	DBLP DOI BibTeX RDF
15	Raimo Ylinen	Polynominal Systems Theory for n-D Systems Applied to Vision-Based Control.	EUROCAST	1993	DBLP DOI BibTeX RDF
15	S. Seshadri, Jeffrey F. Naughton	Sampling Issues in Parallel Database Systems.	EDBT	1992	DBLP DOI BibTeX RDF
15	Kien A. Hua, Chiang Lee, Jih-Kwon Peir	A high performance hybrid architecture for concurrent query execution.	SPDP	1990	DBLP DOI BibTeX RDF
14	Michal Botur, Ivan Chajda, Radomír Halas	Are basic algebras residuated structures?	Soft Comput.	2010	DBLP DOI BibTeX RDF	Basic algebra, Commutative basic algebra, Residuated groupoid, Skew adjointness property, Residuated lattice
14	Markus Diem, Florian Kleber, Robert Sablatnig	Document analysis applied to fragments: feature set for the reconstruction of torn documents.	Document Analysis Systems	2010	DBLP DOI BibTeX RDF	document reconstruction, skew, layout analysis
14	Kees Roos	Farkas Lemma.	Encyclopedia of Optimization	2009	DBLP DOI BibTeX RDF	Theorem of the alternative, Skew-symmetric matrix, Certificate, Orthogonal matrix, Inequality systems
14	Chien Pang Lu, Mango Chia-Tso Chao, Chen Hsing Lo, Chih-Wei Chang	A metal-only-ECO solver for input-slew and output-loading violations.	ISPD	2009	DBLP DOI BibTeX RDF	input skew violation, output loading, buffer insertion, eco
14	Kazi Md. Abdullah Al Mamun, Gyanendra Prasad Joshi, Sung Won Kim	Next Generation Delay and Performance Measuring Algorithm for an Overall Network.	NCM (1)	2008	DBLP DOI BibTeX RDF	performance statistics, quality of service, clock skew, error rate, Delay measurement
14	Haewon Choi, ByungRae Cha, Kyungjun Kim	Energy Efficient Location-Based Clustering for Skewed-Topology Wireless Sensor Networks.	GPC Workshops	2008	DBLP DOI BibTeX RDF	clustering, wireless sensor network, topology, location, skew
14	Tom Fawcett, Alexandru Niculescu-Mizil	PAV and the ROC convex hull.	Mach. Learn.	2007	DBLP DOI BibTeX RDF	Classifier calibration, Class skew, Classification, ROC
14	Abhishek Tiwari 0002, Smruti R. Sarangi, Josep Torrellas	ReCycle: : pipeline adaptation to tolerate process variation.	ISCA	2007	DBLP DOI BibTeX RDF	pipeline, process variation, clock skew
14	Tom Fawcett, Peter A. Flach	A Response to Webb and Ting's On the Application of ROC Analysis to Predict Classification Performance Under Varying Class Distributions.	Mach. Learn.	2005	DBLP DOI BibTeX RDF	classifier evaluation, class skew, classification, ROC
14	Michael Manzo, Tanya G. Roosta, Shankar Sastry 0001	Time synchronization attacks in sensor networks.	SASN	2005	DBLP DOI BibTeX RDF	clock drift and skew, security, sensor network, authentication, time-synchronization
14	Bruno Tenório Ávila, Rafael Dueire Lins, Lamberto Oliveira	A new rotation algorithm for monochromatic images.	ACM Symposium on Document Engineering	2005	DBLP DOI BibTeX RDF	monochromatic image rotation, skew correction
14	Mark Brehob, Stephen Wagner, Eric Torng, Richard J. Enbody	Optimal Replacement Is NP-Hard for Nonstandard Caches.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	optimal cache replacement policy, interval scheduling, skew cache, multilateral cache, approximation algorithm, Cache, victim cache
14	Anders Edman, Christer Svensson	Timing closure through a globally synchronous, timing partitioned design methodology.	DAC	2004	DBLP DOI BibTeX RDF	wire delays, clock skew, timing closure
14	Tom Fawcett	"In vivo" spam filtering: a challenge problem for KDD.	SIGKDD Explor.	2003	DBLP DOI BibTeX RDF	challenge problems, class skew, data streams, text classification, spam, cost-sensitive learning, concept drift, imbalanced data
14	Peter Benner, Ralph Byers, Eric Barth	Algorithm 800: Fortran 77 subroutines for computing the eigenvalues of Hamiltonian matrices. I: the square-reduced method.	ACM Trans. Math. Softw.	2000	DBLP DOI BibTeX RDF	(square-reduced), Hamiltonian matrix, algebraic Riccati equation, skew-Hamiltonian matrix, eigenvalues, FORTRAN 77
14	Masahiko Toyonaga, Keiichi Kurokawa, Takuya Yasui, Atsushi Takahashi 0001	A practical clock tree synthesis for semi-synchronous circuits.	ISPD	2000	DBLP DOI BibTeX RDF	clock-input timing, environmental and manufacturing conditions, semi-synchronous, various timing clock tree, zero skew clock tree, clock scheduling
14	Ayoob E. Dooply, Kenneth Y. Yun	Optimal Clocking and Enhanced Testability for High-Performance Self-Resetting Domino Pipelines.	ARVLSI	1999	DBLP DOI BibTeX RDF	Self-resetting domino, time borrowing, roadblock, skew tolerance design-for-testability, scan register, multiple stuck fault
14	Ahmed El-Amawy, Priyalal Kulasinghe	On the Complexity of Designing Optimal Branch-and-Combine Clock Networks.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF	skew bound, branch-and-combine network, graph orientation, computational complexity, optimal design, Clock network
14	David L. Harris, Stuart F. Oberman, Mark Horowitz	SRT Division Architectures and Implementations.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	skew-tolerant, Computer arithmetic, floating point units, SRT division, domino circuits
14	R. Safari, N. Narasimhamurthi, Malayappan Shridhar, Majid Ahmadi	Form Registration: A Computer Vision Approach.	ICDAR	1997	DBLP DOI BibTeX RDF	Line and Point Correspondence, Forms, Affine Invariants, Point Pattern Matching, Skew Correction
14	Hongjun Lu, Kian-Lee Tan	On Sort-Merge Algorithm for Band Joins.	IEEE Trans. Knowl. Data Eng.	1995	DBLP DOI BibTeX RDF	Band join algorithms, data skew handling, buffer allocation, database query processing
14	Vernon L. Chi	Salphasic Distribution of Clock Signals for Synchronous Systems.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	transmission line theory, loaded transmission line, printed circuit board clock planes, clock plane, phase skew, salphasic clock, synchronisation, clocks, distribution network, clock skews, synchronous systems, synchronous system, propagation delay, system clock, phase shifts, clock signals, clock signal
14	Daniel L. Palumbo	The Derivation and Experimental Verification of Clock Synchronization Theory.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	clock synchronization theory, Interactive Convergence Clock Synchronization Algorithm, Mid-Point Algorithm, clock circuitry, operating conditions, worst case failures, experimental verification, formal methods, formal verification, synchronisation, clock synchronization, clock skew, byzantine failure, proof of correctness, failure modes, timing circuits, malicious failures
14	M. V. Ramakrishna, Edgar A. Ramos	Optimal Distribution of Signatures in Signature Hashing.	IEEE Trans. Knowl. Data Eng.	1992	DBLP DOI BibTeX RDF	signature hashing, external files, single access retrieval, skew distribution, optimisation, database theory, optimization problem, file organisation, asymptotic analysis, load factor
14	Arthur F. Champernowne, Louis B. Bushard, John T. Rusterholz, John R. Schomburg	Latch-to-Latch Timing Rules.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	latch-to-latch timing rules, consecutive latch pairs, multiple skew levels, data propagation delays, multiple clock pulse widths, clock phases, logic design, synchronous systems, combinational logic, propagation delay
14	Stephen H. Unger, Chung-Jen Tan	Clocking Schemes for High-Speed Digital Systems.	IEEE Trans. Computers	1986	DBLP DOI BibTeX RDF	clock pulses, edge-triggered flip-flops, edge tolerances, one-phase clocking, delays, timing, Clocking, digital systems, skew, latches, synchronous circuits
12	Ajit Kumar, Sudhir Kumar 0002	Joint Clock Offset and Skew Estimation Based on Correlated Propagation Delays in Internet of Bio-Nano Things.	IEEE Internet Things J.	2024	DBLP DOI BibTeX RDF
12	Hamidreza Mafi, Naim Ben-Hamida, Sadok Aouini, Yvon Savaria	Digital Compensation of Timing Skew Mismatches in Time-Interleaved ADCs by Source Separation.	IEEE Trans. Instrum. Meas.	2024	DBLP DOI BibTeX RDF
12	Dengquan Li, Longsheng Wang, Yi Shen 0007, Shubin Liu, Zhangming Zhu	A Background Timing Skew Calibration for Time-Interleaved ADCs Based on Frequency Fitness Genetic Algorithm.	IEEE Trans. Instrum. Meas.	2024	DBLP DOI BibTeX RDF
12	Oguzhan Dogru, Ranjith Chiplunkar, Biao Huang 0001	Skew Filtering for Online State Estimation and Control.	IEEE Trans. Ind. Informatics	2024	DBLP DOI BibTeX RDF
12	Panpan Niu, Fei Wang, Xiangyang Wang 0001	SVD-UDWT Difference Domain Statistical Image Watermarking Using Vector Alpha Skew Gaussian Distribution.	Circuits Syst. Signal Process.	2024	DBLP DOI BibTeX RDF
12	Li Dang, Shubin Liu, Ruixue Ding, Yi Shen 0007, Zhangming Zhu	A High Accuracy and Bandwidth Digital Background Calibration Technique for Timing Skew in TI-ADCs.	IEEE Trans. Circuits Syst. I Regul. Pap.	2024	DBLP DOI BibTeX RDF
12	Lixia Cao, Cong Wang, Tonghui Wang, David Trafimow	The APP for estimating population proportion based on skew normal approximations and the Beta-Bernoulli process.	Commun. Stat. Simul. Comput.	2024	DBLP DOI BibTeX RDF
12	Haozhan Meng, X. Rong Li, Vesselin P. Jilkov	Discrete-time linear skew-Gaussian system and its recursive fixed-dimensional exact density filtering.	Autom.	2024	DBLP DOI BibTeX RDF
12	Hannes Bartz, Thomas Jerkovits, Johan Rosenkilde	Fast Kötter-Nielsen-Høholdt interpolation over skew polynomial rings and its application in coding theory.	Des. Codes Cryptogr.	2024	DBLP DOI BibTeX RDF
12	Felicitas Hörmann, Hannes Bartz	Interpolation-based decoding of folded variants of linearized and skew Reed-Solomon codes.	Des. Codes Cryptogr.	2024	DBLP DOI BibTeX RDF
12	Xiaonan Zhu, Zheng Wei, Tonghui Wang, S. T. Boris Choy, Ziwei Ma	An expectation conditional maximization algorithm for the skew-normal based stochastic frontier model.	Comput. Stat.	2024	DBLP DOI BibTeX RDF
12	Chao Shang, Jin Cao, Tong Zhu, Yinghui Zhang 0002, Ben Niu 0001, Hui Li 0006	CADFA: A Clock Skew-Based Active Device Fingerprint Authentication Scheme for Class-1 IoT Devices.	IEEE Syst. J.	2024	DBLP DOI BibTeX RDF
12	Salvatore D. Tomarchio, Luca Bagnato, Antonio Punzo	Model-based clustering using a new multivariate skew distribution.	Adv. Data Anal. Classif.	2024	DBLP DOI BibTeX RDF