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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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Found 5686 publication records. Showing 5677 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
21 | I-Chyn Wey, Lung-Hao Chang, You-Gang Chen, Shih-Hung Chang, An-Yeu Wu |
A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1074-1077, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | William Zhu 0001, Clark D. Thomborson |
Algorithms to Watermark Software Through Register Allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DRMTICS ![In: Digital Rights Management: Technologies, Issues, Challenges and Systems, First International Conference, DRMTICS 2005, Sydney, Australia, October 31 - November 2, 2005, Revised Selected Papers, pp. 180-191, 2005, Springer, 3-540-35998-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Dominik Jochinger, Franz Pichler |
A New Pseudo-Random Generator Based on Gollmann Cascades of Baker-Register-Machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCAST ![In: Computer Aided Systems Theory - EUROCAST 2005, 10th International Conference on Computer Aided Systems Theory, Las Palmas de Gran Canaria, Spain, February 7-11, 2005, Revised Selected Papers, pp. 311-316, 2005, Springer, 3-540-29002-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Hua Yang, Gang Cui, Xiaozong Yang |
Eliminating Inter-Thread Interference in Register File for SMT Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDCAT ![In: Sixth International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2005), 5-8 December 2005, Dalian, China, pp. 40-45, 2005, IEEE Computer Society, 0-7695-2405-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Tuomas Järvinen, Jarmo Takala |
Register-Based Permutation Networks for Stride Permutations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Computer Systems: Architectures, Modeling, and Simulation, Third and Fourth International Workshops, SAMOS 2003 and SAMOS 2004, Samos, Greece, July 21-23, 2003 and July 19-21, 2004, Proceedings, pp. 108-117, 2004, Springer, 3-540-22377-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Andreas Leininger, Michael Gössel, Peter Muhmenthaler |
Diagnosis of Scan-Chains by Use of a Configurable Signature Register and Error-Correcting Code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 1302-1309, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Tetsuya Sueyoshi, Hiroshi Uchida, Hans Jürgen Mattausch, Tetsushi Koide, Yosuke Mitani, Tetsuo Hironaka |
Compact 12-port multi-bank register file test-chip in 0.35µm CMOS for highly parallel processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 551-552, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Chantana Chantrapornchai, Wanlop Surakumpolthorn, Edwin Hsing-Mean Sha |
Efficient Scheduling for Design Exploration with Imprecise Latency and Register Constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing, International Conference EUC 2004, Aizu-Wakamatsu City, Japan, August 25-27, 2004, Proceedings, pp. 259-270, 2004, Springer, 3-540-22906-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Bernard Goossens |
The Instruction Register File. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PaCT ![In: Parallel Computing Technologies, 7th International Conference, PaCT 2003, Novosibirsk, Russia, September 15-19, 2003, Proceedings, pp. 467-481, 2003, Springer, 3-540-40673-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Aneesh Aggarwal, Manoj Franklin |
Energy Efficient Asymmetrically Ported Register Files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 2-7, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Jia Guo, María Jesús Garzarán, David A. Padua |
The Power of Belady?s Algorithm in Register Allocation for Long Basic Blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 16th International Workshop, LCPC 2003, College Station, TX, USA, October 2-4, 2003, Revised Papers, pp. 374-390, 2003, Springer, 3-540-21199-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Rogério Xavier de Azambuja, Luiz C. V. dos Santos |
Global scheduling and register allocation based on predicated execution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 232-235, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Marek Wróblewski, Matthias Müller 0002, Andreas Wortmann 0002, Sven Simon 0001, Wilhelm Pieper, Josef A. Nossek |
A power efficient register file architecture using master latch sharing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 393-396, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Kevin Fan, Nathan Clark, Michael L. Chu, K. V. Manjunath, Rajiv A. Ravindran, Mikhail Smelyanskiy, Scott A. Mahlke |
Systematic Register Bypass Customization for Application-Specific Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 14th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2003), 24-26 June 2003, The Hague, The Netherlands, pp. 64-74, 2003, IEEE Computer Society, 0-7695-1992-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Qiang Xu 0001, Nicola Nicolici |
On Reducing Wrapper Boundary Register Cells in Modular SOC Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 622-631, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Kelvin Lin, Jean Jyh-Jiun Shann, Chung-Ping Chung |
Code Compression by Register Operand Dependency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Interaction between Compilers and Computer Architectures ![In: 6th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-6 2002), 3 February 2002, Boston, MA, USA, pp. 91-101, 2002, IEEE Computer Society, 0-7695-1534-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Dictionary-based compression, Code compression |
21 | Yuhei Kaneko, Nobuhiko Sugino, Akinori Nishihara |
Memory allocation method for indirect addressing with an index register. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS (1) ![In: IEEE Asia Pacific Conference on Circuits and Systems 2002, APCCAS 2002, Singapore, 16-18 December 2002, pp. 199-202, 2002, IEEE, 0-7803-7690-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
21 | Eun-Jin Im, Katherine A. Yelick |
Optimizing Sparse Matrix Computations for Register Reuse in SPARSITY. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Computational Science (1) ![In: Computational Science - ICCS 2001, International Conference, San Francisco, CA, USA, May 28-30, 2001. Proceedings, Part I, pp. 127-136, 2001, Springer, 3-540-42232-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
21 | Dezsö Sima |
The Design Space of Register Renaming Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 20(5), pp. 70-83, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
21 | Thomas Bräunl |
Register-Transfer Level Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MASCOTS ![In: MASCOTS 2000, Proceedings of the 8th International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems, 29 August - 1 September 2000, San Francisco, California, USA, pp. 392-396, 2000, IEEE Computer Society, 0-7695-0728-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
21 | R. Anand, Margarida F. Jacome, Gustavo de Veciana |
Heuristic tradeoffs between latency and energy consumption in register assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Eighth International Workshop on Hardware/Software Codesign, CODES 2000, San Diego, California, USA, 2000, pp. 115-119, 2000, ACM, 1-58113-268-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
21 | Bart Mesman, Carlos A. Alba Pinto, Koen van Eijk |
Efficient Scheduling of DSP Code on Processors with Distributed Register Files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 12th International Symposium on System Synthesis, ISSS '99, Boca Raton, Florida, USA, November 1-4, 1999., pp. 100-106, 1999, ACM / IEEE Computer Society, 0-7695-0356-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
21 | Chaeryung Park, Taewhan Kim, C. L. Liu 0001 |
Register Allocation - A Hierarchical Reduction Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 19(3), pp. 269-285, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
21 | Katzalin Olcoz, Francisco Tirado |
Register Allocation with Simultaneous BIST Intrusio. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 24th EUROMICRO '98 Conference, Engineering Systems and Software for the Next Decade, 25-27 August 1998, Vesteras, Sweden, pp. 10099-10106, 1998, IEEE Computer Society, 0-8186-8646-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
21 | Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr. |
Incorporating interconnect, register, and clock distribution delays into the retiming process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(1), pp. 105-120, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
21 | Mikkel Thorup |
Structured Programs have Small Tree-Width and Good Register Allocation (Extended Abstract). ![Search on Bibsonomy](Pics/bibsonomy.png) |
WG ![In: Graph-Theoretic Concepts in Computer Science, 23rd International Workshop, WG '97, Berlin, Germany, June 18-20, 1997, Proceedings, pp. 318-332, 1997, Springer, 3-540-63757-5. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
21 | Zebo Peng, Krzysztof Kuchcinski |
Automated transformation of algorithms into register-transfer level implementations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(2), pp. 150-166, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
21 | Juin-Yeu Lu, Shiu-Kai Chin |
Generating Designs Using an Algorithmic Register Transfer Language with Formal Semantics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TPHOLs ![In: Higher Order Logic Theorem Proving and Its Applications, 7th International Workshop, Valletta, Malta, September 19-22, 1994, Proceedings, pp. 316-331, 1994, Springer, 3-540-58450-1. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
21 | Waleed Meleis, Edward S. Davidson |
Optimal local register allocation for a multiple-issue machine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Supercomputing ![In: Proceedings of the 8th international conference on Supercomputing, ICS 1994, Manchester, UK, July 11-15, 1994, pp. 107-116, 1994, ACM, 0-89791-665-4. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
21 | Tolga Soyata, Eby G. Friedman |
Retiming with non-zero clock skew, variable register, and interconnect delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 234-241, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
21 | Rainer Göttfert, Harald Niederreiter |
General Lower Bound for the Linear Complexity of the Product of Shift-Register Sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCRYPT ![In: Advances in Cryptology - EUROCRYPT '94, Workshop on the Theory and Application of Cryptographic Techniques, Perugia, Italy, May 9-12, 1994, Proceedings, pp. 223-229, 1994, Springer, 3-540-60176-7. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
21 | Rainer Göttfert, Harald Niederreiter |
On the Linear Complexity of Products of Shift-Register Sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCRYPT ![In: Advances in Cryptology - EUROCRYPT '93, Workshop on the Theory and Application of of Cryptographic Techniques, Lofthus, Norway, May 23-27, 1993, Proceedings, pp. 151-158, 1993, Springer, 3-540-57600-2. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
21 | Thomas Müller-Wipperfürth, Josef Scharinger, Franz Pichler |
FSM Shift Register Realization for Improved Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCAST ![In: Computer Aided Systems Theory - EUROCAST'93, A Selection of Papers from the Third International Workshop on Computer Aided Systems Theory, Las Palmas, Spain, February 22-26, 1993, Proceedings, pp. 254-267, 1993, Springer, 3-540-57601-0. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
21 | C. Leonard Berman |
Circuit width, register allocation, and ordered binary decision diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(8), pp. 1059-1066, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
21 | Christoph W. Keßler, Wolfgang J. Paul, Thomas Rauber |
A Randomized Heuristic Approach to Register Allocation ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLILP ![In: Programming Language Implementation and Logic Programming, 3rd International Symposium, PLILP'91, Passau, Germany, August 26-28, 1991, Proceedings, pp. 195-206, 1991, Springer, 3-540-54444-5. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
21 | Fred C. Chow, John L. Hennessy |
The Priority-Based Coloring Approach to Register Allocation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 12(4), pp. 501-536, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
21 | Arvin Park, Matthew K. Farrens |
Address compression through base register caching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 23rd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1990, Orlando, Florida, USA, November 27-29, 1990, pp. 193-199, 1990, ACM/IEEE, 0-89791-413-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP BibTeX RDF |
CPU performance, microprocessor systems, locality, bandwidth |
21 | Rajiv Gupta 0001 |
Employing Register Channels for the Exploitation of Instruction Level Parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PPoPP ![In: Proceedings of the Second ACM SIGPLAN Symposium on Princiles & Practice of Parallel Programming (PPOPP), Seattle, Washington, USA, March 14-16, 1990, pp. 118-127, 1990, ACM, 0-89791-350-7. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
21 | Bruce Jay Collings, G. Barry Hembree |
Initializing generalized feedback shift register pseudorandom number generators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 33(4), pp. 706-711, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
|
21 | Semyon Shteingart, Andrew W. Nagle, John Grason |
RTG: automatic register level test generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 22nd ACM/IEEE conference on Design automation, DAC 1985, Las Vegas, Nevada, USA, 1985., pp. 803-807, 1985, ACM, 0-8186-0635-5. The full citation details ...](Pics/full.jpeg) |
1985 |
DBLP DOI BibTeX RDF |
|
21 | Andrew Klapper |
Expected pi-Adic Security Measures of Sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SETA ![In: Sequences and Their Applications - SETA 2008, 5th International Conference, Lexington, KY, USA, September 14-18, 2008, Proceedings, pp. 219-229, 2008, Springer, 978-3-540-85911-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
algebraic feedback shift register, sequence, pseudo-randomness, security measure, feedback with carry shift register |
21 | Alodeep Sanyal, Sandip Kundu |
A Built-in Test and Characterization Method for Circuit Marginality Related Failures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 838-843, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Circuit Marginality, Pseudorandom Pattern Generator (PRPG), Multiple Input Signature Register (MISR), Fmax testing based on frequency shmoo, Built-In Self-Test (BIST), Design-for-Testability (DFT), Linear Feedback Shift Register (LFSR) |
21 | Yi-Bing Lin |
Eliminating Overflow for Large-Scale Mobility Databases in Cellular Telephone Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(4), pp. 356-370, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Cellular telephone network, database overflow, visitor location register, home location register, large-scale database |
21 | Steven R. Vegdahl |
Using Node Merging to Enhance Graph Coloring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the 1999 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), Atlanta, Georgia, USA, May 1-4, 1999, pp. 150-154, 1999, ACM, 1-58113-094-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
graph coloring, register allocation, register coalescing |
21 | Yi-Bing Lin |
Reducing location update cost in a PCS network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE/ACM Trans. Netw. ![In: IEEE/ACM Trans. Netw. 5(1), pp. 25-33, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
roaming management, visitor location register, mobility management, personal communications services, home location register |
21 | Michal Kopec |
Can Nonlinear Compactors Be Better than Linear Ones. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 44(11), pp. 1275-1282, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
built-in self-test, linear feedback shift register, signature analysis, Aliasing probability, data compaction, nonlinear feedback shift register |
21 | Josep Llosa, Mateo Valero, Eduard Ayguadé, Antonio González 0001 |
Hypernode reduction modulo scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29 - December 1, 1995, pp. 350-360, 1995, ACM / IEEE Computer Society, 0-8186-7349-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
register allocation, software pipelining, instruction scheduling, loop scheduling, register spilling |
21 | Joseph S. M. Ho, Ian F. Akyildiz |
Local Anchor Scheme for Reducing Location Tracking Costs in PCNs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MobiCom ![In: MOBICOM '95, Proceedings of the First Annual International Conference on Mobile Computing and Networking, Berkeley, CA, USA, November 13-15, 1995., pp. 181-193, 1995, ACM, 0-89791-814-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
call delivery, local anchoring, location registration, visitor location register, home location register |
21 | Svetlana P. Kartashev, Steven I. Kartashev |
Analysis and Synthesis of Dynamic Multicomputer Networks that Reconfigure into Rings, Trees, and Stars. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 36(7), pp. 823-844, 1987. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
stars?single and multirooted, Binary tree?single and multirooted, composite ring structures, reconfiguration code, reconfiguration of dynamic multicomputer networks, ring period, set of rings, shift- register theory, shift register with variable bias, single ring structures |
21 | Jacob Savir |
The Bidirectional Double Latch (BDDL). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 35(1), pp. 65-66, 1986. The full citation details ...](Pics/full.jpeg) |
1986 |
DBLP DOI BibTeX RDF |
shift register latch, shift register failure diagnostics, Design for testability, hardware overhead, LSSD |
21 | Tatsuo Higuchi 0001, Michitaka Kameyama |
Static-Hazard-Free T-Gate for Ternary Memory Element and Its Application to Ternary Counters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 26(12), pp. 1212-1221, 1977. The full citation details ...](Pics/full.jpeg) |
1977 |
DBLP DOI BibTeX RDF |
Counter based on shift register, emitter coupled logic (ECL), feedback shift register (FSR), signed ternary number representation, static-hazard-free T-gate, symmetrical modulo-M counter, synchronous and asynchronous signed ternary counter, ternary memory element, up-down counting |
20 | Roberto Baldoni, Silvia Bonomi, Michel Raynal |
Joining a Distributed Shared Memory Computation in a Dynamic Distributed System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SEUS ![In: Software Technologies for Embedded and Ubiquitous Systems, 7th IFIP WG 10.2 International Workshop, SEUS 2009, Newport Beach, CA, USA, November 16-18, 2009, Proceedings, pp. 91-102, 2009, Springer, 978-3-642-10264-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Provable guarantee, Regular register, Set object, Dynamic system, Synchronous system, Churn |
20 | Joon-Sung Yang, Nur A. Touba |
Expanding Trace Buffer Observation Window for In-System Silicon Debug through Selective Capture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 345-351, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Trace Buffer Observation Window, Two-Dimensional (2-D) Compaction, Cycling Register, Silicon Debug, MISR |
20 | Shao-Yang Wang, Rong-Guey Chang |
Code size reduction by compressing repeated instruction sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 40(3), pp. 319-331, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Repeated instruction sequence, Index table, Instruction table, Register bank, Code compression, Decompression, Instruction prefetching |
20 | Florent Bouchez, Alain Darte, Fabrice Rastello |
On the complexity of spill everywhere under SSA form. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), San Diego, California, USA, June 13-15, 2007, pp. 103-112, 2007, ACM, 978-1-59593-632-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
spill, complexity, register allocation, SSA form |
20 | Tadayoshi Enomoto, Suguru Nagayama, Nobuaki Kobayashi |
Low-Power High-Speed 180-nm CMOS Clock Drivers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 126-127, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
0.640 ns, CMOS clock drivers, register array, delay flip-flops, 251 muW, CMOS technology, power dissipation, delay time, 0.18 micron |
20 | Bin Zhang 0003, Dengguo Feng |
Multi-pass Fast Correlation Attack on Stream Ciphers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Selected Areas in Cryptography ![In: Selected Areas in Cryptography, 13th International Workshop, SAC 2006, Montreal, Canada, August 17-18, 2006 Revised Selected Papers, pp. 234-248, 2006, Springer, 978-3-540-74461-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Stream cipher, Linear feedback shift register (LFSR), Fast correlation attack, Parity-check |
20 | Tor Helleseth, Cees J. A. Jansen, Shahram Khazaei, Alexander Kholosha |
Security of Jump Controlled Sequence Generators for Stream Ciphers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SETA ![In: Sequences and Their Applications - SETA 2006, 4th International Conference, Beijing, China, September 24-28, 2006, Proceedings, pp. 141-152, 2006, Springer, 3-540-44523-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
jump register, key-stream generator, linear relations, Cryptanalysis, stream cipher, Pomaranch |
20 | Mark Goresky, Andrew Klapper |
Periodicity and Distribution Properties of Combined FCSR Sequences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SETA ![In: Sequences and Their Applications - SETA 2006, 4th International Conference, Beijing, China, September 24-28, 2006, Proceedings, pp. 334-341, 2006, Springer, 3-540-44523-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
stream cipher, pseudorandom sequence, Feedback with carry shift register |
20 | Takuya Nakaike, Tatsushi Inagaki, Hideaki Komatsu, Toshio Nakatani |
Profile-based global live-range splitting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN 2006 Conference on Programming Language Design and Implementation, Ottawa, Ontario, Canada, June 11-14, 2006, pp. 216-227, 2006, ACM, 1-59593-320-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
live-range splitting, graph coloring, register allocation |
20 | Stephen Hines, David B. Whalley, Gary S. Tyson |
Adapting compilation techniques to enhance the packing of instructions into registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2006 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2006, Seoul, Korea, October 22-25, 2006, pp. 43-53, 2006, ACM, 1-59593-543-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
instruction packing, instruction register file, compiler optimizations |
20 | Deniz Balkan, Joseph J. Sharkey, Dmitry Ponomarev 0001, Kanad Ghose |
Selective writeback: exploiting transient values for energy-efficiency and performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 37-42, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
energy-efficiency, register files |
20 | Priya Iyer, Shailendra Jain, Bryan Casper, Jason Howard |
Testing High-Speed IO Links Using On-Die Circuitry. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 807-810, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
link characterization, on-die oscilloscope, BER, register file, JTAG, IO |
20 | Alex Aletà, Josep M. Codina, Antonio González 0001, David R. Kaeli |
Demystifying on-the-fly spill code. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN 2005 Conference on Programming Language Design and Implementation, Chicago, IL, USA, June 12-15, 2005, pp. 180-189, 2005, ACM, 1-59593-056-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
register allocation, modulo scheduling, spill code |
20 | Ruo Ando, Yoshiyasu Takefuji |
Self Debugging Mode for Patch-Independent Nullification of Unknown Remote Process Infection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CANS ![In: Cryptology and Network Security, 4th International Conference, CANS 2005, Xiamen, China, December 14-16, 2005, Proceedings, pp. 85-95, 2005, Springer, 3-540-30849-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
self-debugging mode, real-time nullification, debug register, improved debug exception handler, branchIP recorder |
20 | Kevin Chen, Matthew Henricksen, William Millan, Joanne Fuller, Leonie Ruth Simpson, Ed Dawson, Hoon-Jae Lee 0001, Sang-Jae Moon |
Dragon: A Fast Word Based Stream Cipher. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICISC ![In: Information Security and Cryptology - ICISC 2004, 7th International Conference, Seoul, Korea, December 2-3, 2004, Revised Selected Papers, pp. 33-50, 2004, Springer, 3-540-26226-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
word based stream cipher, nonlinear filter, nonlinear feedback shift register |
20 | Yun-Nan Chang |
An Efficient In-Place VLSI Architecture for Viterbi Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 33(3), pp. 317-324, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
register-exchange, trace-back, ACS unit, Viterbi decoder |
20 | Manoranjan Satpathy, Rabi N. Mahapatra, Siddharth Choudhuri, Sachin V. Chitnis |
High Performance Code Generation through Lazy Activation Records. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Interaction between Compilers and Computer Architectures ![In: 7th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-7 2003), 8 February 2003, Anaheim, CA, USA, pp. 37-50, 2003, IEEE Computer Society, 0-7695-1889-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Register Utilization, Activation Records, Low Power Optimization, Embedded Systems |
20 | Christoph W. Keßler, Andrzej Bednarski |
Optimal integrated code generation for clustered VLIW architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES-SCOPES ![In: Proceedings of the 2002 Joint Conference on Languages, Compilers, and Tools for Embedded Systems & Software and Compilers for Embedded Systems (LCTES'02-SCOPES'02), Berlin, Germany, 19-21 June 2002, pp. 102-111, 2002, ACM, 1-58113-527-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
integrated code generation, space profile, dynamic programming, register allocation, instruction scheduling, instruction selection |
20 | Zoran Budimlic, Keith D. Cooper, Timothy J. Harvey, Ken Kennedy, Timothy S. Oberg, Steven W. Reeves |
Fast Copy Coalescing and Live-Range Identification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the 2002 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), Berlin, Germany, June 17-19, 2002, pp. 25-32, 2002, ACM, 1-58113-463-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
copy coalescing, live-range identification, code generation, register allocation, interference graph |
20 | Milenko Drinic, Darko Kirovski |
Behavioral synthesis via engineering change. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 39th Design Automation Conference, DAC 2002, New Orleans, LA, USA, June 10-14, 2002, pp. 18-21, 2002, ACM, 1-58113-461-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
engineering change, scheduling, transformations, register assignment |
20 | Guang Gong, Lein Harn, Huapeng Wu |
The GH Public-Key Cryptosystem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Selected Areas in Cryptography ![In: Selected Areas in Cryptography, 8th Annual International Workshop, SAC 2001 Toronto, Ontario, Canada, August 16-17, 2001, Revised Papers, pp. 284-300, 2001, Springer, 3-540-43066-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
third-order linear feedback shift register sequences over finite fields, digital signature, Public-key cryptosystem |
20 | Alexander Kholosha |
Clock-Controlled Shift Registers and Generalized Geffe Key-Stream Generator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
INDOCRYPT ![In: Progress in Cryptology - INDOCRYPT 2001, Second International Conference on Cryptology in India, Chennai, India, December 16-20, 2001, Proceedings, pp. 287-296, 2001, Springer, 3-540-43010-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
key-stream generator, clock-controlled shift register, Geffe generator, cryptography |
20 | Koen van Eijk, Bart Mesman, Carlos A. Alba Pinto, Qin Zhao, Marco Bekooij, Jef L. van Meerbergen, Jochen A. G. Jess |
Constraint analysis for code generation: basic techniques and applications in FACTS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 5(4), pp. 774-793, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
foreground memory, phase coupling, scheduling, DSP, constraint analysis, register binding |
20 | Rastislav Bodík, Rajiv Gupta 0001, Mary Lou Soffa |
Load-Reuse Analysis: Design and Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the 1999 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), Atlanta, Georgia, USA, May 1-4, 1999, pp. 64-76, 1999, ACM, 1-58113-094-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
data-flow analysis, program representations, profile-guided optimizations, register promotion |
20 | Dingchao Li, Yuji Iwahori, Tatsuya Hayashi, Naohiro Ishii |
A Spill Code Placement Framework for Code Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 11th International Workshop, LCPC'98, Chapel Hill, NC, USA, August 7-9, 1998, Proceedings, pp. 263-274, 1998, Springer, 3-540-66426-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Fine grain parallel architectures, program behavior analysis, compiler optimization, register spilling, code scheduling |
20 | Oliver Rüthing |
Optimal Code Motion in the Presence of Large Expressions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCL ![In: Proceedings of the 1998 International Conference on Computer Languages, ICCL 1998, Chicago, IL, USA, May 14-16, 1998, pp. 216-, 1998, IEEE Computer Society, 0-8186-8454-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
partial redundancy, graph theory, register allocation, graph matching, program optimization, code motion, elimination |
20 | M. Anton Ertl, Andreas Krall |
Removing Anti Dependences by Repairing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 6th International Conference, CC'96, Linköping, Sweden, April 24-26, 1996, Proceedings, pp. 33-43, 1996, Springer, 3-540-61053-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
anti dependence, instruction-level parallelism, speculative execution, repairing, register renaming |
20 | Larry Carter, Jeanne Ferrante, Susan Flynn Hummel |
Hierarchical tiling for improved superscalar performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '95, The 9th International Parallel Processing Symposium, April 25-28, 1995, Santa Barbara, California, USA, pp. 239-245, 1995, IEEE Computer Society, 0-8186-7074-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
hierarchical tiling, superscalar performance, inner-loop performance, compiler phases, scalar replacement, storage mapping, superscalar pipelined processors, automatic preprocessor, performance evaluation, parallel processing, parallelization, message passing, message passing, register allocation, instruction scheduling, optimizing compiler, data locality, archival storage |
20 | Jay K. Adams, John Alan Miller, Donald E. Thomas |
Execution-time profiling for multiple-process behavioral synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 144-149, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
execution-time profiling, multiple-process behavioral synthesis, back-annotating, source description, behavioral simulation model, annotated behavioral simulation, high level synthesis, high-level synthesis, timing, timing, logic CAD, digital simulation, circuit analysis computing, hardware design, software profiling, register-transfer level model |
20 | Gerd Maderlechner, Helmut Mayer 0001 |
Conversion of high level information from scanned maps into geographic information systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDAR ![In: Third International Conference on Document Analysis and Recognition, ICDAR 1995, August 14 - 15, 1995, Montreal, Canada. Volume I, pp. 253-256, 1995, IEEE Computer Society, 0-8186-7128-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
frame based representation, high level information conversion, scanned maps, land register maps, feedback cycles, legal information extraction, parcels, boundary stones, topographic information, feature extraction, geographic information systems, geographic information systems, knowledge representation, frames, semantic networks, semantic networks, cartography, explicit knowledge, automatic extraction, law administration |
20 | Peter Dahl, Matthew T. O'Keefe |
Reducing memory traffic with CRegs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30 - December 2, 1994, pp. 100-104, 1994, ACM / IEEE Computer Society, 0-89791-707-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
CRegs, ambiguous alias, live range, graph coloring, register allocation |
20 | Preston Briggs, Linda Torczon |
An Efficient Representation for Sparse Sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LOPLAS ![In: LOPLAS 2(1-4), pp. 59-69, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
compiler implementation, set representations, register allocation, set operations |
20 | Ajay Kumar Verma, Philip Brisk, Paolo Ienne |
Fast, quasi-optimal, and pipelined instruction-set extensions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008, pp. 334-339, 2008, IEEE, 978-1-4244-1921-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
20 | Yang Xiao 0001, Hui Chen 0001, Hsiao-Hwa Chen, Bo Sun 0001, C. L. Philip Chen |
Optimal Utilization and Effects of Inaccurate Estimation in Mobile Database Failure Restoration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Wirel. Commun. ![In: IEEE Trans. Wirel. Commun. 6(6), pp. 2086-2095, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Guillermo Payá Vayá, Javier Martín-Langerwerf, Piriya Taptimthong, Peter Pirsch |
Design Space Exploration of Media Processors: A Parameterized Scheduler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSAMOS ![In: Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2007), Samos, Greece, July 16-19, 2007, pp. 41-49, 2007, IEEE, 1-4244-1058-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Gregory V. Chockler, Rachid Guerraoui, Idit Keidar |
Amnesic Distributed Storage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DISC ![In: Distributed Computing, 21st International Symposium, DISC 2007, Lemesos, Cyprus, September 24-26, 2007, Proceedings, pp. 139-151, 2007, Springer, 978-3-540-75141-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
20 | Xiaotong Zhuang, Santosh Pande |
Parallelizing load/stores on dual-bank memory embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 5(3), pp. 613-657, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
memory bank allocation, parallel load/stores, profile driven optimization, DSP architectures |
20 | Ge Jin, Sang-Joon Lee, James K. Hahn, Steven Bielamowicz, Rajat Mittal 0002, Raymond Walsh |
3D Surface Reconstruction and Registration for Image Guided Medialization Laryngoplasty. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVC (1) ![In: Advances in Visual Computing, Second International Symposium, ISVC 2006, Lake Tahoe, NV, USA, November 6-8, 2006 Proceedings, Part I, pp. 761-770, 2006, Springer, 3-540-48628-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
3D Reconstruction, Registration, Image Guided Surgery |
20 | Lisa Higham, Colette Johnen |
Relationships between communication models in networks using atomic registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Ryan Collins, Fernando Alegre, Xiaotong Zhuang, Santosh Pande |
Compiler assisted dynamic management of registers for network processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
20 | Chang-Jin Choi, Sang-Hun Yoon, Jong-Wha Chong, Shouyin Liu |
A New Low-Power and High Speed Viterbi Decoder Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICUCT ![In: Ubiquitous Convergence Technology, First International Conference, ICUCT 2006, Jeju Island, Korea, December 5-6, 2006, Revised Selected Papers, pp. 283-291, 2006, Springer, 978-3-540-71788-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
RE-exchange, low-power, look-ahead, viterbi |
20 | Yongxiang Liu, Gokhan Memik, Glenn Reinman |
Reducing the Energy of Speculative Instruction Schedulers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 641-646, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Lei Wang 0003 |
Error-tolerance memory Microarchitecture via Dynamic Multithreading. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 179-184, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Hongbo Rong, Alban Douillet, Ramaswamy Govindarajan, Guang R. Gao |
Code Generation for Single-Dimension Software Pipelining of Multi-Dimensional Loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 20-24 March 2004, San Jose, CA, USA, pp. 175-188, 2004, IEEE Computer Society, 0-7695-2102-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Byoungro So, Mary W. Hall |
Increasing the Applicability of Scalar Replacement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CC ![In: Compiler Construction, 13th International Conference, CC 2004, Held as Part of the Joint European Conferences on Theory and Practice of Software, ETAPS 2004, Barcelona, Spain, March 29 - April 2, 2004, Proceedings, pp. 185-201, 2004, Springer, 3-540-21297-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Solomon W. Golomb, Pey-Feng Lee |
Which Irreducible Polynomials Divide Trinomials over GF(2)? ![Search on Bibsonomy](Pics/bibsonomy.png) |
SETA ![In: Sequences and Their Applications - SETA 2004, Third International Conference, Seoul, Korea, October 24-28, 2004, Revised Selected Papers, pp. 414-424, 2004, Springer, 3-540-26084-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Wenlong Li, Haibo Lin, Yu Chen, Zhizhong Tang |
Increasing Software-Pipelined Loops in the Itanium-Like Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPA ![In: Parallel and Distributed Processing and Applications, Second InternationalSymposium, ISPA 2004, Hong Kong, China, December 13-15, 2004, Proceedings, pp. 947-951, 2004, Springer, 3-540-24128-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Dmitry Ponomarev 0001, Gurhan Kucuk, Oguz Ergin, Kanad Ghose |
Reducing Datapath Energy through the Isolation of Short-Lived Operands. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 12th International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), 27 September - 1 October 2003, New Orleans, LA, USA, pp. 258-268, 2003, IEEE Computer Society, 0-7695-2021-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Peter Suaris, Dongsheng Wang 0012, Pei-Ning Guo, Nan-Chi Chou |
A physical retiming algorithm for field programmable gate arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 247, 2003, ACM, 1-58113-651-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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