Search results for "subthreshold"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
10	Jennifer Blain Christen, Andreas G. Andreou	A Self-Biased Operational Transconductance Amplifier in 0.18 micron 3D SOI-CMOS.	ISCAS	2007	DBLP DOI BibTeX RDF
10	Volkan Kursun, Sherif A. Tawfik, Zhiyu Liu	Leakage-Aware Design of Nanometer SoC.	ISCAS	2007	DBLP DOI BibTeX RDF
10	Paulo F. Butzen, André Inácio Reis, Chris H. Kim, Renato P. Ribas	Modeling and estimating leakage current in series-parallel CMOS networks.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	leakage current modeling, static power dissipation, CMOS gates
10	Nigel Drego, Anantha P. Chandrakasan, Duane S. Boning	A Test-Structure to Efficiently Study Threshold-Voltage Variation in Large MOSFET Arrays.	ISQED	2007	DBLP DOI BibTeX RDF
10	Byunghee Choi, Youngsoo Shin	Lookup Table-Based Adaptive Body Biasing of Multiple Macros.	ISQED	2007	DBLP DOI BibTeX RDF
10	Kazuki Nakada, Keiji Miura, Hatsuo Hayashi	Theoretical Analysis of Synchronization Phenomena in Two Pulse-Coupled Resonate-and-Fire Neurons.	IJCNN	2007	DBLP DOI BibTeX RDF
10	Saraju P. Mohanty, Elias Kougianos	Simultaneous Power Fluctuation and Average Power Minimization during Nano-CMOS Behavioral Synthesis.	VLSI Design	2007	DBLP DOI BibTeX RDF
10	Jyi-Tsong Lin, Yi-Chuen Eng, Tai-Yi Lee, Kao-Cheng Lin	Analysis of Si-body thickness variation for a new 40 nm gate length bFDSOI.	VLSI Design	2007	DBLP DOI BibTeX RDF
10	Yuanlin Lu, Vishwani D. Agrawal	Statistical Leakage and Timing Optimization for Submicron Process Variation.	VLSI Design	2007	DBLP DOI BibTeX RDF
10	Jie Gu 0003, Sachin S. Sapatnekar, Chris H. Kim	Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift.	DAC	2007	DBLP DOI BibTeX RDF
10	Tao Li, Zhiping Yu	Statistical Analysis of Full-Chip Leakage Power Considering Junction Tunneling Leakage.	DAC	2007	DBLP DOI BibTeX RDF
10	Krisztina Szalisznyó	Role of hyperpolarization-activated conductances in the lateral superior olive: A modeling study.	J. Comput. Neurosci.	2006	DBLP DOI BibTeX RDF	hyperpolarization activated currents, LSO, interaural sound intensity difference, rate code, dynamic width, type I neuron, type II neuron
10	Renaud Jolivet, Alexander Rauch, Hans-Rudolf Lüscher, Wulfram Gerstner	Predicting spike timing of neocortical pyramidal neurons by simple threshold models.	J. Comput. Neurosci.	2006	DBLP DOI BibTeX RDF	Spike Response Model, Stochastic input, Spike-timing reliability, Predicting spike timing, Adapting threshold
10	Jae-Joon Kim, Kaushik Roy 0001	A Leakage-Tolerant Low-Swing Circuit Style in Partially Depleted Silicon-on-Insulator CMOS Technologies.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
10	Rajeev R. Rao, Anirudh Devgan, David T. Blaauw, Dennis Sylvester	Analytical yield prediction considering leakage/performance correlation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
10	Saibal Mukhopadhyay, Keunwoo Kim, Ching-Te Chuang, Kaushik Roy 0001	Modeling and Analysis of Leakage Currents in Double-Gate Technologies.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
10	Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy 0001	Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
10	Kaviraj Chopra, Sarma B. K. Vrudhula	Efficient Symbolic Algorithms for Computing the Minimum and Bounded Leakage States.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
10	Preetham Lakshmikanthan, Adrian Nunez	A Novel Methodology to Reduce Leakage Power in CMOS Complementary Circuits.	PATMOS	2006	DBLP DOI BibTeX RDF
10	Se Hun Kim, Vincent John Mooney	Sleepy Keeper: a New Approach to Low-leakage Power VLSI Design.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
10	Behnam Amelifard, Farzan Fallah, Massoud Pedram	Reducing the sub-threshold and gate-tunneling leakage of SRAM cells using Dual-Vt and Dual-Tox assignment.	DATE	2006	DBLP DOI BibTeX RDF
10	Qikai Chen, Saibal Mukhopadhyay, Aditya Bansal, Kaushik Roy 0001	Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design.	DATE	2006	DBLP DOI BibTeX RDF
10	Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy 0001	Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies.	DATE	2006	DBLP DOI BibTeX RDF
10	S. H. Rasouli, Amir Amirabadi, A. Seyedi, Ali Afzali-Kusha	Double edge triggered Feedback Flip-Flop in sub 100NM technology.	ASP-DAC	2006	DBLP DOI BibTeX RDF
10	Hyung-Ock Kim, Youngsoo Shin	Analysis and optimization of gate leakage current of power gating circuits.	ASP-DAC	2006	DBLP DOI BibTeX RDF
10	Sheng-Chih Lin, Kaustav Banerjee	An electrothermally-aware full-chip substrate temperature gradient evaluation methodology for leakage dominant technologies with implications for power estimation and hot-spot management.	ICCAD	2006	DBLP DOI BibTeX RDF
10	Baozhen Yu, Michael L. Bushnell	A novel dynamic power cutoff technique (DPCT) for active leakage reduction in deep submicron CMOS circuits.	ISLPED	2006	DBLP DOI BibTeX RDF	power cutoff, standby current, stacking, leakage current, dynamic power
10	Samuel Rodríguez, Bruce L. Jacob	Energy/power breakdown of pipelined nanometer caches (90nm/65nm/45nm/32nm).	ISLPED	2006	DBLP DOI BibTeX RDF	nanometer design, pipelined caches, cache design
10	Omer Can Akgun, Yusuf Leblebici	Weak inversion performance of CMOS and DCVSPG logic families in sub-300 mV range.	ISCAS	2006	DBLP DOI BibTeX RDF
10	Kazuki Nakada, Jun Igarashi, A. Tetsuya, Hatsuo Hayashi	Noise Effects on Performance of Signal Detection in an Analog VLSI Resonate-And Fire Neuron.	ISCAS	2006	DBLP DOI BibTeX RDF
10	Edward K. Lee 0002, Eusebiu Matei, Ravi S. Ananth	A 0.9 V rail-to-rail constant gm amplifier for implantable biomedical applications.	ISCAS	2006	DBLP DOI BibTeX RDF
10	Volkan Kursun, Zhiyu Liu	Wide temperature spectrum low leakage dynamic circuit technique for sub-65nm CMOS technologies.	ISCAS	2006	DBLP DOI BibTeX RDF
10	Kaoru Nakada	Robustness in binary cellular non-linear networks analog VLSI resonate-and-fire neuron.	ISCAS	2006	DBLP DOI BibTeX RDF
10	Bruno Andò, Salvatore Baglio, Vincenzo Sacco, Adi R. Bulsara, Visarath In, Andy Kho, Antonio Palacios, Patrick Longhini	Dynamic cooperative behavior in a coupled-core fluxgate magnetometer.	ISCAS	2006	DBLP DOI BibTeX RDF
10	Micah G. O'Halloran, Rahul Sarpeshkar	An analog storage cell with 5e-/sec leakage.	ISCAS	2006	DBLP DOI BibTeX RDF
10	Carlos Muñiz-Montero, Alejandro Díaz-Sánchez, Ramón González Carvajal	Offset compensation using unbalanced polarization.	ISCAS	2006	DBLP DOI BibTeX RDF
10	Jonathan Tapson	Supercritical stability in a sonar receiver circuit.	ISCAS	2006	DBLP DOI BibTeX RDF
10	Jin He 0003, Xing Zhang 0002, Ganggang Zhang, Yangyuan Wang	A Carrier-Based Analytic Model for Undoped (Lightly Doped) Ultra-Thin-Body Silicon-on-Insulator (UTB-SOI) MOSFETs.	ISQED	2006	DBLP DOI BibTeX RDF
10	Ashok Patel, Bart Kosko	Mutual-Information Noise Benefits in Brownian Models of Continuous and Spiking Neurons.	IJCNN	2006	DBLP DOI BibTeX RDF
10	M. Jagadesh Kumar, Ali A. Orouji	Phase Change Memory Faults.	VLSI Design	2006	DBLP DOI BibTeX RDF
10	Chuen M. Tan, Masud H. Chowdhury	Simultaneous Analysis of Capacitive Coupling and Leakage Noise in Nanometer Scale Circuits.	APCCAS	2006	DBLP DOI BibTeX RDF
10	Hong Luo, Huazhong Yang, Rong Luo	Accurate and Fast Estimation of Junction Band-to-Band Leakage in Nanometer-Scale MOSFET.	APCCAS	2006	DBLP DOI BibTeX RDF
10	Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar	Gate oxide leakage and delay tradeoffs for dual-Tox circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
10	Benton H. Calhoun, Denis C. Daly, Naveen Verma, Daniel F. Finchelstein, David D. Wentzloff, Alice Wang, Seong-Hwan Cho, Anantha P. Chandrakasan	Design Considerations for Ultra-Low Energy Wireless Microsensor Nodes.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	wireless sensor networks, low-power design, Integrated circuits, energy-aware systems
10	Dongwoo Lee, David T. Blaauw, Dennis Sylvester	Static leakage reduction through simultaneous Vt/Tox and state assignment.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
10	Siva G. Narendra	Challenges and design choices in nanoscale CMOS.	ACM J. Emerg. Technol. Comput. Syst.	2005	DBLP DOI BibTeX RDF	nanoscale, process variation, CMOS, leakage power
10	Máté Lengyel, Zsófia Huhn, Péter Érdi	Computational theories on the function of theta oscillations.	Biol. Cybern.	2005	DBLP DOI BibTeX RDF
10	Rajeev R. Rao, David T. Blaauw, Dennis Sylvester, Anirudh Devgan	Modeling and Analysis of Parametric Yield under Power and Performance Constraints.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	G.4.g Reliability and robustness, B.7 Integrated Circuits, Fault-Tolerance
10	Sung-Bae Park	DLV (Deep Low Voltage): Circuits and Devices.	PATMOS	2005	DBLP DOI BibTeX RDF
10	Valeriu Beiu, Asbjørn Djupdal, Snorre Aunet	Ultra Low-Power Neural Inspired Addition: When Serial Might Outperform Parallel Architectures.	IWANN	2005	DBLP DOI BibTeX RDF
10	Saibal Mukhopadhyay, Swarup Bhunia, Kaushik Roy 0001	Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits.	DATE	2005	DBLP DOI BibTeX RDF
10	Yingmin Li, David M. Brooks, Zhigang Hu, Kevin Skadron	Performance, Energy, and Thermal Considerations for SMT and CMP Architectures.	HPCA	2005	DBLP DOI BibTeX RDF
10	Jun Liu, Zhengguo Lou, Guang Li 0001	Effect of Noises on Two-Layer Hodgkin-Huxley Neuronal Network.	ICNC (1)	2005	DBLP DOI BibTeX RDF
10	Leyla Nazhandali, Michael Minuth, Bo Zhai, Javin Olson, Todd M. Austin, David T. Blaauw	A second-generation sensor network processor with application-driven memory optimizations and out-of-order execution.	CASES	2005	DBLP DOI BibTeX RDF	sensor network, energy efficiency, microprocessor, memory organization
10	Andrew B. Kahng, Swamy Muddu, Puneet Sharma	Defocus-aware leakage estimation and control.	ISLPED	2005	DBLP DOI BibTeX RDF	ACLV, yield, leakage, lithography
10	Amit Agarwal 0001, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy 0001	Effectiveness of low power dual-Vt designs in nano-scale technologies under process parameter variations.	ISLPED	2005	DBLP DOI BibTeX RDF	process variation, yield, leakage, dual-Vt, metal gate
10	Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya	Analog CMOS implementation of a neuromorphic oscillator with current-mode low-pass filters.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
10	Paul Beckett	Low-power spatial computing using dynamic threshold devices.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
10	Paul Beckett, Seth Copen Goldstein	Why area might reduce power in nanoscale CMOS.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
10	Giuseppe de Vita, Giuseppe Iannaccone	Ultra low power RF section of a passive microwave RFID transponder in 0.35µm BiCMOS.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
10	Jihyun Lee, Yong-Bin Kim	ASLIC: A Low Power CMOS Analog Circuit Design Automation.	ISQED	2005	DBLP DOI BibTeX RDF
10	Carlos Aguirre, Doris Campos, Pedro Pascual, Eduardo Serrano	Neuronal Behavior with Sub-threshold Oscillations and Spiking/Bursting Activity Using a Piecewise Linear Two-Dimensional Map.	ICANN (1)	2005	DBLP DOI BibTeX RDF
10	Yu-Shiang Lin, Dennis Sylvester	A New Asymmetric Skewed Buffer Design for Runtime Leakage Power Reduction.	VLSI Design	2005	DBLP DOI BibTeX RDF
10	Hongliang Chang, Sachin S. Sapatnekar	Full-chip analysis of leakage power under process variations, including spatial correlations.	DAC	2005	DBLP DOI BibTeX RDF
10	Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hamid Mahmoodi-Meimand, Kaushik Roy 0001	A novel synthesis approach for active leakage power reduction using dynamic supply gating.	DAC	2005	DBLP DOI BibTeX RDF
10	Martin St-Hilaire, André Longtin	Comparison of Coding Capabilities of Type I and Type II Neurons.	J. Comput. Neurosci.	2004	DBLP DOI BibTeX RDF	Type I neuron, Type II neuron, Morris Lecar model, electric fish, bifurcation theory, information theory, noise, neural coding, phase locking
10	Jianfeng Feng, David Brown 0004	Decoding Input Signals in Time Domain - A Model Approach.	J. Comput. Neurosci.	2004	DBLP DOI BibTeX RDF	the integrate-and-fire model, the Hodgkin-Huxley model, input frequency, tuning curves, decoding
10	Domenik Helms, Eike Schmidt, Wolfgang Nebel	Leakage in CMOS Circuits - An Introduction.	PATMOS	2004	DBLP DOI BibTeX RDF
10	Ashish Srivastava, Dennis Sylvester, David T. Blaauw	Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design.	DATE	2004	DBLP DOI BibTeX RDF
10	Yingmin Li, Dharmesh Parikh, Yan Zhang 0028, Karthik Sankaranarayanan, Mircea R. Stan, Kevin Skadron	State-Preserving vs. Non-State-Preserving Leakage Control in Caches.	DATE	2004	DBLP DOI BibTeX RDF
10	Dongwoo Lee, Harmander Deogun, David T. Blaauw, Dennis Sylvester	Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization.	DATE	2004	DBLP DOI BibTeX RDF
10	Saumil Shah, Kanak Agarwal, Dennis Sylvester	A New Threshold Voltage Assignment Scheme for Runtime Leakage Reduction in On-Chip Repeaters.	ICCD	2004	DBLP DOI BibTeX RDF
10	Francisco Serra-Graells, Xavier Redondo	Exact design of all-MOS log filters.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
10	Nhan Nguyen, Chris Winstead, Vincent C. Gaudet, Christian Schlegel	A 0.8V CMOS analog decoder for an (8, 4, 4) extended Hamming code.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
10	Daniel J. Allen, Angelo W. Pereira, Paul E. Hasler	A programmable coefficient continuous-time A/D Delta-Sigma modulator.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
10	Seiichiro Fujii, Toshinori Sato	Non-uniform Set-Associative Caches for Power-Aware Embedded Processors.	EUC	2004	DBLP DOI BibTeX RDF
10	Phillip Chin, Charles A. Zukowski, George Gristede, Stephen V. Kosonocky	Characterization of logic circuit techniques for high leakage CMOS technologies.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	monotonic logic, low power, leakage current
10	Navid Azizi, Farid N. Najm	An Asymmetric SRAM Cell to Lower Gate Leakage.	ISQED	2004	DBLP DOI BibTeX RDF
10	Kaviraj Chopra, Sarma B. K. Vrudhula, Sarvesh Bhardwaj	Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic.	VLSI Design	2004	DBLP DOI BibTeX RDF
10	David D. Wentzloff, Benton H. Calhoun, Rex Min, Alice Wang, Nathan Ickes, Anantha P. Chandrakasan	Design Considerations for Next Generation Wireless Power-Aware Microsensor Nodes.	VLSI Design	2004	DBLP DOI BibTeX RDF
10	Kaviraj Chopra, Sarma B. K. Vrudhula	Implicit pseudo boolean enumeration algorithms for input vector control.	DAC	2004	DBLP DOI BibTeX RDF	power, CMOS, SAT, binary decision diagrams, leakage, symbolic methods
10	Saibal Mukhopadhyay, Cassondra Neau, R. T. Cakici, Amit Agarwal 0001, Chris H. Kim, Kaushik Roy 0001	Gate leakage reduction for scaled devices using transistor stacking.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
10	Heather Hanson, M. S. Hrishikesh, Vikas Agarwal, Stephen W. Keckler, Doug Burger	Static energy reduction techniques for microprocessor caches.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
10	Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang	Timing constraints for domino logic gates with timing-dependent keepers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
10	Mohab Anis, Shawki Areibi, Mohamed I. Elmasry	Design and optimization of multithreshold CMOS (MTCMOS) circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
10	José Luis Peña	Binaural processing in the synthesis of auditory spatial receptive fields.	Biol. Cybern.	2003	DBLP DOI BibTeX RDF
10	Frank Honoré, Benton H. Calhoun, Anantha P. Chandrakasan	Power-aware architectures and circuits for FPGA-based signal processing.	FPGA	2003	DBLP DOI BibTeX RDF
10	Emrah Acar, Anirudh Devgan, Rahul M. Rao, Ying Liu, Haihua Su, Sani R. Nassif, Jeffrey L. Burns	Leakage and leakage sensitivity computation for combinational circuits.	ISLPED	2003	DBLP DOI BibTeX RDF	iddq analysis, sensitivity, power estimation, leakage power
10	Timothy K. Horiuchi, Ralph Etienne-Cummings	A time-series processor for sonar mapping and novelty detection.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
10	Debasis Samanta, Ajit Pal	Synthesis of Dual-VT Dynamic CMOS Circuits.	VLSI Design	2003	DBLP DOI BibTeX RDF	nora logic, unate decomposition, low power, Logic synthesis, high performance, leakage power, domino logic, dynamic circuits, dual-VT
10	Dongwoo Lee, Wesley Kwong, David T. Blaauw, Dennis Sylvester	Analysis and minimization techniques for total leakage considering gate oxide leakage.	DAC	2003	DBLP DOI BibTeX RDF
10	Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang	Noise constrained transistor sizing and power optimization for dual Vst domino logic.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
10	Steve Dropsho, Volkan Kursun, David H. Albonesi, Sandhya Dwarkadas, Eby G. Friedman	Managing static leakage energy in microprocessor functional units.	MICRO	2002	DBLP DOI BibTeX RDF
10	Chris H. Kim, Kaushik Roy 0001	Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors.	ISLPED	2002	DBLP DOI BibTeX RDF
10	Trond Ytterdal, Snorre Aunet	Compact low-voltage self-calibrating digital floating-gate CMOS logic circuits.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
10	Roman Genov, Gert Cauwenberghs	Charge-based MOS correlated double sampling comparator and folding circuit.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
10	Masakazu Yagi, Tadashi Shibata	An associative-processor-based mixed signal system for robust grayscale image recognition.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
10	Christopher D. Salthouse, Rahul Sarpeshkar	A micropower band-pass filter for use in bionic ears.	ISCAS (5)	2002	DBLP DOI BibTeX RDF
10	Adrian M. Ionescu, V. Pott, R. Fritschi, Kaustav Banerjee, Michel J. Declercq, Philippe Renaud, C. Hibert, Philippe Flückiger, G. A. Racine	Modeling and Design of a Low-Voltage SOI Suspended-Gate MOSFET (SG-MOSFET) with a Metal-over-Gate Architecture.	ISQED	2002	DBLP DOI BibTeX RDF
10	Wenjie Jiang, Vivek Tiwari, Erik de la Iglesia, Amit Sinha	Topological Analysis for Leakage Prediction of Digital Circuits.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF