Search results for "cores"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
29	Chiou-Kou Tung, Shao-Hui Shieh, Yu-Cherng Hung, Ming-Chien Tsai	High-Performance Low-Power Full-Swing Full Adder Cores with Output Driving Capability.	APCCAS	2006	DBLP DOI BibTeX RDF
29	Peter Hallschmid, Steven J. E. Wilton	Routing architecture optimizations for high-density embedded programmable IP cores.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
29	Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda	Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores.	MTV	2005	DBLP DOI BibTeX RDF
29	Roman L. Lysecky, Frank Vahid	A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning.	DATE	2005	DBLP DOI BibTeX RDF
29	Yana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo	Straight Method for Reallocation of Complex Cores by Dynamic Reconfiguration in Virtex II FPGAs.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
29	Holger Lange, Andreas Koch 0001	HW/SW Co-design by Automatic Embedding of Complex IP Cores.	FPL	2004	DBLP DOI BibTeX RDF
29	Kwan-Hee Yoo, Jong-Sung Ha	An Effective Modeling of Single Cores Prostheses Using Geometric Techniques.	International Conference on Computational Science	2004	DBLP DOI BibTeX RDF
29	Jeff Young, Ron Sass	FERP Interface and Interconnect Cores for Stream Processing Applications.	EUC	2004	DBLP DOI BibTeX RDF
29	Yuejian Wu, Paul N. MacDonald	Testing ASICs with multiple identical cores.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
29	Subhayu Basu, Indranil Sengupta 0001, Dipanwita Roy Chowdhury, Sudipta Bhawmik	An Integrated Approach to Testing Embedded Cores and Interconnects Using Test Access Mechanism (TAM) Switch.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	TAM switch, system-on-chip, interconnect testing
29	Madhu K. Iyer, Kwang-Ting Cheng	Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs.	VTS	2002	DBLP DOI BibTeX RDF
29	Mohamed M. Hafed, Gordon W. Roberts	Test and Evaluation of Multiple Embedded Mixed-Signal Test Cores.	ITC	2002	DBLP DOI BibTeX RDF
29	Antonis M. Paschalis, Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Yervant Zorian	An Effective BIST Architecture for Fast Multiplier Cores.	DATE	1999	DBLP DOI BibTeX RDF
29	Ken Batcher, Christos A. Papachristou	Instruction Randomization Self Test For Processor Cores.	VTS	1999	DBLP DOI BibTeX RDF
29		Testing Embedded Cores.	IEEE Des. Test Comput.	1997	DBLP DOI BibTeX RDF
28	Stephen S. Pawlowski	Exascale science: the next frontier in high performance computing.	ICS	2010	DBLP DOI BibTeX RDF	exascale systems, memory and storage bandwidth, millions of cores, software scalability, system resiliency, power consumption
28	Vignesh T. Ravi, Wenjing Ma, David Chiu 0001, Gagan Agrawal	Compiler and runtime support for enabling generalized reduction computations on heterogeneous parallel configurations.	ICS	2010	DBLP DOI BibTeX RDF	dynamic work distribution, generalized reductions, multi-cores, GPGPU, heterogeneous systems
28	M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt	Accelerating critical section execution with asymmetric multi-core architectures.	ASPLOS	2009	DBLP DOI BibTeX RDF	heterogeneous cores, parallel programming, cmp, multi-core, locks, critical sections
28	Sudarshan Bahukudumbi, Sule Ozev, Krishnendu Chakrabarty, Vikram Iyengar	AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs.	ASP-DAC	2007	DBLP DOI BibTeX RDF	mixed-signal cores, wafer-level defect screening, packaging cost reduction, big-D/small-A mixed-signal system-on-chip designs, mixed-signal SoC, consumer electronics market, wafer-level testing, correlation-based signature analysis, low-cost digital testers, generic cost model, mixed-signal test, digital logic, test cost reduction
28	Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki	CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	SoC test control, TAPed cores, P1500 wrappers, test access mechanism, I/O bandwidth
28	Serafín Olcoz, Ana Castellvi, Maria Garcia, Jose Angel Gomez	Static Analysis Tools for Soft-Core Reviews and Audits.	DATE	1998	DBLP DOI BibTeX RDF	Soft-Cores, management, analysis, VHDL
28	Guihai Yan, Xiaoyao Liang, Yinhe Han 0001, Xiaowei Li 0001	Leveraging the core-level complementary effects of PVT variations to reduce timing emergencies in multi-core processors.	ISCA	2010	DBLP DOI BibTeX RDF	complimentary effects, delay sensor, pvt variations, timing emergency, thread migration
28	Abhishek Udupa, R. Govindarajan, Matthew J. Thazhuthaveetil	Synergistic execution of stream programs on multicores with accelerators.	LCTES	2009	DBLP DOI BibTeX RDF	CUDAa, partitioning, software pipelining, stream programming, GPU programming
28	Moinuddin K. Qureshi	Adaptive Spill-Receive for robust high-performance caching in CMPs.	HPCA	2009	DBLP DOI BibTeX RDF
28	Jungseob Lee, Nam Sung Kim	Optimizing total power of many-core processors considering voltage scaling limit and process variations.	ISLPED	2009	DBLP DOI BibTeX RDF	voltage and frequency scaling, process variations, parallel applications, many-core processor
28	Björn Saballus, Thomas Fuhrmann	Maintaining reference graphs of globally accessible objects in fully decentralized distributed systems.	HPDC	2009	DBLP DOI BibTeX RDF	globally accessible objects, single system image, object migration
28	Brian M. Rogers, Anil Krishna, Gordon B. Bell, Ken V. Vu, Xiaowei Jiang, Yan Solihin	Scaling the bandwidth wall: challenges in and avenues for CMP scaling.	ISCA	2009	DBLP DOI BibTeX RDF	analytical model, memory bandwidth, chip multi-processor
28	Jungseob Lee, Nam Sung Kim	Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating.	DAC	2009	DBLP DOI BibTeX RDF	multicore processor, DVFS, power gating
28	Bogdan F. Romanescu, Daniel J. Sorin	Core cannibalization architecture: improving lifetime chip performance for multicore processors in the presence of hard faults.	PACT	2008	DBLP DOI BibTeX RDF	lifetime performance, fault tolerance, reliability, multicore
28	Haitham Akkary, Komal Jothi, Renjith Retnamma, Satyanarayana Nekkalapu, Doug Hall, Shahrokh Shahidzadeh	On the potential of latency tolerant execution in speculative multithreading.	IFMT	2008	DBLP DOI BibTeX RDF	latency-tolerant architectures, chip multiprocessors, speculative multithreading, many-core processors
28	Jeffery A. Brown, Dean M. Tullsen	The shared-thread multiprocessor.	ICS	2008	DBLP DOI BibTeX RDF	chip multiprocessors, simultaneous multithreading
28	James Laudon, Lawrence Spracklen	The Coming Wave of Multithreaded Chip Multiprocessors.	Int. J. Parallel Program.	2007	DBLP DOI BibTeX RDF	performance, parallel programming, multithreading, Chip multiprocessing
28	Hongtao Zhong, Steven A. Lieberman, Scott A. Mahlke	Extending Multicore Architectures to Exploit Hybrid Parallelism in Single-thread Applications.	HPCA	2007	DBLP DOI BibTeX RDF
28	Bryan Veal, Annie P. Foong	Performance scalability of a multi-core web server.	ANCS	2007	DBLP DOI BibTeX RDF	network protocol stacks, scalability, load balancing, networks, parallelism, web servers, cache hierarchies
28	Pavel A. Dmitriev, Carl Lagoze	Mining Generalized Graph Patterns Based on User Examples.	ICDM	2006	DBLP DOI BibTeX RDF
28	Jared C. Smolens, Brian T. Gold, Babak Falsafi, James C. Hoe	Reunion: Complexity-Effective Multicore Redundancy.	MICRO	2006	DBLP DOI BibTeX RDF
28	Pedro C. Diniz, Gokul Govindu	Design of a Field-Programmable Dual-Precision Floating-Point Arithmetic Unit.	FPL	2006	DBLP DOI BibTeX RDF
28	Noel Eisley, Vassos Soteriou, Li-Shiuan Peh	High-level power analysis for multi-core chips.	CASES	2006	DBLP DOI BibTeX RDF	simulation, chip multiprocessor (CMP), multi-core, power analysis, system-on-a-chip (SoC)
28	Vasileios Liaskovitis, Shimin Chen, Phillip B. Gibbons, Anastassia Ailamaki, Guy E. Blelloch, Babak Falsafi, Limor Fix, Nikos Hardavellas, Michael Kozuch, Todd C. Mowry, Chris Wilkerson	Parallel depth first vs. work stealing schedulers on CMP architectures.	SPAA	2006	DBLP DOI BibTeX RDF	scheduling, caches, chip multiprocessors
28	Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty	A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs.	ICCD	2005	DBLP DOI BibTeX RDF
28	Özgün Paker, Jens Sparsø, Niels Haandbæk, Mogens Isager, Lars Skovby Nielsen	A Low-Power Heterogeneous Multiprocessor Architecture for Audio Signal Processing.	J. VLSI Signal Process.	2004	DBLP DOI BibTeX RDF	ASIP-application specific instruction set processor, low power, multiprocessor, heterogeneous, scalable architecture, audio signal processing
28	Mohamed A. Gomaa, Michael D. Powell, T. N. Vijaykumar	Heat-and-run: leveraging SMT and CMP to manage power density through the operating system.	ASPLOS	2004	DBLP DOI BibTeX RDF	CMP, migration, SMT, heat, power density
28	Catherine H. Gebotys, Robert J. Gebotys	A Framework for Security on NoC Technologies.	ISVLSI	2003	DBLP DOI BibTeX RDF
28	Ganapathy Kasturirangan, Michael S. Hsiao	Spectrum-Based BIST in Complex SOCs.	VTS	2002	DBLP DOI BibTeX RDF
28	Jaehyuk Huh 0001, Doug Burger, Stephen W. Keckler	Exploring the Design Space of Future CMPs.	IEEE PACT	2001	DBLP DOI BibTeX RDF
28	C. P. Ravikumar, Ashutosh Verma, Gaurav Chandra	A Polynomial-Time Algorithm for Power Constrained Testing of Core Based Systems.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
24	Muhammad Asfand Hafeez, Wai-Kong Lee, Angshuman Karmakar, Seong Oun Hwang	TMVP-based Polynomial Convolution for Saber and Sable on GPU using CUDA-cores and Tensor-cores.	IACR Cryptol. ePrint Arch.	2023	DBLP BibTeX RDF
24	Hyunsoo Cho, Kyounghwan Hong	Corners of self-conjugate (s, s + 1)-cores and (s‾, s+1‾)-cores.	Discret. Math.	2022	DBLP DOI BibTeX RDF
24	Khoa Ho, Hui Zhao 0013, Adwait Jog, Saraju P. Mohanty	Improving GPU Throughput through Parallel Execution Using Tensor Cores and CUDA Cores.	ISVLSI	2022	DBLP DOI BibTeX RDF
24	Ehsan Ali, Wanchalerm Pora	Modular transformation of embedded systems from firm-cores to soft-cores.	Int. J. Embed. Syst.	2021	DBLP DOI BibTeX RDF
24	Redha Gouicem, Damien Carver, Jean-Pierre Lozi, Julien Sopena, Baptiste Lepers, Willy Zwaenepoel, Nicolas Palix, Julia Lawall, Gilles Muller	Fewer Cores, More Hertz: Leveraging High-Frequency Cores in the OS Scheduler for Improved Application Performance.	USENIX Annual Technical Conference	2020	DBLP BibTeX RDF
24	Hsien-Chung Wu	Cores and dominance cores of cooperative games endowed with fuzzy payoffs.	Fuzzy Optim. Decis. Mak.	2019	DBLP DOI BibTeX RDF
24	Shruti Padmanabha, Andrew Lukefahr, Reetuparna Das, Scott A. Mahlke	Mirage cores: the illusion of many out-of-order cores using in-order hardware.	MICRO	2017	DBLP DOI BibTeX RDF
24	Rishi Nath, James A. Sellers	A Combinatorial Proof of a Relationship Between Maximal $(2k-1, 2k+1)$-Cores and $(2k-1, 2k, 2k+1)$-Cores.	Electron. J. Comb.	2016	DBLP DOI BibTeX RDF
24	Mitsuhiko Igarashi, Toshifumi Uemura, Ryo Mori, Hiroshi Kishibe, Midori Nagayama, Masaaki Taniguchi, Kohei Wakahara, Toshiharu Saito, Masaki Fujigaya, Kazuki Fukuoka, Koji Nii, Takeshi Kataoka, Toshihiro Hattori	A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores.	IEEE J. Solid State Circuits	2015	DBLP DOI BibTeX RDF
24	Pier Stanislao Paolucci, Roberto Ammendola, Andrea Biagioni, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Elena Pastorelli, Francesco Simula, Piero Vicini	Power, Energy and Speed of Embedded and Server Multi-Cores applied to Distributed Simulation of Spiking Neural Networks: ARM in NVIDIA Tegra vs Intel Xeon quad-cores.	CoRR	2015	DBLP BibTeX RDF
24	Hsien-Chung Wu	Unifying the proper cores and dominance cores of cooperative fuzzy games.	Fuzzy Optim. Decis. Mak.	2015	DBLP DOI BibTeX RDF
24	Xinke Chen, Guangfei Zhang, Huandong Wang, Ruiyang Wu, Peng Wu, Longbing Zhang	MRP: mix real cores and pseudo cores for FPGA-based chip-multiprocessor simulation.	DATE	2015	DBLP BibTeX RDF
24	Nayandeep Deka Baruah, Kallol Nath	Infinite families of arithmetic identities for self-conjugate 5-cores and 7-cores.	Discret. Math.	2014	DBLP DOI BibTeX RDF
24	Mitsuhiko Igarashi, Toshifumi Uemura, Ryo Mori, Noriaki Maeda, Hiroshi Kishibe, Midori Nagayama, Masaaki Taniguchi, Kohei Wakahara, Toshiharu Saito, Masaki Fujigaya, Kazuki Fukuoka, Koji Nii, Takeshi Kataoka, Toshihiro Hattori	10.2 A 28nm HPM heterogeneous multi-core mobile application processor with 2GHz cores and low-power 1GHz cores.	ISSCC	2014	DBLP DOI BibTeX RDF
24	Amin Ansari, Shuguang Feng, Shantanu Gupta, Josep Torrellas, Scott A. Mahlke	Illusionist: Transforming lightweight cores into aggressive cores on demand.	HPCA	2013	DBLP DOI BibTeX RDF
24	Hsien-Chung Wu	Proper cores and dominance cores of fuzzy games.	Fuzzy Optim. Decis. Mak.	2012	DBLP DOI BibTeX RDF
24	Joachim Knäblein, Claudia Tischendorf, Erik Markert, Ulrich Heinkel	Technology Independent, Embedded Logic Cores Utilizing synthesizable embedded FPGA-cores for ASIC design validation.	ReCoSoC	2010	DBLP BibTeX RDF
24	David Aukerman, Ben Kane, Lawrence Sze	On simultaneous s-cores/t-cores.	Discret. Math.	2009	DBLP DOI BibTeX RDF
24	Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki	Testing TAPed cores and wrapped cores with the same test access mechanism.	DATE	2001	DBLP DOI BibTeX RDF
24	John A. Baldwin Jr.	Circuits Employing Toroidal Magnetic Cores as Analogs of Multipath Cores.	IRE Trans. Electron. Comput.	1962	DBLP DOI BibTeX RDF
23	Martin Zabel, Rainer G. Spallek	Application requirements and efficiency of embedded Java bytecode multi-cores.	JTRES	2010	DBLP DOI BibTeX RDF	multi-core, multi-threaded, realtime, Java bytecode
23	Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott A. Mahlke	Necromancer: enhancing system throughput by animating dead cores.	ISCA	2010	DBLP DOI BibTeX RDF	execution abstraction, heterogeneous core coupling, manufacturing defects
23	Wan Yeon Lee, Young Woong Ko, Heejo Lee, Hyogon Kim	Energy-efficient scheduling of a real-time task on DVFS-enabled multi-cores.	ICHIT	2009	DBLP DOI BibTeX RDF	parallel processing, energy efficiency, DVFS, multi-core processor, real-time video
23	Jiuxing Liu, Bülent Abali	Virtualization polling engine (VPE): using dedicated CPU cores to accelerate I/O virtualization.	ICS	2009	DBLP DOI BibTeX RDF	networking, virtual machine, ethernet
23	David Tarjan, Jiayuan Meng, Kevin Skadron	Increasing memory miss tolerance for SIMD cores.	SC	2009	DBLP DOI BibTeX RDF
23	Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos	Multilevel-Huffman Test-Data Compression for IP Cores With Multiple Scan Chains.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
23	Danilo Ravotto, Ernesto Sánchez 0001, Massimiliano Schillaci, Giovanni Squillero	An Evolutionary Methodology for Test Generation for Peripheral Cores Via Dynamic FSM Extraction.	EvoWorkshops	2008	DBLP DOI BibTeX RDF	Peripheral testing, ?GP3, test generation, approximate methods, evolutionary methods
23	Nagarajan Venkateswaran, Karthik Chandrasekar 0001, Shrikanth Ganapathy	Design for Testability of Functional Cores in High Performance Node Architectures.	DELTA	2008	DBLP DOI BibTeX RDF	Integrated Memory and Logic, Memory-in-Logic Cells, Higher Level Functional Units, Performance Consistency, Reliabilty, Heterogenous Multi-Core
23	Vivy Suhendra, Tulika Mitra	Exploring locking & partitioning for predictable shared caches on multi-cores.	DAC	2008	DBLP DOI BibTeX RDF	cache locking, shared-cache multi-core, WCET, cache partitioning
23	Xiaoyu Ruan, Rajendra S. Katti	Data-Independent Pattern Run-Length Compression for Testing Embedded Cores in SoCs.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	system-on-chips, automatic test pattern generator, Automatic test equipment, test data compression, embedded core testing, run-length coding
23	Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos	Multilevel Huffman Coding: An Efficient Test-Data Compression Method for IP Cores.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
23	Tino Weinkauf, Jan Sahner, Holger Theisel, Hans-Christian Hege	Cores of Swirling Particle Motion in Unsteady Flows.	IEEE Trans. Vis. Comput. Graph.	2007	DBLP DOI BibTeX RDF	particle motion, feature extraction, unsteady flow visualization
23	Ozgur Sinanoglu, Tsvetomir Petrov	A non-intrusive isolation approach for soft cores.	DATE	2007	DBLP DOI BibTeX RDF
23	Nicola E. L'Insalata, Sergio Saponara, Luca Fanucci, Pierangelo Terreni	Automatic Generation of Low-Complexity FFT/IFFT Cores for Multi-Band OFDM Systems.	DSD	2007	DBLP DOI BibTeX RDF
23	Albert Meixner, Michael E. Bauer, Daniel J. Sorin	Argus: Low-Cost, Comprehensive Error Detection in Simple Cores.	MICRO	2007	DBLP DOI BibTeX RDF
23	Letícia Maria Veiras Bolzani, Ernesto Sánchez 0001, Massimiliano Schillaci, Giovanni Squillero	Co-evolution of test programs and stimuli vectors for testing of embedded peripheral cores.	IEEE Congress on Evolutionary Computation	2007	DBLP DOI BibTeX RDF
23	Jin Wang, Chang Hao Piao, Chong Ho Lee	Implementing Multi-VRC Cores to Evolve Combinational Logic Circuits in Parallel.	ICES	2007	DBLP DOI BibTeX RDF	Intrinsic evolvable hardware, scalability, parallel evolutionary algorithm, incremental evolution
23	Letícia Maria Veiras Bolzani, Ernesto Sánchez 0001, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero	An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores.	IOLTS	2007	DBLP DOI BibTeX RDF
23	Ilya Ganusov, Martin Burtscher	Future execution: A prefetching mechanism that uses multiple cores to speed up single threads.	ACM Trans. Archit. Code Optim.	2006	DBLP DOI BibTeX RDF	Future execution, chip multiprocessors, prefetching, memory wall
23	Gail A. Walters	Innovative technologies I - Applying scalable acalis field programmable multi-cores to HPC.	SC	2006	DBLP DOI BibTeX RDF
23	Daming Zhang, King-Jet Tseng	Effect of High Permittivity and Core Dimensions on the Permeability Measurement for Mn-Zn Ferrite Cores Used in High-Frequency Transformer.	DELTA	2006	DBLP DOI BibTeX RDF	Complex permeability, dielectric effect, field-circuit coupled method, Mn-Zn ferrite
23	Kaizhong Jiang, Zhao Lu, Junzhong Gu	A 0-1 Hardware/Software Partitioning Algorithm over IP cores.	ICAS	2006	DBLP DOI BibTeX RDF
23	Mohammad Tehranipoor, Mehrdad Nourani, Krishnendu Chakrabarty	Nine-coded compression technique for testing embedded cores in SoCs.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
23	Wei Han 0001, Ahmet T. Erdogan, Tughrul Arslan, Mohd. Hasan	The development of high performance FFT IP cores through hybrid low power algorithmic methodology.	ASP-DAC	2005	DBLP DOI BibTeX RDF
23	Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna	Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores.	IPDPS	2005	DBLP DOI BibTeX RDF
23	Ernesto Sánchez 0001, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero, Luca Sterpone, Massimo Violante	New evolutionary techniques for test-program generation for complex microprocessor cores.	GECCO	2005	DBLP DOI BibTeX RDF	evolutionary algorithms, automatic test program generation
23	Bradley R. Quinton, Steven J. E. Wilton	Concentrator access networks for programmable logic cores on SoCs.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
23	Lei Li 0036, Krishnendu Chakrabarty, Seiji Kajihara, Shivakumar Swaminathan	Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores.	VLSI Design	2005	DBLP DOI BibTeX RDF
23	Arijit Ghosh, Tony Givargis	Cache optimization for embedded processor cores: An analytical approach.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	design space exploration, system-on-a-chip, Cache optimization, core-based design
23	Yi-Dong Shen, Zhiyong Shen, Shi-Ming Zhang, Qiang Yang 0001	Cluster Cores-Based Clustering for High Dimensional Data.	ICDM	2004	DBLP DOI BibTeX RDF
23	Sukanta Das, Biplab K. Sikdar, Parimal Pal Chaudhuri	Nonlinear CA Based Scalable Design of On-Chip TPG for Multiple Cores.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
23	Jianhui Xing, Hong Wang, Shiyuan Yang	Constructing Transparency Paths for IP Cores Using Greedy Searching Strategy.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
23	Edson L. Horta, John W. Lockwood	Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs.	FPL	2004	DBLP DOI BibTeX RDF
23	Qiang Xu 0001, Nicola Nicolici	Time/Area Tradeoffs in Testing Hierarchical SOCs With Hard Mega-Cores.	ITC	2004	DBLP DOI BibTeX RDF