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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 2996 occurrences of 1338 keywords
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Results
Found 4838 publication records. Showing 4828 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
29 | Chiou-Kou Tung, Shao-Hui Shieh, Yu-Cherng Hung, Ming-Chien Tsai |
High-Performance Low-Power Full-Swing Full Adder Cores with Output Driving Capability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 614-617, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Peter Hallschmid, Steven J. E. Wilton |
Routing architecture optimizations for high-density embedded programmable IP cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(11), pp. 1320-1324, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda |
Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), Common Challenges and Solutions, 3-4 November 2005, Austin, Texas, USA, pp. 55-62, 2005, IEEE Computer Society, 0-7695-2627-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Roman L. Lysecky, Frank Vahid |
A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 18-23, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Yana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo |
Straight Method for Reallocation of Complex Cores by Dynamic Reconfiguration in Virtex II FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 8-10 June 2005, Montreal, Canada, pp. 77-83, 2005, IEEE Computer Society, 0-7695-2361-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
29 | Holger Lange, Andreas Koch 0001 |
HW/SW Co-design by Automatic Embedding of Complex IP Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings, pp. 679-689, 2004, Springer, 3-540-22989-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Kwan-Hee Yoo, Jong-Sung Ha |
An Effective Modeling of Single Cores Prostheses Using Geometric Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Computational Science ![In: Computational Science - ICCS 2004, 4th International Conference, Kraków, Poland, June 6-9, 2004, Proceedings, Part IV, pp. 131-138, 2004, Springer, 3-540-22129-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Jeff Young, Ron Sass |
FERP Interface and Interconnect Cores for Stream Processing Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing, International Conference EUC 2004, Aizu-Wakamatsu City, Japan, August 25-27, 2004, Proceedings, pp. 291-300, 2004, Springer, 3-540-22906-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
29 | Yuejian Wu, Paul N. MacDonald |
Testing ASICs with multiple identical cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(3), pp. 327-336, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
29 | Subhayu Basu, Indranil Sengupta 0001, Dipanwita Roy Chowdhury, Sudipta Bhawmik |
An Integrated Approach to Testing Embedded Cores and Interconnects Using Test Access Mechanism (TAM) Switch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(4-5), pp. 475-485, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
TAM switch, system-on-chip, interconnect testing |
29 | Madhu K. Iyer, Kwang-Ting Cheng |
Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA, pp. 139-144, 2002, IEEE Computer Society, 0-7695-1570-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
29 | Mohamed M. Hafed, Gordon W. Roberts |
Test and Evaluation of Multiple Embedded Mixed-Signal Test Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 1022-1030, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
29 | Antonis M. Paschalis, Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Yervant Zorian |
An Effective BIST Architecture for Fast Multiplier Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 117-121, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
29 | Ken Batcher, Christos A. Papachristou |
Instruction Randomization Self Test For Processor Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA, pp. 34-40, 1999, IEEE Computer Society, 0-7695-0146-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
29 | |
Testing Embedded Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 14(2), pp. 81-89, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
28 | Stephen S. Pawlowski |
Exascale science: the next frontier in high performance computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 24th International Conference on Supercomputing, 2010, Tsukuba, Ibaraki, Japan, June 2-4, 2010, pp. 1, 2010, ACM, 978-1-4503-0018-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
exascale systems, memory and storage bandwidth, millions of cores, software scalability, system resiliency, power consumption |
28 | Vignesh T. Ravi, Wenjing Ma, David Chiu 0001, Gagan Agrawal |
Compiler and runtime support for enabling generalized reduction computations on heterogeneous parallel configurations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 24th International Conference on Supercomputing, 2010, Tsukuba, Ibaraki, Japan, June 2-4, 2010, pp. 137-146, 2010, ACM, 978-1-4503-0018-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
dynamic work distribution, generalized reductions, multi-cores, GPGPU, heterogeneous systems |
28 | M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt |
Accelerating critical section execution with asymmetric multi-core architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2009, Washington, DC, USA, March 7-11, 2009, pp. 253-264, 2009, ACM, 978-1-60558-406-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
heterogeneous cores, parallel programming, cmp, multi-core, locks, critical sections |
28 | Sudarshan Bahukudumbi, Sule Ozev, Krishnendu Chakrabarty, Vikram Iyengar |
AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 823-828, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
mixed-signal cores, wafer-level defect screening, packaging cost reduction, big-D/small-A mixed-signal system-on-chip designs, mixed-signal SoC, consumer electronics market, wafer-level testing, correlation-based signature analysis, low-cost digital testers, generic cost model, mixed-signal test, digital logic, test cost reduction |
28 | Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki |
CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(4-5), pp. 455-473, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
SoC test control, TAPed cores, P1500 wrappers, test access mechanism, I/O bandwidth |
28 | Serafín Olcoz, Ana Castellvi, Maria Garcia, Jose Angel Gomez |
Static Analysis Tools for Soft-Core Reviews and Audits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 935-936, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Soft-Cores, management, analysis, VHDL |
28 | Guihai Yan, Xiaoyao Liang, Yinhe Han 0001, Xiaowei Li 0001 |
Leveraging the core-level complementary effects of PVT variations to reduce timing emergencies in multi-core processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France, pp. 485-496, 2010, ACM, 978-1-4503-0053-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
complimentary effects, delay sensor, pvt variations, timing emergency, thread migration |
28 | Abhishek Udupa, R. Govindarajan, Matthew J. Thazhuthaveetil |
Synergistic execution of stream programs on multicores with accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems, LCTES 2009, Dublin, Ireland, June 19-20, 2009, pp. 99-108, 2009, ACM, 978-1-60558-356-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
CUDAa, partitioning, software pipelining, stream programming, GPU programming |
28 | Moinuddin K. Qureshi |
Adaptive Spill-Receive for robust high-performance caching in CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA, pp. 45-54, 2009, IEEE Computer Society, 978-1-4244-2932-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
28 | Jungseob Lee, Nam Sung Kim |
Optimizing total power of many-core processors considering voltage scaling limit and process variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 201-206, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
voltage and frequency scaling, process variations, parallel applications, many-core processor |
28 | Björn Saballus, Thomas Fuhrmann |
Maintaining reference graphs of globally accessible objects in fully decentralized distributed systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPDC ![In: Proceedings of the 18th ACM International Symposium on High Performance Distributed Computing, HPDC 2009, Garching, Germany, June 11-13, 2009, pp. 59-60, 2009, ACM, 978-1-60558-587-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
globally accessible objects, single system image, object migration |
28 | Brian M. Rogers, Anil Krishna, Gordon B. Bell, Ken V. Vu, Xiaowei Jiang, Yan Solihin |
Scaling the bandwidth wall: challenges in and avenues for CMP scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 36th International Symposium on Computer Architecture (ISCA 2009), June 20-24, 2009, Austin, TX, USA, pp. 371-382, 2009, ACM, 978-1-60558-526-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
analytical model, memory bandwidth, chip multi-processor |
28 | Jungseob Lee, Nam Sung Kim |
Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 46th Design Automation Conference, DAC 2009, San Francisco, CA, USA, July 26-31, 2009, pp. 47-50, 2009, ACM, 978-1-60558-497-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
multicore processor, DVFS, power gating |
28 | Bogdan F. Romanescu, Daniel J. Sorin |
Core cannibalization architecture: improving lifetime chip performance for multicore processors in the presence of hard faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 17th International Conference on Parallel Architectures and Compilation Techniques, PACT 2008, Toronto, Ontario, Canada, October 25-29, 2008, pp. 43-51, 2008, ACM, 978-1-60558-282-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
lifetime performance, fault tolerance, reliability, multicore |
28 | Haitham Akkary, Komal Jothi, Renjith Retnamma, Satyanarayana Nekkalapu, Doug Hall, Shahrokh Shahidzadeh |
On the potential of latency tolerant execution in speculative multithreading. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IFMT ![In: Proceedings of the 1st international forum on Next-generation multicore/manycore technologies, IFMT 2008, Cairo, Egypt, November 24-25, 2008, pp. 3, 2008, ACM, 978-1-60558-407-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
latency-tolerant architectures, chip multiprocessors, speculative multithreading, many-core processors |
28 | Jeffery A. Brown, Dean M. Tullsen |
The shared-thread multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 22nd Annual International Conference on Supercomputing, ICS 2008, Island of Kos, Greece, June 7-12, 2008, pp. 73-82, 2008, ACM, 978-1-60558-158-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
chip multiprocessors, simultaneous multithreading |
28 | James Laudon, Lawrence Spracklen |
The Coming Wave of Multithreaded Chip Multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 35(3), pp. 299-330, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
performance, parallel programming, multithreading, Chip multiprocessing |
28 | Hongtao Zhong, Steven A. Lieberman, Scott A. Mahlke |
Extending Multicore Architectures to Exploit Hybrid Parallelism in Single-thread Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 10-14 February 2007, Phoenix, Arizona, USA, pp. 25-36, 2007, IEEE Computer Society, 1-4244-0804-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
28 | Bryan Veal, Annie P. Foong |
Performance scalability of a multi-core web server. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ANCS ![In: Proceedings of the 2007 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, ANCS 2007, Orlando, Florida, USA, December 3-4, 2007, pp. 57-66, 2007, ACM, 978-1-59593-945-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
network protocol stacks, scalability, load balancing, networks, parallelism, web servers, cache hierarchies |
28 | Pavel A. Dmitriev, Carl Lagoze |
Mining Generalized Graph Patterns Based on User Examples. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDM ![In: Proceedings of the 6th IEEE International Conference on Data Mining (ICDM 2006), 18-22 December 2006, Hong Kong, China, pp. 857-862, 2006, IEEE Computer Society, 0-7695-2701-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Jared C. Smolens, Brian T. Gold, Babak Falsafi, James C. Hoe |
Reunion: Complexity-Effective Multicore Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 9-13 December 2006, Orlando, Florida, USA, pp. 223-234, 2006, IEEE Computer Society, 0-7695-2732-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Pedro C. Diniz, Gokul Govindu |
Design of a Field-Programmable Dual-Precision Floating-Point Arithmetic Unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-4, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Noel Eisley, Vassos Soteriou, Li-Shiuan Peh |
High-level power analysis for multi-core chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2006 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2006, Seoul, Korea, October 22-25, 2006, pp. 389-400, 2006, ACM, 1-59593-543-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
simulation, chip multiprocessor (CMP), multi-core, power analysis, system-on-a-chip (SoC) |
28 | Vasileios Liaskovitis, Shimin Chen, Phillip B. Gibbons, Anastassia Ailamaki, Guy E. Blelloch, Babak Falsafi, Limor Fix, Nikos Hardavellas, Michael Kozuch, Todd C. Mowry, Chris Wilkerson |
Parallel depth first vs. work stealing schedulers on CMP architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPAA ![In: SPAA 2006: Proceedings of the 18th Annual ACM Symposium on Parallelism in Algorithms and Architectures, Cambridge, Massachusetts, USA, July 30 - August 2, 2006, pp. 330, 2006, ACM, 1-59593-452-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
scheduling, caches, chip multiprocessors |
28 | Anuja Sehgal, Sule Ozev, Krishnendu Chakrabarty |
A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 137-142, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Özgün Paker, Jens Sparsø, Niels Haandbæk, Mogens Isager, Lars Skovby Nielsen |
A Low-Power Heterogeneous Multiprocessor Architecture for Audio Signal Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 37(1), pp. 95-110, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
ASIP-application specific instruction set processor, low power, multiprocessor, heterogeneous, scalable architecture, audio signal processing |
28 | Mohamed A. Gomaa, Michael D. Powell, T. N. Vijaykumar |
Heat-and-run: leveraging SMT and CMP to manage power density through the operating system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2004, Boston, MA, USA, October 7-13, 2004, pp. 260-270, 2004, ACM, 1-58113-804-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
CMP, migration, SMT, heat, power density |
28 | Catherine H. Gebotys, Robert J. Gebotys |
A Framework for Security on NoC Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), New Trends and Technologies for VLSI Systems Design, 20-21 February 2003, Tampa, FL, USA, pp. 113-120, 2003, IEEE Computer Society, 0-7695-1904-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
28 | Ganapathy Kasturirangan, Michael S. Hsiao |
Spectrum-Based BIST in Complex SOCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA, pp. 111-116, 2002, IEEE Computer Society, 0-7695-1570-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
28 | Jaehyuk Huh 0001, Doug Burger, Stephen W. Keckler |
Exploring the Design Space of Future CMPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001), 8-12 September 2001, Barcelona, Spain, pp. 199-210, 2001, IEEE Computer Society, 0-7695-1363-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
28 | C. P. Ravikumar, Ashutosh Verma, Gaurav Chandra |
A Polynomial-Time Algorithm for Power Constrained Testing of Core Based Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 107-112, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
24 | Muhammad Asfand Hafeez, Wai-Kong Lee, Angshuman Karmakar, Seong Oun Hwang |
TMVP-based Polynomial Convolution for Saber and Sable on GPU using CUDA-cores and Tensor-cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IACR Cryptol. ePrint Arch. ![In: IACR Cryptol. ePrint Arch. 2023, pp. 1541, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP BibTeX RDF |
|
24 | Hyunsoo Cho, Kyounghwan Hong |
Corners of self-conjugate (s, s + 1)-cores and (s‾, s+1‾)-cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Discret. Math. ![In: Discret. Math. 345(9), pp. 112949, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Khoa Ho, Hui Zhao 0013, Adwait Jog, Saraju P. Mohanty |
Improving GPU Throughput through Parallel Execution Using Tensor Cores and CUDA Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2022, Nicosia, Cyprus, July 4-6, 2022, pp. 223-228, 2022, IEEE, 978-1-6654-6605-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
24 | Ehsan Ali, Wanchalerm Pora |
Modular transformation of embedded systems from firm-cores to soft-cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Embed. Syst. ![In: Int. J. Embed. Syst. 14(3), pp. 259-276, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
24 | Redha Gouicem, Damien Carver, Jean-Pierre Lozi, Julien Sopena, Baptiste Lepers, Willy Zwaenepoel, Nicolas Palix, Julia Lawall, Gilles Muller |
Fewer Cores, More Hertz: Leveraging High-Frequency Cores in the OS Scheduler for Improved Application Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
USENIX Annual Technical Conference ![In: 2020 USENIX Annual Technical Conference, USENIX ATC 2020, July 15-17, 2020, pp. 435-448, 2020, USENIX Association, 978-1-939133-14-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
24 | Hsien-Chung Wu |
Cores and dominance cores of cooperative games endowed with fuzzy payoffs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Fuzzy Optim. Decis. Mak. ![In: Fuzzy Optim. Decis. Mak. 18(2), pp. 219-257, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
24 | Shruti Padmanabha, Andrew Lukefahr, Reetuparna Das, Scott A. Mahlke |
Mirage cores: the illusion of many out-of-order cores using in-order hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2017, Cambridge, MA, USA, October 14-18, 2017, pp. 745-758, 2017, ACM, 978-1-4503-4952-9. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
24 | Rishi Nath, James A. Sellers |
A Combinatorial Proof of a Relationship Between Maximal $(2k-1, 2k+1)$-Cores and $(2k-1, 2k, 2k+1)$-Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Electron. J. Comb. ![In: Electron. J. Comb. 23(1), pp. 1, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
24 | Mitsuhiko Igarashi, Toshifumi Uemura, Ryo Mori, Hiroshi Kishibe, Midori Nagayama, Masaaki Taniguchi, Kohei Wakahara, Toshiharu Saito, Masaki Fujigaya, Kazuki Fukuoka, Koji Nii, Takeshi Kataoka, Toshihiro Hattori |
A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Solid State Circuits ![In: IEEE J. Solid State Circuits 50(1), pp. 92-101, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Pier Stanislao Paolucci, Roberto Ammendola, Andrea Biagioni, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Elena Pastorelli, Francesco Simula, Piero Vicini |
Power, Energy and Speed of Embedded and Server Multi-Cores applied to Distributed Simulation of Spiking Neural Networks: ARM in NVIDIA Tegra vs Intel Xeon quad-cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1505.03015, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
|
24 | Hsien-Chung Wu |
Unifying the proper cores and dominance cores of cooperative fuzzy games. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Fuzzy Optim. Decis. Mak. ![In: Fuzzy Optim. Decis. Mak. 14(3), pp. 243-263, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
24 | Xinke Chen, Guangfei Zhang, Huandong Wang, Ruiyang Wu, Peng Wu, Longbing Zhang |
MRP: mix real cores and pseudo cores for FPGA-based chip-multiprocessor simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France, March 9-13, 2015, pp. 211-216, 2015, ACM, 978-3-9815370-4-8. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
|
24 | Nayandeep Deka Baruah, Kallol Nath |
Infinite families of arithmetic identities for self-conjugate 5-cores and 7-cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Discret. Math. ![In: Discret. Math. 321, pp. 57-67, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
24 | Mitsuhiko Igarashi, Toshifumi Uemura, Ryo Mori, Noriaki Maeda, Hiroshi Kishibe, Midori Nagayama, Masaaki Taniguchi, Kohei Wakahara, Toshiharu Saito, Masaki Fujigaya, Kazuki Fukuoka, Koji Nii, Takeshi Kataoka, Toshihiro Hattori |
10.2 A 28nm HPM heterogeneous multi-core mobile application processor with 2GHz cores and low-power 1GHz cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSCC ![In: 2014 IEEE International Conference on Solid-State Circuits Conference, ISSCC 2014, Digest of Technical Papers, San Francisco, CA, USA, February 9-13, 2014, pp. 178-179, 2014, IEEE, 978-1-4799-0918-6. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
24 | Amin Ansari, Shuguang Feng, Shantanu Gupta, Josep Torrellas, Scott A. Mahlke |
Illusionist: Transforming lightweight cores into aggressive cores on demand. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013, Shenzhen, China, February 23-27, 2013, pp. 436-447, 2013, IEEE Computer Society, 978-1-4673-5585-8. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
24 | Hsien-Chung Wu |
Proper cores and dominance cores of fuzzy games. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Fuzzy Optim. Decis. Mak. ![In: Fuzzy Optim. Decis. Mak. 11(1), pp. 47-72, 2012. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
24 | Joachim Knäblein, Claudia Tischendorf, Erik Markert, Ulrich Heinkel |
Technology Independent, Embedded Logic Cores Utilizing synthesizable embedded FPGA-cores for ASIC design validation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReCoSoC ![In: Proceedings of the 5th International Workshop on Reconfigurable Communication-centric Systems on Chip, ReCoSoC 2010, Karlsruhe, Germany, May 17-19, 2010, pp. 161-168, 2010, KIT Scientific Publishing, 978-3-86644-515-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP BibTeX RDF |
|
24 | David Aukerman, Ben Kane, Lawrence Sze |
On simultaneous s-cores/t-cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Discret. Math. ![In: Discret. Math. 309(9), pp. 2712-2720, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
24 | Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki |
Testing TAPed cores and wrapped cores with the same test access mechanism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2001, Munich, Germany, March 12-16, 2001, pp. 150-155, 2001, IEEE Computer Society, 0-7695-0993-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
24 | John A. Baldwin Jr. |
Circuits Employing Toroidal Magnetic Cores as Analogs of Multipath Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IRE Trans. Electron. Comput. ![In: IRE Trans. Electron. Comput. 11(2), pp. 218-223, 1962. The full citation details ...](Pics/full.jpeg) |
1962 |
DBLP DOI BibTeX RDF |
|
23 | Martin Zabel, Rainer G. Spallek |
Application requirements and efficiency of embedded Java bytecode multi-cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
JTRES ![In: Proceedings of the 8th International Workshop on Java Technologies for Real-Time and Embedded Systems, JTRES 2010, Prague, Czech Republic, August 19-21, 2010, pp. 46-52, 2010, ACM, 978-1-4503-0122-0. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
multi-core, multi-threaded, realtime, Java bytecode |
23 | Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott A. Mahlke |
Necromancer: enhancing system throughput by animating dead cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France, pp. 473-484, 2010, ACM, 978-1-4503-0053-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
execution abstraction, heterogeneous core coupling, manufacturing defects |
23 | Wan Yeon Lee, Young Woong Ko, Heejo Lee, Hyogon Kim |
Energy-efficient scheduling of a real-time task on DVFS-enabled multi-cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICHIT ![In: Proceedings of the 2009 International Conference on Hybrid Information Technology, ICHIT 2009, Daejeon, Korea, August 27-29, 2009, pp. 273-277, 2009, ACM, 978-1-60558-662-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
parallel processing, energy efficiency, DVFS, multi-core processor, real-time video |
23 | Jiuxing Liu, Bülent Abali |
Virtualization polling engine (VPE): using dedicated CPU cores to accelerate I/O virtualization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 23rd international conference on Supercomputing, 2009, Yorktown Heights, NY, USA, June 8-12, 2009, pp. 225-234, 2009, ACM, 978-1-60558-498-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
networking, virtual machine, ethernet |
23 | David Tarjan, Jiayuan Meng, Kevin Skadron |
Increasing memory miss tolerance for SIMD cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE Conference on High Performance Computing, SC 2009, November 14-20, 2009, Portland, Oregon, USA, 2009, ACM, 978-1-60558-744-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos |
Multilevel-Huffman Test-Data Compression for IP Cores With Multiple Scan Chains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(7), pp. 926-931, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
23 | Danilo Ravotto, Ernesto Sánchez 0001, Massimiliano Schillaci, Giovanni Squillero |
An Evolutionary Methodology for Test Generation for Peripheral Cores Via Dynamic FSM Extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EvoWorkshops ![In: Applications of Evolutionary Computing, EvoWorkshops 2008: EvoCOMNET, EvoFIN, EvoHOT, EvoIASP, EvoMUSART, EvoNUM, EvoSTOC, and EvoTransLog, Naples, Italy, March 26-28, 2008. Proceedings, pp. 214-223, 2008, Springer, 978-3-540-78760-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Peripheral testing, ?GP3, test generation, approximate methods, evolutionary methods |
23 | Nagarajan Venkateswaran, Karthik Chandrasekar 0001, Shrikanth Ganapathy |
Design for Testability of Functional Cores in High Performance Node Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008, pp. 302-307, 2008, IEEE Computer Society, 978-0-7695-3110-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Integrated Memory and Logic, Memory-in-Logic Cells, Higher Level Functional Units, Performance Consistency, Reliabilty, Heterogenous Multi-Core |
23 | Vivy Suhendra, Tulika Mitra |
Exploring locking & partitioning for predictable shared caches on multi-cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 300-303, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
cache locking, shared-cache multi-core, WCET, cache partitioning |
23 | Xiaoyu Ruan, Rajendra S. Katti |
Data-Independent Pattern Run-Length Compression for Testing Embedded Cores in SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(4), pp. 545-556, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
system-on-chips, automatic test pattern generator, Automatic test equipment, test data compression, embedded core testing, run-length coding |
23 | Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos |
Multilevel Huffman Coding: An Efficient Test-Data Compression Method for IP Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(6), pp. 1070-1083, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Tino Weinkauf, Jan Sahner, Holger Theisel, Hans-Christian Hege |
Cores of Swirling Particle Motion in Unsteady Flows. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Vis. Comput. Graph. ![In: IEEE Trans. Vis. Comput. Graph. 13(6), pp. 1759-1766, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
particle motion, feature extraction, unsteady flow visualization |
23 | Ozgur Sinanoglu, Tsvetomir Petrov |
A non-intrusive isolation approach for soft cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 27-32, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Nicola E. L'Insalata, Sergio Saponara, Luca Fanucci, Pierangelo Terreni |
Automatic Generation of Low-Complexity FFT/IFFT Cores for Multi-Band OFDM Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany, pp. 361-368, 2007, IEEE Computer Society, 0-7695-2978-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Albert Meixner, Michael E. Bauer, Daniel J. Sorin |
Argus: Low-Cost, Comprehensive Error Detection in Simple Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 1-5 December 2007, Chicago, Illinois, USA, pp. 210-222, 2007, IEEE Computer Society, 0-7695-3047-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Letícia Maria Veiras Bolzani, Ernesto Sánchez 0001, Massimiliano Schillaci, Giovanni Squillero |
Co-evolution of test programs and stimuli vectors for testing of embedded peripheral cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Congress on Evolutionary Computation ![In: Proceedings of the IEEE Congress on Evolutionary Computation, CEC 2007, 25-28 September 2007, Singapore, pp. 3474-3481, 2007, IEEE, 978-1-4244-1339-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Jin Wang, Chang Hao Piao, Chong Ho Lee |
Implementing Multi-VRC Cores to Evolve Combinational Logic Circuits in Parallel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICES ![In: Evolvable Systems: From Biology to Hardware, 7th International Conference, ICES 2007, Wuhan, China, September 21-23, 2007, Proceedings, pp. 23-34, 2007, Springer, 978-3-540-74625-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Intrinsic evolvable hardware, scalability, parallel evolutionary algorithm, incremental evolution |
23 | Letícia Maria Veiras Bolzani, Ernesto Sánchez 0001, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero |
An Automated Methodology for Cogeneration of Test Blocks for Peripheral Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 8-11 July 2007, Heraklion, Crete, Greece, pp. 265-270, 2007, IEEE Computer Society, 0-7695-2918-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
23 | Ilya Ganusov, Martin Burtscher |
Future execution: A prefetching mechanism that uses multiple cores to speed up single threads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 3(4), pp. 424-449, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Future execution, chip multiprocessors, prefetching, memory wall |
23 | Gail A. Walters |
Innovative technologies I - Applying scalable acalis field programmable multi-cores to HPC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, November 11-17, 2006, Tampa, FL, USA, pp. 253, 2006, ACM Press, 0-7695-2700-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Daming Zhang, King-Jet Tseng |
Effect of High Permittivity and Core Dimensions on the Permeability Measurement for Mn-Zn Ferrite Cores Used in High-Frequency Transformer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: Third IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2006), 17-19 January 2006, Kuala Lumpur, Malaysia, pp. 371-378, 2006, IEEE Computer Society, 0-7695-2500-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Complex permeability, dielectric effect, field-circuit coupled method, Mn-Zn ferrite |
23 | Kaizhong Jiang, Zhao Lu, Junzhong Gu |
A 0-1 Hardware/Software Partitioning Algorithm over IP cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICAS ![In: 2006 International Conference on Autonomic and Autonomous Systems (ICAS 2006), 16-21 July 2006, Silicon Valley, California, USA, pp. 25, 2006, IEEE Computer Society, 0-7695-2653-5. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
23 | Mohammad Tehranipoor, Mehrdad Nourani, Krishnendu Chakrabarty |
Nine-coded compression technique for testing embedded cores in SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(6), pp. 719-731, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Wei Han 0001, Ahmet T. Erdogan, Tughrul Arslan, Mohd. Hasan |
The development of high performance FFT IP cores through hybrid low power algorithmic methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 549-552, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna |
Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, 2005, IEEE Computer Society, 0-7695-2312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Ernesto Sánchez 0001, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero, Luca Sterpone, Massimo Violante |
New evolutionary techniques for test-program generation for complex microprocessor cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO ![In: Genetic and Evolutionary Computation Conference, GECCO 2005, Proceedings, Washington DC, USA, June 25-29, 2005, pp. 2193-2194, 2005, ACM, 1-59593-010-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
evolutionary algorithms, automatic test program generation |
23 | Bradley R. Quinton, Steven J. E. Wilton |
Concentrator access networks for programmable logic cores on SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 45-48, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Lei Li 0036, Krishnendu Chakrabarty, Seiji Kajihara, Shivakumar Swaminathan |
Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 53-58, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
23 | Arijit Ghosh, Tony Givargis |
Cache optimization for embedded processor cores: An analytical approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 9(4), pp. 419-440, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
design space exploration, system-on-a-chip, Cache optimization, core-based design |
23 | Yi-Dong Shen, Zhiyong Shen, Shi-Ming Zhang, Qiang Yang 0001 |
Cluster Cores-Based Clustering for High Dimensional Data. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDM ![In: Proceedings of the 4th IEEE International Conference on Data Mining (ICDM 2004), 1-4 November 2004, Brighton, UK, pp. 519-522, 2004, IEEE Computer Society, 0-7695-2142-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Sukanta Das, Biplab K. Sikdar, Parimal Pal Chaudhuri |
Nonlinear CA Based Scalable Design of On-Chip TPG for Multiple Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, pp. 331-334, 2004, IEEE Computer Society, 0-7695-2235-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Jianhui Xing, Hong Wang, Shiyuan Yang |
Constructing Transparency Paths for IP Cores Using Greedy Searching Strategy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, pp. 14-19, 2004, IEEE Computer Society, 0-7695-2235-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Edson L. Horta, John W. Lockwood |
Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings, pp. 975-979, 2004, Springer, 3-540-22989-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
23 | Qiang Xu 0001, Nicola Nicolici |
Time/Area Tradeoffs in Testing Hierarchical SOCs With Hard Mega-Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 1196-1202, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
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