Search results for "interconnection"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
16	Joan-Lluís Ferrer, Elvira Baydal, Antonio Robles, Pedro López 0001, José Duato	Congestion Management in MINs through Marked and Validated Packets.	PDP	2007	DBLP DOI BibTeX RDF
16	Pierre-Marc Bureau, José M. Fernandez 0001	Optimising Networks Against Malware.	IPCCC	2007	DBLP DOI BibTeX RDF
16	Min Xie, Youren Wang, Li Wang, Yuan Zhang	Design on Operator-Based Reconfigurable Hardware Architecture and Cell Circuit.	ICES	2007	DBLP DOI BibTeX RDF	Operator-based programmable cell circuit, FPGA, Reconfigurable computing, Reconfigurable hardware, Information processing
16	Stamatis Vassiliadis, Ioannis Sourdis	FLUX Networks: Interconnects on Demand.	ICSAMOS	2006	DBLP DOI BibTeX RDF
16	Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis	Designing Alternative FPGA Implementations Using Spatial Data from Hardware Resources.	PATMOS	2006	DBLP DOI BibTeX RDF
16	Yuriy Sheynin, Elena Suvorova, Felix Shutenko	Complexity and Low Power Issues for On-chip Interconnections in MPSoC System Level Design.	ISVLSI	2006	DBLP DOI BibTeX RDF
16	Ari Kulmala, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen	Evaluating SoC Network Performance in MPEG-4 Encoder.	SiPS	2006	DBLP DOI BibTeX RDF
16	Kostas Siozios, Dimitrios Soudris	Wire Segment Length and Switch Box Co-Optimization for FPGA Architectures.	FPL	2006	DBLP DOI BibTeX RDF
16	Grigoris Dimitroulakos, Michalis D. Galanis, Constantinos E. Goutis	Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures.	IPDPS	2006	DBLP DOI BibTeX RDF
16	Ming-Der Shieh, Tai-Ping Wang, Chien-Ming Wu, Chun-Ming Huang	Efficient path metric access for reducing interconnect overhead in Viterbi decoders.	ISCAS	2006	DBLP DOI BibTeX RDF
16	Ashok Narasimhan, Bhooma Srinivasaraghavan, Ramalingam Sridhar	A Low-Power Asymmetric Source Driver Level Converter Based Current-Mode Signaling Scheme for Global Interconnects.	VLSI Design	2006	DBLP DOI BibTeX RDF
16	Ngoc Chi Nguyen, Vo Dinh Minh Nhat, Sungyoung Lee	Fault Free Shortest Path Routing on the de Bruijn Networks.	ICN (2)	2005	DBLP DOI BibTeX RDF
16	Erno Salminen, Ari Kulmala, Timo D. Hämäläinen	HIBI-based multiprocessor SoC on FPGA.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
16	Gustavo Pereira, Antonio Andrade Jr., Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell	Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays.	VTS	2005	DBLP DOI BibTeX RDF	FPAA testing, Mixed-signal test, interconnect testing, oscillation-based test
16	Ashok Narasimhan, Manish Kasotiya, Ramalingam Sridhar	A Low-Swing Differential Signaling Scheme for On-Chip Global Interconnects.	VLSI Design	2005	DBLP DOI BibTeX RDF
16	Chien-Ping Chang, Pao-Lien Lai, Jimmy J. M. Tan, Lih-Hsing Hsu	Diagnosability of t-Connected Networks and Product Networks under the Comparison Diagnosis Model.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	comparison diagnosis model, t-diagnosable, order graph, connectivity, Diagnosability, product networks
16	Luciano Lenzini, Enzo Mingozzi, Giovanni Stea	Eligibility-Based Round Robin for Fair and Efficient Packet Scheduling in Wormhole Switching Networks.	IEEE Trans. Parallel Distributed Syst.	2004	DBLP DOI BibTeX RDF	wormhole switching networks, quality of service, fairness, Packet scheduling
16	Aline Mello 0001, Leandro Möller, Ney Calazans, Fernando Gehm Moraes	MultiNoC: A Multiprocessing System Enabled by a Network on Chip.	DATE	2004	DBLP DOI BibTeX RDF
16	Jorji Nonaka, Nobuyuki Kukimoto, Naohisa Sakamoto, Hiroshi Hazama, Yasuhiro Watashiba, Xuezhen Liu, Masato Ogata, Masanori Kanazawa, Koji Koyamada	Hybrid Hardware-Accelerated Image Composition for Sort-Last Parallel Rendering on Graphics Clusters with Commodity Image Compositor.	VolVis	2004	DBLP DOI BibTeX RDF	Sort-Last, Hardware-Assisted, Cluster Computing, Parallel Rendering, Image Compositing
16	Sharad Jaiswal, Arnold L. Rosenberg, Donald F. Towsley	Comparing the Structure of Power-Law Graphs and the Internet AS Graph.	ICNP	2004	DBLP DOI BibTeX RDF	AS Graph, power-law graphs, Internet Topology
16	Mustafa Çakir, Eike Grimpe, Wolfgang Nebel	HW-Driven Emulation with Automatic Interface Generation.	FPL	2003	DBLP DOI BibTeX RDF
16	José Carlos Sancho, Juan Carlos Martínez, Antonio Robles, Pedro López 0001, José Flich, José Duato	Performance Evaluation of COWs under Real Parallel Application.	IPDPS	2003	DBLP DOI BibTeX RDF	real parallel applications, routing algorithms, irregular topologies, execution-driven simulation, COWs
16	Douglas C. Sicker	Applying a Layered Policy Model to IP Based Voice Services.	HICSS	2003	DBLP DOI BibTeX RDF
16	Partha Pratim Pande, Cristian Grecu, André Ivanov	High-Throughput Switch-Based Interconnect for Future SoCs.	IWSOC	2003	DBLP DOI BibTeX RDF	SoC, Wormhole Routing, Virtual Channels, Interconnect Architecture
16	Dorothy Kucar, Anthony Vannelli	InterconnectionModelling Using Distributed RLC Models.	IWSOC	2003	DBLP DOI BibTeX RDF
16	Naotaka Ohsawa, Masanori Hariyama, Michitaka Kameyama	High-Performance Field Programmable VLSI Processor Based on a Direct Allocation of a Control/Data Flow Graph.	ISVLSI	2002	DBLP DOI BibTeX RDF	FPGA, Reconfigurable processor, Two-dimensional array, Bit-serial architecture
16	Carsten Trinitis, Martin Schulz 0001, Wolfgang Karl	Boosting the Performance of Electromagnetic Simulations on a PC-Cluster.	PARELEC	2002	DBLP DOI BibTeX RDF	Electric field simulation, High voltage engineering, SCI, Parallel Efficiency, Commodity clusters
16	Joo Beom Yun, Seong Tae Jhang, Chu Shik Jhon, Cheol Won Lee	Analysis of System Performance by Changing the Ring Architecture on the Dual Ring CC-NUMA System.	ICPADS	2002	DBLP DOI BibTeX RDF
16	Jouni Riihimäki, Erno Salminen, Kimmo Kuusilinna, Timo Hämäläinen 0001	Parameter optimization tool for enhancing on-chip network performance.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
16	V. Srinivasan, Sriram Govindarajan, Ranga Vemuri	Fine-grained and coarse-grained behavioral partitioning with effective utilization of memory and design space exploration for multi-FPGA architectures.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
16	Antonio Zenteno, Víctor H. Champac, Joan Figueras	Detectability Conditions of Full Opens in the Interconnections.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	logic testing, IDDQ testing, opens, defect modeling
16	Mike Sheng, Jonathan Rose	Mixing buffers and pass transistors in FPGA routing architectures.	FPGA	2001	DBLP DOI BibTeX RDF
16	Oliver Bringmann 0001, Wolfgang Rosenstiel, Carsten Menn	Target Architecture Oriented High-Level Synthesis for Multi-FPGA Based Emulation.	DATE	2000	DBLP DOI BibTeX RDF
16	Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka	Intelligent EB Test System for Automatic VLSI Fault Tracing.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	fault tracing, electron beam test system, fault tracing, VLSI, intelligent system
16	Pierpaolo Baglietto	Euclidean Distance Transform on a Dedicated Architecture Based on a Reconfigurable Mesh Networ.	ICIAP	1999	DBLP DOI BibTeX RDF
16	Brian K. Schmidt, Monica S. Lam, J. Duane Northcutt	The interactive performance of SLIM: a stateless, thin-client architecture.	SOSP	1999	DBLP DOI BibTeX RDF
16	Chi-Chou Kao, Yen-Tai Lai	A routability and performance driven technology mapping algorithm for LUT based FPGA designs.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
16	Jianmin Li, Chung-Kuan Cheng	Routability improvement using dynamic interconnect architecture.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
16	Ju Hwan Yi, Hoon Choi, In-Cheol Park, Seung Ho Hwang, Chong-Min Kyung	Multiple Behavior Module Synthesis Based on Selective Groupings.	DATE	1998	DBLP DOI BibTeX RDF
16	Shiuann-Shiuh Lin, Yuh-Ju Lin, TingTing Hwang	Net assignment for the FPGA-based logic emulation system in the folded-Clos network structure.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
16	Chirag S. Patel, Sek M. Chai, Sudhakar Yalamanchili, David E. Schimmel	Power/Performance Trade-offs for Direct Networks.	PCRCW	1997	DBLP DOI BibTeX RDF
16	Fabrizio Petrini, Marco Vanneschi	Network Performance under Physical Constraints.	ICPP	1997	DBLP DOI BibTeX RDF
16	Tadayoshi Horita, Itsuo Takanami	A Polynomial Time Algorithm for Reconfiguring the 1 1/2 Track-Switch Model with PE and Bus faults.	ISPAN	1997	DBLP DOI BibTeX RDF	mesh arrays, the 1frac{1}{2} track-switch model, fault-tolerance, polynomial time algorithm, wafer scale integration
16	James M. Neighbors	Finding Reusable Software Components in Large Systems.	WCRE	1996	DBLP DOI BibTeX RDF	component, reuse, subsystem
16	Jiao Fan, D. Zaleta, Chung-Kuan Cheng, S. H. Lee	Physical models and algorithms for optoelectronic MCM layout.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
16	Antonio González 0001, Miguel Valero-García, Luis Díaz de Cerio	Executing Algorithms with Hypercube Topology on Torus Multicomputers.	IEEE Trans. Parallel Distributed Syst.	1995	DBLP DOI BibTeX RDF	scalable distributed memory multiprocessors, torus multicomputers, mapping of parallel algorithms, hypercubes, Graph embeddings
16	Somchai Prasitjutrakul, William J. Kubitz	A performance-driven global router for custom VLSI chip design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
16	Jeff Kramer, Jeff Magee, Morris Sloman	Configuring distributed systems.	ACM SIGOPS European Workshop	1992	DBLP DOI BibTeX RDF
16	Uma Bhattacharya, Swapan Bhattacharya	Mapping of Fault-Tolerant Permutations in Omega.	ICCI	1991	DBLP DOI BibTeX RDF
16	Matthias Passlack, Manfred Uhle, Horst Elschner	Analysis of propagation delays in high-speed VLSI circuits using a distributed line model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
16	Ishfaq Ahmad, Arif Ghafoor	A semi distributed load balancing scheme for large multicomputer systems.	SPDP	1990	DBLP DOI BibTeX RDF
16	Goos Kant, Jan van Leeuwen	The File Distribution Problem for Processor Networks.	SWAT	1990	DBLP DOI BibTeX RDF
16	Teresa H.-Y. Meng, Robert W. Brodersen, David G. Messerschmitt	Automatic synthesis of asynchronous circuits from high-level specifications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
16	James M. Purtilo	MINION: An Environment to Organize Mathematical Problem Solving.	ISSAC	1989	DBLP DOI BibTeX RDF
16	Siamak Arya, Blaine Gaither	Parallel algorithm development workbench.	SC	1988	DBLP DOI BibTeX RDF
16	Emilio Luque, Joan Sorribes, Ana Ripoll	Tuning architecture at run-time.	MICRO	1987	DBLP DOI BibTeX RDF
16	Johannes Milde, Thomas Plückebaum, Walter Ameling	Synchronous Communication of Cooperating Processes in the M5PS Multiprocessor.	CONPAR	1986	DBLP DOI BibTeX RDF
16	Laxmi N. Bhuyan, Dharma P. Agrawal	Applications of SIMD computers in signal processing.	AFIPS National Computer Conference	1982	DBLP DOI BibTeX RDF
16	Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio	MRR: Enabling fully adaptive multicast routing for CMP interconnection networks.	HPCA	2009	DBLP DOI BibTeX RDF
16	Gonzalo Zarza, Diego Lugones, Daniel Franco 0002, Emilio Luque	A Multipath Fault-Tolerant Routing Method for High-Speed Interconnection Networks.	Euro-Par	2009	DBLP DOI BibTeX RDF
16	Xiao Liu 0011, Qiang Xu 0001	Interconnection fabric design for tracing signals in post-silicon validation.	DAC	2009	DBLP DOI BibTeX RDF	trace-based debug, post-silicon validation
16	Sungjoon Jung, Tag Gon Kim	An Operation and Interconnection Sharing Algorithm for Reconfiguration Overhead Reduction Using Static Partial Reconfiguration.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
16	Olav Lysne, Sven-Arne Reinemo, Tor Skeie, Åshild Grønstad Solheim, Thomas Sødring, Lars Paul Huse, Bjørn Dag Johnsen	Interconnection Networks: Architectural Challenges for Utility Computing Data Centers.	Computer	2008	DBLP DOI BibTeX RDF
16	Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri	Adaptive Channel Buffers in On-Chip Interconnection Networks - A Power and Performance Analysis.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
16	Fei Qiao, Huazhong Yang, Gang Huang, Hui Wang 0004	Implementation of low-swing differential interface circuits for high-speed on-chip asynchronous interconnection.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	low-swing interface, differential signaling, tapered-buffer, interconnect, asynchronous circuit, low power circuit
16	Po-Tsang Huang, Wei-Li Fang, Yin-Ling Wang, Wei Hwang	Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip.	NOCS	2008	DBLP DOI BibTeX RDF	interconnnection, reliability, low power, network-on-chip
16	Pablo Abad Fidalgo, Valentin Puente, José-Ángel Gregorio	Reducing the Interconnection Network Cost of Chip Multiprocessors.	NOCS	2008	DBLP DOI BibTeX RDF	Chip Multiprocessors, Deadlock, Router Design
16	Alessandro Astolfi, Romeo Ortega	Interconnection and Damping Assignment Passivity-Based Control: Static vs dynamic state-feedback.	CDC	2008	DBLP DOI BibTeX RDF
16	Hongbing Fan, Jason Ernst, Yu-Liang Wu	Customized Reconfigurable Interconnection Networks for multiple application SOCS.	FPL	2008	DBLP DOI BibTeX RDF
16	Bin Yao, Haisen S. Li, Tian Zhou 0002, Baowei Chen	Theoretical Research on Topological Properties of Generalized K-Ary n-Cube Interconnection Network.	ICYCS	2008	DBLP DOI BibTeX RDF
16	Jung-Heum Park, Hee-Chul Kim, Hyeong-Seok Lim	On the construction of paired many-to-many disjoint path covers in hypercube-like interconnection networks with faulty elements.	IPDPS	2008	DBLP DOI BibTeX RDF
16	Zhengjia Wang, Yuhui Wang, Zhouping Yin	A Multi-physics Simulation Based Parameters Optimization for Anisotropic Conductive Adhesive Interconnection in Electronic Packaging.	ICIRA (2)	2008	DBLP DOI BibTeX RDF	Anisotropic conductive adhesive (ACA), coupled field, multi-physics simulation, optimization, reliability
16	Seulki Lee, Jerald Yoo, Hoi-Jun Yoo	A 200Mbps 0.02nJ/b dual-mode inductive coupling transceiver for cm-range interconnection.	ISCAS	2008	DBLP DOI BibTeX RDF
16	Hazem Moussa, Amer Baghdadi, Michel Jézéquel	Binary de Bruijn interconnection network for a flexible LDPC/turbo decoder.	ISCAS	2008	DBLP DOI BibTeX RDF
16	Guilherme Piêgas Koslovski, Pascale Vicat-Blanc Primet, Andrea Schwertner Charão	VXDL: Virtual Resources and Interconnection Networks Description Language.	GridNets	2008	DBLP DOI BibTeX RDF	virtual grids, network virtualization, description language
16	Cory Hawkins, Benjamin A. Small, D. Scott Wills, Keren Bergman	The Data Vortex, an All Optical Path Multicomputer Interconnection Network.	IEEE Trans. Parallel Distributed Syst.	2007	DBLP DOI BibTeX RDF	Optical switch fabrics, photonic packet switch, data vortex switch architecture, packet switching, optical switching
16	William J. Dally	Enabling Technology for On-Chip Interconnection Networks.	NOCS	2007	DBLP DOI BibTeX RDF
16	Alejandro Martínez-Vicente, Pedro Javier García, Francisco José Alfaro, José L. Sánchez 0002, José Flich, Francisco J. Quiles 0001, José Duato	Integrated QoS Provision and Congestion Management for Interconnection Networks.	Euro-Par	2007	DBLP DOI BibTeX RDF
16	Torsten Hoefler, Andre Lichei, Wolfgang Rehm	Low-Overhead LogGP Parameter Assessment for Modern Interconnection Networks.	IPDPS	2007	DBLP DOI BibTeX RDF
16	Lei Wang 0017, Yaping Lin, Yonghe Liu	Key Distribution for Group-based Sensor Deployment Using a Novel Interconnection Graph.	WOWMOM	2007	DBLP DOI BibTeX RDF
16	Sotirios Xydis, George Economakos, Kiamal Z. Pekmestzi	A Reconfigurable Arithmetic Data-path Based On Regular Interconnection.	AHS	2007	DBLP DOI BibTeX RDF
16	Aleksandr Rudkevich, Kaan Egilmez, Minghai Liu, Prashant Murti, Poonsaeng Visudhiphan, Richard Tabors, Thomas J. Overbye	Identification and Congestion Analysis of Transmission Corridors of the Eastern Interconnection.	HICSS	2007	DBLP DOI BibTeX RDF
16	Ioannis Papaefstathiou, George Kornaros, Nikolaos Chrysos	A buffered crossbar-based chip interconnection framework supporting quality of service.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	chip interconnect, quality of service, system on chip, network on chip, multi-processor, buffered crossbar
16	Seung Eun Lee, Jun Ho Bahn, Nader Bagherzadeh	Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP).	SBAC-PAD	2007	DBLP DOI BibTeX RDF
16	Crispín Gómez Requena, María Engracia Gómez, Pedro López 0001, José Duato	An Efficient Fault-Tolerant Routing Methodology for Fat-Tree Interconnection Networks.	ISPA	2007	DBLP DOI BibTeX RDF
16	Dimitris C. Vasiliadis, George E. Rizos, Costas Vassilakis	Performance Analysis of dual priority single-buffered blocking Multistage Interconnection Networks.	ICNS	2007	DBLP DOI BibTeX RDF
16	Pedro Javier García, Francisco J. Quiles 0001, José Flich, José Duato, Ian Johnson, Finbar Naven	Efficient, Scalable Congestion Management for Interconnection Networks.	IEEE Micro	2006	DBLP DOI BibTeX RDF	Regional Explicit Congestion Notification (RECN), congestion management
16	Federico Quaglio, Fabrizio Vacca, Cristiano Castellano, Alberto Tarable, Guido Masera	Interconnection framework for high-throughput, flexible LDPC decoders.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
16	Paulo S. Motta Pires, Luiz Affonso H. G. Oliveira	Security Aspects of SCADA and Corporate Network Interconnection: An Overview.	DepCoS-RELCOMEX	2006	DBLP DOI BibTeX RDF
16	Shinyoung Lim, Abdelsalam Helal	Encapsulation and Entity-Based Approach of Interconnection Between Sensor Platform and Middleware of Pervasive Computing.	UCS	2006	DBLP DOI BibTeX RDF
16	Hamed Nassar, Mohamed Ali Ahmed	Performance Analysis of Finite Buffered Multistage Interconnection Networks Routing Two-Class Traffic.	ISCC	2006	DBLP DOI BibTeX RDF
16	Thomas Kuhn 0001, Philipp Becker	A Simulator Interconnection Framework for the Accurate Performance Simulation of SDL Models.	SAM	2006	DBLP DOI BibTeX RDF
16	Michal P. Karpowicz, Krzysztof Malinowski 0001	Dynamic Resource Allocation Mechanism for Network Interconnection Management.	International Conference on Computational Science (3)	2006	DBLP DOI BibTeX RDF
16	Mukesh Ranjan, Ranga Vemuri	Exact hierarchical symbolic analysis of large analog networks using a general interconnection template.	ISCAS	2006	DBLP DOI BibTeX RDF
16	Kostas Siozios, Dimitrios Soudris, Adonios Thanailakis	A novel methodology for designing high-performance and low-power FPGA interconnection targeting DSP applications.	ISCAS	2006	DBLP DOI BibTeX RDF
16	George Jie Yuan, Nabil H. Farhat, Jan Van der Spiegel	A CMOS monolithic implementation of a nonlinear interconnection module for a corticonic network.	ISCAS	2006	DBLP DOI BibTeX RDF
16	Jung-Heum Park, Hyeong-Seok Lim, Hee-Chul Kim	Panconnectivity and Pancyclicity of Hypercube-Like Interconnection Networks with Faulty Elements.	ISPA Workshops	2006	DBLP DOI BibTeX RDF
16	Carlos Eduardo da Silva, Adilson B. Lopes, Glêdson Elias da Silveira, Guido Lemos de Souza Filho, Maurício F. Magalhães	A Component Interconnection Model for Interactive Digital Television Systems.	AINA (1)	2006	DBLP DOI BibTeX RDF
16	Nen-Chung Wang, Chih-Ping Chu	An Efficient Tree-Based Multicasting Algorithm on Wormhole-Routed Star Graph Interconnection Networks Embedded with Hamiltonian Path.	J. Supercomput.	2005	DBLP DOI BibTeX RDF	parallel computing, multicast, wormhole routing, star graphs, tree-based routing
16	José Duato, Ian Johnson, José Flich, Finbar Naven, Pedro Javier García, Teresa Nachiondo Frinós	A New Scalable and Cost-Effective Congestion Management Strategy for Lossless Multistage Interconnection Networks.	HPCA	2005	DBLP DOI BibTeX RDF