Search results for "memories"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
13	Hao Che, Zhijun Wang 0001, Kai Zheng 0003, Bin Liu 0001	DRES: Dynamic Range Encoding Scheme for TCAM Coprocessors.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Composite structures, Storage/repositories, Network repositories/data mining/backup, Associative memories
13	Mazen Kharbutli, Yan Solihin	Counter-Based Cache Replacement and Bypassing Algorithms.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Cache Bypassing, Counter-Based Algorithms, Cache memories, Cache Replacement, Cache Misses
13	Neila Mezghani, Amar Mitiche, Mohamed Cheriet	Bayes Classification of Online Arabic Characters by Gibbs Modeling of Class Conditional Densities.	IEEE Trans. Pattern Anal. Mach. Intell.	2008	DBLP DOI BibTeX RDF	and, Clustering, classification, association rules, Associative memories
13	Gerard Oleksik, Lorna M. Brown	Sonic gems: exploring the potential of audio recording as a form of sentimental memory capture.	BCS HCI (1)	2008	DBLP DOI BibTeX RDF	audio capture, memories, audio, sound
13	Federico Neri, Angelo Priamo	SPYWatch, Overcoming Linguistic Barriers in Information Management.	EuroISI	2008	DBLP DOI BibTeX RDF	open source intelligence, multilingual lexicons, supervised clustering, natural language processing, machine translation, focused crawling, functional analysis, unsupervised clustering, morphological analysis, syntactic analysis, translation memories
13	Luiza M. N. Coutinho, José Leandro D. Mendes, Carlos A. P. S. Martins	Dynamically Reconfigurable Split Cache Architecture.	ReConFig	2008	DBLP DOI BibTeX RDF	Computer Architecture, Reconfigurable Computing, Cache memories
13	Neta Aizenbud-Reshef, Eran Belinsky, Michal Jacovi, David Laufer, Vladimir Soroka	Pensieve: augmenting human memory.	CHI Extended Abstracts	2008	DBLP DOI BibTeX RDF	augmenting memory, experience logging, pensieve, mobile phones, sharing memories
13	Mario Aldape-Pérez, Israel Román-Godínez, Oscar Camacho Nieto	Thresholded Learning Matrix for Efficient Pattern Recalling.	CIARP	2008	DBLP DOI BibTeX RDF	Lernmatrix, Supervised Learning, Pattern Classification, Associative Memories, Dynamic Threshold
13	Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser	Utilizing shared data in chip multiprocessors with the nahalal architecture.	SPAA	2008	DBLP DOI BibTeX RDF	chip multiprocessors, cache memories
13	Yutao Zhong 0001, Steven G. Dropsho, Xipeng Shen, Ahren Studer, Chen Ding 0001	Miss Rate Prediction Across Program Inputs and Cache Configurations.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	optimization, compilers, Cache memories, modeling techniques, performance analysis and design aids
13	Jaydeep Marathe, Frank Mueller 0001	Source-Code-Correlated Cache Coherence Characterization of OpenMP Benchmarks.	IEEE Trans. Parallel Distributed Syst.	2007	DBLP DOI BibTeX RDF	simulation, Cache memories, SMPs, program instrumentation, coherence protocols, dynamic binary rewriting
13	Jaehyuk Huh 0001, Changkyu Kim, Hazim Shafi, Lixin Zhang 0002, Doug Burger, Stephen W. Keckler	A NUCA Substrate for Flexible CMP Cache Sharing.	IEEE Trans. Parallel Distributed Syst.	2007	DBLP DOI BibTeX RDF	Multiprocessor systems, cache memories, adaptable architectures
13	Ricardo Barrón, Humberto Sossa, Benjamín Cruz	A New Algorithm for Training Multi-layered Morphological Networks.	CIARP	2007	DBLP DOI BibTeX RDF	maximal support neighborhoods, Associative memories, Morphological neural networks
13	Rui M. Jesus, Ricardo J. Dias, Rute Frias, Nuno Correia 0001	Geographic image retrieval in mobile guides.	GIR	2007	DBLP DOI BibTeX RDF	geographic image retrieval, mobile guides, personal memories
13	Sandro Romani, Daniel J. Amit, Gianluigi Mongillo	Mean-field analysis of selective persistent activity in presence of short-term synaptic depression.	J. Comput. Neurosci.	2006	DBLP DOI BibTeX RDF	Mean-field analysis, Overlapping memories, Selective persistent activity, STD, Spiking neuron
13	Moon-Hee Choi, Woo-Chan Park, Francis Neelamkavil, Tack-Don Han, Shin-Dug Kim	An Effective Visibility Culling Method Based on Cache Block.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	visible/surface algorithms, Computer graphics, cache memories, graphics processors
13	Hwansoo Han, Chau-Wen Tseng	Exploiting Locality for Irregular Scientific Codes.	IEEE Trans. Parallel Distributed Syst.	2006	DBLP DOI BibTeX RDF	inspector/executor, data reordering, computation reordering, Compiler optimization, cache memories
13	Vilas Sridharan, Hossein Asadi 0001, Mehdi Baradaran Tahoori, David R. Kaeli	Reducing Data Cache Susceptibility to Soft Errors.	IEEE Trans. Dependable Secur. Comput.	2006	DBLP DOI BibTeX RDF	refresh, refetch, Fault tolerance, reliability, cache memories, soft errors, error modeling
13	Corina Sas, Alan J. Dix	Designing for collective remembering.	CHI Extended Abstracts	2006	DBLP DOI BibTeX RDF	memory technology, interaction design, episodic memory, collective memories
13	Jaume Abella 0001, Antonio González 0001	Heterogeneous way-size cache.	ICS	2006	DBLP DOI BibTeX RDF	adaptive, low power, cache memories, set-associative
13	Cameron McNairy, Rohit Bhatia	Montecito: A Dual-Core, Dual-Thread Itanium Processor.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Reliability, Power Management, Cache memories, Multithreaded processors, Testing and Fault-Tolerance
13	Philip Machanick	The Value of a Small Microkernel for Dreamy Memory and the RAMpage Memory Hierarchy.	J. Comput. Sci. Technol.	2005	DBLP DOI BibTeX RDF	low-power design, cache memories, virtual memory, microkernels, main memory
13	Konstantinos Koutroumbas	COMAX: A Cooperative Method for Determining the Position of the Maxima.	Neural Process. Lett.	2005	DBLP DOI BibTeX RDF	feedforward neural network architectures, Hamming Max-net, recurrent neural network architectures, selection of the position of the maximum, associative memories
13	Jaume Abella 0001, Antonio González 0001, Xavier Vera, Michael F. P. O'Boyle	IATAC: a smart predictor to turn-off L2 cache lines.	ACM Trans. Archit. Code Optim.	2005	DBLP DOI BibTeX RDF	turning off cache lines, low power, Cache memories, L2 cache
13	Gian Carlo Cardarilli, Fabrizio Lombardi, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano	A Comparative Evaluation of Designs for Reliable Memory Systems.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	mass memories, fault tolerance, Markov model, reed solomon codes
13	Philip Jacob 0001, Okan Erdogan, Aamir Zia, Paul M. Belemjian, Russell P. Kraft, John F. McDonald 0001	Predicting the Performance of a 3D Processor-Memory Chip Stack.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	Simulation, Cache memories, Performance of Systems
13	Akihito Sakanaka, Seiichirou Fujii, Toshinori Sato	A leakage-energy-reduction technique for highly-associative caches in embedded systems.	SIGARCH Comput. Archit. News	2004	DBLP DOI BibTeX RDF	cache memories, embedded processors, leakage current
13	Jingling Xue, Xavier Vera	Efficient and Accurate Analytical Modeling of Whole-Program Data Cache Behavior.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	performance evaluation, analytical modeling, cache memories, data locality, Modeling techniques
13	Victor M. DeLaLuz, Ismail Kadayif, Mahmut T. Kandemir, Ugur Sezer	Access Pattern Restructuring for Memory Energy.	IEEE Trans. Parallel Distributed Syst.	2004	DBLP DOI BibTeX RDF	banked memories, embedded systems, Compiler optimization, energy consumption, access pattern
13	Kubilay Atasu, Luca Breveglieri, Marco Macchetti	Efficient AES implementations for ARM based platforms.	SAC	2004	DBLP DOI BibTeX RDF	ARM microprocessor, AES, cache memories, code optimisation
13	Antonis Papanikolaou, Miguel Miranda, Francky Catthoor	Overcoming the "Memory Wall" by improved system design exploration and a link to process technology options.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	combined system design and process technology exploration, optimal energy/delay trade-off exploration in memories
13	Michel Dubois 0001	Fighting the memory wall with assisted execution.	Conf. Computing Frontiers	2004	DBLP DOI BibTeX RDF	prefetching, cache memories, superscalar processors, simultaneous multithreading, latency tolerance
13	Yiannis Andreopoulos, Peter Schelkens, Gauthier Lafruit, Kostas Masselos, Jan Cornelis 0001	High-Level Cache Modeling for 2-D Discrete Wavelet Transform Implementations.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	discrete wavelet transform implementations, cache memories, theoretical modeling
13	Wei Zhang 0002, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin	Performance, energy, and reliability tradeoffs in replicating hot cache lines.	CASES	2003	DBLP DOI BibTeX RDF	cache reliability, line replication, cache memories, leakage power
13	Carlos Molina, Carles Aliagas, Montse Garcia 0002, Antonio González 0001, Jordi Tubella	Non redundant data cache.	ISLPED	2003	DBLP DOI BibTeX RDF	value replication, low power, compression, cache memories
13	Sybille Hellebrand, Hans-Joachim Wunderlich, Alexander A. Ivaniuk, Yuri V. Klimets, Vyacheslav N. Yarmolik	Efficient Online and Offline Testing of Embedded DRAMs.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	online checking, BIST, systems-on-a-chip, Embedded memories
13	Premkumar T. Devanbu, Stuart G. Stubblebine	Stack and Queue Integrity on Hostile Platforms.	IEEE Trans. Software Eng.	2002	DBLP DOI BibTeX RDF	correctness of memories, oblivious ram, security, data structures, software protection
13	Victor De La Luz, Mahmut T. Kandemir, Ibrahim Kolcu	Automatic data migration for reducing energy consumption in multi-bank memory systems.	DAC	2002	DBLP DOI BibTeX RDF	multi-bank memories, energy consumption, data migration
13	Claude Limousin, Julien Sébot, Alexis Vartanian, Nathalie Drach-Temam	Improving 3D geometry transformations on a simultaneous multithreaded SIMD processor.	ICS	2001	DBLP DOI BibTeX RDF	SIMD extensions, cache memories, parallel rendering, data prefetching, SMT, applications specific architectures
13	Alexis Vartanian, Jean-Luc Béchennec, Nathalie Drach-Temam	The Best Distribution for a Parallel OpenGL 3D Engine with Texture Caches.	HPCA	2000	DBLP DOI BibTeX RDF	texture mapping, Cache memories, parallel rendering, multiprocessing, application specific architecture
13	Tong Sun, Qing Yang 0001	A Comparative Analysis of Cache Designs for Vector Processing.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	simulation, Performance evaluation, benchmarks, memory hierarchy, cache memories, vector processing
13	Somnath Ghosh, Margaret Martonosi, Sharad Malik	Cache miss equations: a compiler framework for analyzing and tuning memory behavior.	ACM Trans. Program. Lang. Syst.	1999	DBLP DOI BibTeX RDF	optimization, compilation, program transformation, cache memories
13	Saleh E. Abdullahi, Graem A. Ringwood	Garbage Collecting the Internet: A Survey of Distributed Garbage Collection.	ACM Comput. Surv.	1998	DBLP DOI BibTeX RDF	automatic storage reclamation, distributed object-oriented management, distributed, object-oriented databases, memory management, distributed file systems, distributed memories, network communication, reference counting
13	Abhijit K. Choudhury, Ellen L. Hahne	A new buffer management scheme for hierarchical shared memory switches.	IEEE/ACM Trans. Netw.	1997	DBLP DOI BibTeX RDF	backpressure, buffer memories, hierarchical switch, pushout, asynchronous transfer mode, memory management, shared memory systems, priorities, queuing analysis, losses
13	Alberto Faro, Daniela Giordano	From Documenting Design to Design by Documenting.	SIGDOC	1997	DBLP DOI BibTeX RDF	design memories, case-based reasoning, scenario-based design
13	Bin Wei	Comments on "A Multiaccess Frame Buffer Architecture".	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	Frame buffers, parallel memory architecture, computer graphics, interleaved memories, storage schemes
13	Sihai Xiao, Xiaofa Shih, Guilang Feng, T. R. N. Rao	A Generalization of the Single b-Bit Byte Error Correcting and Double Bit Error Detecting Codes for High-Speed Memory Systems.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	High-speed memories, byte error-correcting/detecting codes, companion matrix, subfields/cosets, primitive polynomials
13	Mayez A. Al-Mouhamed, Steven S. Seiden	Minimization of Memory and Network Contention for Accessing Arbitrary Data Patterns in SIMD Systems.	IEEE Trans. Computers	1996	DBLP DOI BibTeX RDF	NP-completeness, multistage networks, storage schemes, parallel memories, Memory conflicts
13	Avraham Leff, Joel L. Wolf, Philip S. Yu	Efficient LRU-Based Buffering in a LAN Remote Caching Architecture.	IEEE Trans. Parallel Distributed Syst.	1996	DBLP DOI BibTeX RDF	performance evaluation, local area networks, Memory management, memory hierarchies, distributed memories, distributed database systems
13	Douglas H. Summerville, José G. Delgado-Frias, Stamatis Vassiliadis	A Flexible Bit-Pattern Associative Router for Interconnection Networks.	IEEE Trans. Parallel Distributed Syst.	1996	DBLP DOI BibTeX RDF	Routing algorithm execution, adaptive routing and flexible routers, interconnection networks, associative memories, oblivious routing
13	Ad J. van de Goor, Georgi Gaydadjiev, V. G. Mikitjuk, Vyacheslav N. Yarmolik	March LR: a test for realistic linked faults.	VTS	1996	DBLP DOI BibTeX RDF	disturb faults, March LR, March LRD, March LRDD, fault diagnosis, integrated circuit testing, fault models, fault coverage, march tests, integrated memory circuits, semiconductor memories, linked faults
13	Bapiraju Vinnakota	Implementing Multiplication with Split Read-Only Memory.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	table of squares, Multiplication, squares, table look-up, read only memories
13	Kay A. Robbins, Steven Robbins	Buffered Banks in Multiprocessor Systems.	IEEE Trans. Computers	1995	DBLP DOI BibTeX RDF	Buffered memories, logical memory banks, vector processors, Cray Y-MP, memory conflicts
13	Marc D. Riedel, Janusz Rajski	Fault coverage analysis of RAM test algorithms.	VTS	1995	DBLP DOI BibTeX RDF	RAM test algorithms, flexible software analysis program, arbitrary test sequences, coverage statistics, functional cell-array faults, fault state transition conditions, representative fault classes, fault diagnosis, integrated circuit testing, fault coverage, random-access storage, integrated memory circuits, semiconductor memories, test algorithms
13	Wen-mei W. Hwu, Thomas M. Conte	The Susceptibility of Programs to Context Switching.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	program susceptibility, memory system performance degradation, single-pass method, recurrence/conflict model, voluntary context switches, involuntary context switches, length distribution, address referencing, cache flushing, SPEC89 benchmarks, simulation, performance evaluation, performance analysis, memory hierarchy, cache memories, memory architecture, buffer storage, multiprogramming, multiprogramming, design space, context switching
13	Jean Vuillemin	On Circuits and Numbers.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	PROM, 2-adic integers, synchronous decision diagrams, BDD constructs, bit-serial circuits, reset signals, 2Z, arithmetic synthesis f, periodic binary constants, deeply binding synchronous enable, combinational circuit semantics, arbitrary precision, programmable active memories, specification languages, sequential circuits, combinational circuits, digital arithmetic, logic CAD, adders, digital circuits, arithmetic, combinatorial circuits, synchronous circuits, continuous functions, rational numbers
13	Montse Peiron, Mateo Valero, Eduard Ayguadé	Synchronized access to streams in SIMD vector multiprocessors.	International Conference on Supercomputing	1994	DBLP DOI BibTeX RDF	SIMD vector multiprocessors, multi-module memories, vectors with constant stride, interconnection networks, conflict-free access
13	Jesse Zhixi Fang, Mi Lu	An Iteration Partition Approach for Cache or Local Memory Thrashing on Parallel Processing.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	iteration partition approach, local cache memory, write-invalidate protocol, local memory thrashing, nested parallel loops, array element accesses, enclosed loop indexes, correct iteration, nested loop structures, parallel programs, parallel programming, iterative methods, memory hierarchies, storage management, cache coherence, memory architecture, parallel loops, local memories, loop nests, parallel code
13	Dominique Thiébaut, Harold S. Stone	Improving Disk Cache Hit-Ratios Through Cache Partitioning.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	fully associative cache memories, buffer storage, adaptive algorithm, cache storage, content-addressable storage, cache partitioning, magnetic disc storage, hit-ratios, disk cache, queuing network model
13	Mateo Valero, Tomás Lang, Eduard Ayguadé	Conflict-free access of vectors with power-of-two strides.	ICS	1992	DBLP DOI BibTeX RDF	multi-module memories, out-of-order access, power-of-two strides, vector processors, conflict-free access, storage schemes
13	Bruno Ciciani	Redundancy effect on yield of binary tree RAMs.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	semiconductor memory design, VLSI chip design, yield evaluation, Fault-tolerant memories
13	Kifung C. Cheung, Gurindar S. Sohi, Kewal K. Saluja, Dhiraj K. Pradhan	Design and Analysis of a Gracefully Degrading Interleaved Memory System.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	gracefully degrading interleaved memory system, digital storage, fault tolerant computing, trace-driven simulation, interleaved memories, reconfiguration scheme
13	René David, Antoine Fuentes, Bernard Courtois	Random Pattern Testing Versus Deterministic Testing of RAM's.	IEEE Trans. Computers	1989	DBLP DOI BibTeX RDF	random pattern testing, double faults, classical fault models, multiple-coupling faults, Markov chains, integrated circuit testing, Markov processes, random-access storage, RAMs, test patterns, parameters, random-access memories, pattern-sensitive faults, deterministic testing, single faults
13	Eric Regener	A Transition Sequence Generator for RAM Fault Detection.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	transition sequence generator, RAM fault detection, n-bit CMOS memories, test address sequence, ordered pair, next-state generator, integrated circuit testing, logic circuit, CMOS integrated circuits, random-access storage, integrated memory circuits
13	Harry A. G. Wijshoff, Jan van Leeuwen	On Linear Skewing Schemes and d-Ordered Vectors.	IEEE Trans. Computers	1987	DBLP DOI BibTeX RDF	d-ordered vectors, linear skewing schemes, SIMD machines, Conflict-free access, parallel memories, two-dimensional arrays
13	James E. Smith, James R. Goodman	Instruction Cache Replacement Policies and Organizations.	IEEE Trans. Computers	1985	DBLP DOI BibTeX RDF	fully associative, loop model, Cache memories, replacement algorithms, memory organization, direct-mapped, set-associative
13	Laxmi N. Bhuyan	An Analysis of Processor-Memory Interconnection Networks.	IEEE Trans. Computers	1985	DBLP DOI BibTeX RDF	multiprocessor performance, favorite memories, Bandwidth, multistage interconnection networks, crossbar switches
13	Balakrishna R. Iyer, J. Bartlett Sinclair	Dynamic Memory Interconnections for Rapid Access.	IEEE Trans. Computers	1984	DBLP DOI BibTeX RDF	Access algorithm, interconnection networks, access times, dynamic memories
13	Larry A. Dunning, Murali R. Varanasi	Code Constructions for Error Control in Byte Organized Memory Systems.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	SEC-BED codes, Byte errors, byte organization, package failures, fault tolerance, memories, error-correcting codes, error-detecting codes, linear codes
13	Christos A. Papachristou	Direct Implementation of Discrete and Residue-Based Functions Via Optimal Encoding: A Programmable Array Logic Approach.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	Addition and multiplication mod M, discrete functions, optimal residue encoding, PLA's, programmable array logic (PAL), residue-based functions, ROM's, VLSI, associative memories
13	Kin-Man Chung, Fabrizio Luccio, C. K. Wong	On the Complexity of Sorting in Magnetic Bubble Memory Systems.	IEEE Trans. Computers	1980	DBLP DOI BibTeX RDF	control states, sorting, switches, Analysis of algorithm, magnetic bubble memories
13	Malcolm C. Easton, Peter A. Franaszek	Use Bit Scanning in Replacement Decisions.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	operating system overhead, page fault rate, paged memories, paged storage, page replacement algorithms, Miss ratio
13	B. Ramakrishna Rau	Interleaved Memory Bandwidth in a Model of a Muyltiprocessor Computer System.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	performance evaluation, multiprocessors, Analytical models, memory bandwidth, memory interference, interleaved memories
13	Bert Speelpenning, Jürg Nievergelt	A Simple Model of Processor - Resource Utilization in Networks of Communicating Modules.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	performance analysis, interaction model, resource utilization, shared resources, Interleaved memories
13	Sudhakar M. Reddy	A Class of Linear Codes for Error Control in Byte-per-Card Organized Digital Systems.	IEEE Trans. Computers	1978	DBLP DOI BibTeX RDF	byte-error detecting codes, byte-per-card systems, memories, linear codes, Binary codes
13	Brian Randell, C. J. Kuehner	Dynamic storage allocation systems.	Commun. ACM	1968	DBLP DOI BibTeX RDF	addressing mechanisms, storage fragmentation, segmentation, storage management, virtual memories, paging, multiprogramming, storage allocation, storage hierarchies
13	G. Oppenheimer, Norman Weizer	Resource management for a medium scale time-sharing operating system.	Commun. ACM	1968	DBLP DOI BibTeX RDF	operating systems, resource management, memory management, task scheduling, virtual memories, paging, time-sharing, system simulation
12	Yibo Chen, Jishen Zhao, Yuan Xie 0001	3D-nonFAR: three-dimensional non-volatile FPGA architecture using phase change memory.	ISLPED	2010	DBLP DOI BibTeX RDF	non-volatile FPGA, phase-change memory, 3D IC
12	Stamatis G. Kavadias, Manolis Katevenis, Michail Zampetakis, Dimitrios S. Nikolopoulos	On-chip communication and synchronization mechanisms with cache-integrated network interfaces.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	explicit communication, inter-processor synchronization, cache, network interface
12	Kuo-Kun Tseng, Yuan-Cheng Lai, Ying-Dar Lin, Tsern-Huei Lee	A fast scalable automaton-matching accelerator for embedded content processors.	ACM Trans. Embed. Comput. Syst.	2009	DBLP DOI BibTeX RDF	Aho-Corasick, String matching, Bloom filter, automaton, content filtering
12	Masashi Ishibashi, Yoshio Nakatani	Metadata-Based Reminder Classification in Reminiscence Engineering.	HCI (8)	2009	DBLP DOI BibTeX RDF	ontology, classification, metadata, personal memory
12	Xinyu Li, Omar Hammami	Small scale multiprocessor soft IP (SSM IP): single FPGA chip area and performance evaluation.	FPGA	2009	DBLP DOI BibTeX RDF	fpga, multiprocessor, network on chip
12	Pei-Yu Chi, Xiao Xiao, Keywon Chung, Carnaven Chiu	Burn your memory away: one-time use video capture and storage device to encourage memory appreciation.	CHI Extended Abstracts	2009	DBLP DOI BibTeX RDF	appreciation, augmented object, burn, everyday object, matchstick, ubiquitous computing, memory, fire, video capture
12	Nikolaos Mavridis, Chandan Datta, Shervin Emami, Chiraz BenAbdelkader, Andry Tanoto, Tamer Rabie	FaceBots: social robots utilizing facebook.	HRI	2009	DBLP DOI BibTeX RDF	conversational robots, human-robot interaction, social robots
12	Nikolaos Mavridis, Chandan Datta, Shervin Emami, Andry Tanoto, Chiraz BenAbdelkader, Tamer Rabie	FaceBots: robots utilizing and publishing social information in facebook.	HRI	2009	DBLP DOI BibTeX RDF	conversational robots, human-robot interaction, social robots
12	Martin Dimitrov, Mike Mantor, Huiyang Zhou	Understanding software approaches for GPGPU reliability.	GPGPU	2009	DBLP DOI BibTeX RDF	reliability, GPGPU
12	Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn, Christian Schlegel	A Compact and Accurate Gaussian Variate Generator.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
12	Vamsi Vankamamidi, Marco Ottavi, Fabrizio Lombardi	A Serial Memory by Quantum-Dot Cellular Automata (QCA).	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	memory architecture, emerging technologies, QCA
12	Isabelle Bichindaritz	Memory Structures and Organization in Case-Based Reasoning.	Case-Based Reasoning on Images and Signals	2008	DBLP DOI BibTeX RDF
12	Dominic Hillenbrand, Jörg Henkel	Block cache for embedded systems.	ASP-DAC	2008	DBLP DOI BibTeX RDF
12	Kazuteru Miyazaki, Shigenobu Kobayashi	Proposal of Exploitation-Oriented Learning PS-r#.	IDEAL	2008	DBLP DOI BibTeX RDF
12	Alain Berthoz	Cognitive strategies for spatial memory of navigation: studies combining virtual reality and brain imaging.	VRST	2008	DBLP DOI BibTeX RDF
12	Wei Wang, Qigang Wang, Wei Wei, Dong Liu	Evaluating Heterogeneous Memory Model by Realistic Trace-Driven Hardware/Software Co-simulation.	Euro-Par	2008	DBLP DOI BibTeX RDF	Performance model, Memory architecture, Trace-driven simulation
12	Ying Yu, Raymond R. Hoare, Alex K. Jones	A CAM-based intrusion detection system for single-packet attack detection.	IPDPS	2008	DBLP DOI BibTeX RDF
12	Jiri Barnat, Lubos Brim, Stefan Edelkamp, Damian Sulewski, Pavel Simecek	Can Flash Memory Help in Model Checking?	FMICS	2008	DBLP DOI BibTeX RDF
12	Sain-Zee Ueng, Melvin Lathara, Sara S. Baghsorkhi, Wen-mei W. Hwu	CUDA-Lite: Reducing GPU Programming Complexity.	LCPC	2008	DBLP DOI BibTeX RDF
12	Paul Pao-Fang Cheng	A Knowledge-Based Tool for Generating and Verifying Hardware-Ready Embedded Memory Models.	ISQED	2008	DBLP DOI BibTeX RDF
12	Avijit Dutta, Abhijit Jas	Combinational Logic Circuit Protection Using Customized Error Detecting and Correcting Codes.	ISQED	2008	DBLP DOI BibTeX RDF	EDAC, adhoc code, customizable codes, ECC
12	Balázs Ujfalussy, Péter Erös, Zoltán Somogyvári, Tamás Kiss	Episodes in Space: A Modeling Study of Hippocampal Place Representation.	SAB	2008	DBLP DOI BibTeX RDF	space representation, spatial memory, hippocampus, computational neuroscience, episodic memory, grid cell, place cell
12	Ching-Tsan Chiang, Yu-Bin Lin	The learning convergence of High Dimension CMAC_GBF.	IJCNN	2008	DBLP DOI BibTeX RDF