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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 389 occurrences of 238 keywords
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Results
Found 900 publication records. Showing 900 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Yoann Guillemenet, Syed Zahid Ahmed, Lionel Torres, Alexandre Martheley, Julien Eydoux, Jean-Baptiste Cuelle, Laurent Rouge, Gilles Sassatelli |
MRAM Based eFPGAs: Programming and Silicon Flows, Exploration Environments, MRAM Current State in Industry and Its Unique Potentials for FPGAs. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
FPGA, Dynamic Reconfiguration, MRAM, non volatility |
1 | Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez |
Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
MFPGA, Timing balance, WDDL, Routing, Placement, Differential Power Analysis |
1 | Martín Vázquez 0001, Gustavo Sutter, Gery Bioul, Jean-Pierre Deschamps |
Decimal Adders/Subtractors in FPGA: Efficient 6-input LUT Implementations. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
BCD, add/subtract, addtion, FPGA, subtraction, decimal arithmetic |
1 | Rafael A. Arce-Nazario, Edusmildo Orozco, Dorothy Bollman |
A Systolic Array Based Architecture for Implementing Multivariate Polynomial Interpolation Tasks. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
multivariate polynomial interpolation, parameterizable architectures, bioinformatic applications, reverse engineering problem for gene networks, systolic arrays |
1 | Julien Delorme, Amor Nafkha, Pierre Leray, Christophe Moy |
New OPBHWICAP Interface for Realtime Partial Reconfiguration of FPGA. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
FPGA, NoC, SDR, Partial Reconfiguration |
1 | Solmaz Ghaznavi, Catherine H. Gebotys, Reouven Elbaz |
Efficient Technique for the FPGA Implementation of the AES MixColumns Transformation. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
MixColumns, FPGA, architecture, AES, LUT |
1 | Armando Astarloa, Jesús Lázaro 0001, Unai Bidarte, Aitzol Zuloaga, Jaime Jimenez |
PCIREX: A Fast Prototyping Platform for TMR Dynamically Reconfigurable Systems. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
Fault Tolerance, FPGA, Dynamic Reconfiguration, Partial Reconfiguration, TMR, Self-repairing |
1 | Jorge Surís, Adolfo Recio, Peter Athanas |
Enhancing the Productivity of Radio Designers with RapidRadio. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
Signal classification, FPGA, Synthesis, Automation |
1 | Adwait Gupte, Phillip H. Jones |
Hotspot Mitigation Using Dynamic Partial Reconfiguration for Improved Performance. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Oscar Alvarado Nava, Arturo Díaz-Pérez |
Acceleration of Fractal Image Compression Using the Hardware-Software Co-design Methodology. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
FPGA, Hardware-Software Co-Design, Fractal Compression |
1 | Sven Eisenhardt, Thomas Schweizer, Andreas Bernauer, Tommy Kuhn, Wolfgang Rosenstiel |
Prevention of Hot Spot Development on Coarse-Grained Dynamically Reconfigurable Architectures. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
temperature optimization, reliability, reconfigurable computing, hot spot, coarse-grained |
1 | Muhammad Aqeel Wahlah, Kees Goossens |
Composable and Persistent-State Application Swapping on FPGAs Using Hardwired Network on Chip. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Stefan Döbrich, Christian Hochberger |
Effects of Simplistic Online Synthesis for AMIDAR Processors. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
online synthesis, dynamic reconfiguration |
1 | Antoine Trouvé, Lovic Gauthier, Takayuki Kando, Benoit Ryder, Sebastien Pouzols, Pradeep Rao, Norifumi Yoshimatsu, Kazuaki J. Murakami |
Accelerating Cryptographic Applications Using Dynamically Reconfigurable Functional Units. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
compiler, Dynamic reconfiguration, accelerator |
1 | Carlos Minchola, Gustavo Sutter |
A FPGA IEEE-754-2008 Decimal64 Floating-Point Multiplier. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
|
1 | John A. Kalomiros, John N. Lygouras |
A Reconfigurable Architecture for Stereo-Assisted Detection of Point-Features for Robot Mapping. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
Real-Time systems, Machine vision, Reconfigurable hardware, Robot mapping |
1 | Mingjie Lin, Yaling Ma |
Base-Calling in DNA Pyrosequencing with Reconfigurable Bayesian Network. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
pyrosequencing, performance, FPGA |
1 | Viktor K. Prasanna, Lionel Torres, René Cumplido (eds.) |
ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 9-11 December 2009, Proceedings |
ReConFig |
2009 |
DBLP BibTeX RDF |
|
1 | Abel G. Silva-Filho, Sidney M. L. Lima, F. C. L. Cox |
Low Power RTL Exploration Mechanism Based on the Cache Parameters. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
Exploration Mechanism, NIOSII, FPGA, Embedded Systems, SoC, Low Power Design, Cache Memory |
1 | Daniel Llamocca, Marios S. Pattichis, G. Alonzo Vera |
A Dynamically Reconfigurable Platform for Fixed-Point FIR Filters. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
FPGA, hardware, FIR filters, distributed arithmetic, dynamic partial reconfiguration |
1 | André Stauffer, Joël Rossier |
Bio-inspired Self-Testing and Self-Organizing Bit Slice Processors. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
configurable molecule, cicatrization, test, configuration, regeneration |
1 | Jiang Jiang, Vincent Mirian, Kam Pui Tang, Paul Chow, Zuocheng Xing |
Matrix Multiplication Based on Scalable Macro-Pipelined FPGA Accelerator Architecture. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
temporal parallelism, macro-pipeline, FPGA accelerator, matrix multiplication |
1 | Pablo Huerta, Javier Castillo, César Pedraza, Javier Cano 0001, José Ignacio Martínez |
Symmetric Multiprocessor Systems on FPGA. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
FPGA, Multiprocessor, SMP |
1 | Gustavo Sutter, Elias Todorovich, Gery Bioul, Martín Vázquez 0001, Jean-Pierre Deschamps |
FPGA Implementations of BCD Multipliers. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
BCD arithmetic, IEEE-745 standard |
1 | Hideki Yamada, Yasunori Osana, Tomoya Ishimori, Tomonori Ooya, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, Noriko Hiroi, Hideharu Amano, Yuichiro Shibata, Kiyoshi Oguri |
A Modular Approach to Heterogeneous Biochemical Model Simulation on an FPGA. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
Biochemistry, Kinetic simulation, FPGA, Design automation |
1 | Vlad Mihai Sima, Koen Bertels |
Runtime Memory Allocation in a Heterogeneous Reconfigurable Platform. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
heterogeneous, memory allocation, runtime, scratch pad memory |
1 | Lei Wang 0003, Lei Chen 0010, Zhiping Wen 0001, Huabo Sun, Shuo Wang |
A Novel High-Density Single-Event Upset Hardened Configurable SRAM Applied to FPGA. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
Heavy ion, CSRAM, Medici, FPGA, HSPICE |
1 | Shivam Bhasin, Jean-Luc Danger, Florent Flament, Tarik Graba, Sylvain Guilley, Yves Mathieu, Maxime Nassar, Laurent Sauvage, Nidhal Selmane |
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Nathalie Bochard, Florent Bernard, Viktor Fischer |
Observing the Randomness in RO-Based TRNG. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
FPGA, Jitter, Ring Oscillators, True Random Number Generators |
1 | Arghavan Asad, Amir Ehsani Zonouz, Mehrdad Seyrafi, Mohsen Soryani, Mahmood Fathy |
Modeling and Analyzing of Blocking Time Effects on Power Consumption in Network-on-Chips. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
Network on Chip(NoC), High Traffic Regions, Packet Blocking Power Consumption, Blocking Time |
1 | Rachid Dafali, Jean-Philippe Diguet |
Self-Adaptive Network Interface (SANI): Local Component of a NoC Configuration Manager. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu |
DPL on Stratix II FPGA: What to Expect?. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
Dual-rail with Precharge Logic (DPL), Wave Dynamic Differential Logic (WDDL), Field Programmable Gates Array (FPGA), Differential Power Analysis (DPA), Commercial Off-The-Shelf (COTS), Side-Channel Analysis (SCA) |
1 | James Coole, John Robert Wernsing, Greg Stitt |
A Traversal Cache Framework for FPGA Acceleration of Pointer Data Structures: A Case Study on Barnes-Hut N-body Simulation. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
traversal cache, FPGA, speedup, pointers |
1 | Leonard Colavito, Dennis Silage |
Efficient PGA LFSR Implementation Whitens Pseudorandom Numbers. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
Whitening, FPGA, LFSR |
1 | Ahmet Onur Durahim, Erkay Savas, Kazim Yumbul |
Implementing a Protected Zone in a Reconfigurable Processor for Isolated Execution of Cryptographic Algorithms. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Hector Borrayo-Sandoval, Ramón Parra-Michel, Luis F. Gonzalez-Perez, Fernando Landeros Printzen, Claudia Feregrino Uribe |
Design and Implementation of a Configurable Interleaver/Deinterleaver for Turbo Codes in 3GPP Standard. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
configurable, interleaver, Turbo codes |
1 | Naoki Tanida, Mary Inaba, Kei Hiraki, Takeshi Yoshino |
Hardware Accelerator for Full-Text Search (HAFTS) with Succinct Data Structure. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
compressed suffix array, FPGA, succinct data structure, full-text search |
1 | César Torres-Huitzil |
On the Implementation of Central Pattern Generators for Periodic Rhythmic Locomotion. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
rhythmic locomotion patterns, FPGA, Central pattern generators |
1 | Diego F. Sánchez, Daniel M. Muñoz, Carlos H. Llanos, Jose M. Motta |
FPGA Implementation for Direct Kinematics of a Spherical Robot Manipulator. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
Direct Kinematics, FPGA, Floating-point, Robot Manipulator, FSM |
1 | Guillermo Conde, Gregory W. Donohoe, Siva Maheswaran |
Low Power, Reconfigurable Computing Platform for Spacecraft. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Chenxin Zhang, Thomas Lenart, Henrik Svensson, Viktor Öwall |
Design of Coarse-Grained Dynamically Reconfigurable Architecture for DSP Applications. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
Dynamically reconfigurable cell array, Hybrid interconnect, FFT, Coarse-grained reconfigurable architecture |
1 | Abelardo Jara-Berrocal, Ann Gordon-Ross |
Runtime Temporal Partitioning Assembly to Reduce FPGA Reconfiguration Time. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
field programmable gate arrays, partial reconfiguration, temporal partitioning, module placement |
1 | Kenichi Koizumi, Mary Inaba, Kei Hiraki, Yasuo Ishii, Takefumi Miyoshi, Kazuki Yoshizoe |
Triple Line-Based Playout for Go - An Accelerator for Monte Carlo Go. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
|
1 | Siddhartha Datta, Ron Sass |
Scalability Studies of the BLASTn Scan and Ungapped Extension Functions. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
Ungapped Extension, FPGA, Reconfiguration, mathematical model, Scan, BLAST |
1 | Stephanie Drzevitzky, Uwe Kastens, Marco Platzner |
Proof-Carrying Hardware: Towards Runtime Verification of Reconfigurable Modules. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
verification, reconfiguration, hardware |
1 | Taciano A. Rodolfo, Ney Laert Vilar Calazans, Fernando Gehm Moraes |
Floating Point Hardware for Embedded Processors in FPGAs: Design Space Exploration for Performance and Area. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
floating point hardware, GALS design, FPGA, prototyping, embedded processor |
1 | Kenneth L. Rice, Mohammad Ashraf Bhuiyan, Tarek M. Taha, Christopher N. Vutsinas, Melissa C. Smith |
FPGA Implementation of Izhikevich Spiking Neural Networks for Character Recognition. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
FPGA, spiking neural networks |
1 | Juan Fernando Eusse Giraldo, Ricardo Pezzuol Jacobi |
Signal Processing Domain Application Mapping on the Brick Reconfigurable Array. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
Expression Grain, Reconfigurable Computing, Signal Processing, Application Mapping |
1 | Guilherme Montez Guindani, Frederico Ferlini, Jeferson Oliveira, Ney Laert Vilar Calazans, Daniel V. Pigatto, Fernando Gehm Moraes |
A 10 Gbps OTN Framer Implementation Targeting FPGA Devices. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
OTN, Optical Transport Network, Telecommunication Circuits, Framer, FPGA |
1 | Marcus Jeitler, Jakob Lechner |
Speeding up Fault Injection for Asynchronous Logic by FPGA-Based Emulation. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
Four State Logic, Asynchronous Processor Design, Fault Injection, Asynchronous Design |
1 | Asadollah Shahbahrami, Mahmood Ahmadi, Stephan Wong, Koen Bertels |
A New Approach to Implement Discrete Wavelet Transform Using Collaboration of Reconfigurable Elements. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
Grid Computing, Reconfigurable Computing, DWT |
1 | Taho Dorta, Jaime Jimenez, José Luis Martín 0001, Unai Bidarte, Armando Astarloa |
Overview of FPGA-Based Multiprocessor Systems. |
ReConFig |
2009 |
DBLP DOI BibTeX RDF |
MPoPC, Soft Multiprocessor, FPGA, MPSoC |
1 | Elmar Weber, Florian Dittmann 0001, Norma Montealegre |
Part-E - A Tool for Reconfigurable System Design. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
Part-E, bitstream generation, modelling, MDD, partial reconfiguration |
1 | Xuan Zhang, Cesar Ortega-Sanchez, Iain Murray 0002 |
Reconfigurable PDA for the Visually Impaired Using FPGAs. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
FPGAs, embedded systems, Assistive technology, system on a chip |
1 | David Champagne, Reouven Elbaz, Catherine H. Gebotys, Lionel Torres, Ruby B. Lee |
Forward-Secure Content Distribution to Reconfigurable Hardware. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
Security, FPGA, Content Distribution, Broadcast Encryption, Forward-Secure |
1 | Gabriel Caffarena, Juan A. López, Gerardo Leyva, Carlos Carreras, Octavio Nieto-Taladriz |
Optimized Architectural Synthesis of Fixed-Point Datapaths. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
Embedded Multipliers, Fixed-Point, Architectural Synthesis |
1 | Scott Lloyd, Quinn Snell |
Sequence Alignment with Traceback on Reconfigurable Hardware. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
biological, architecture, sequence, alignment, accelerate |
1 | Jose Hugo Barron-Zambrano, César Torres-Huitzil, Mauricio Cerda |
Flexible Architecture for Three Classes of Optical Flow Extraction Algorithms. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Pablo Huerta, Javier Castillo, Carlos Sanchez, José Ignacio Martínez |
Operating System for Symmetric Multiprocessors on FPGA. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
softcore processor, FPGA, Operating System, SMP |
1 | Abdulhadi Shoufan, Sorin A. Huss, Oliver Kelm, Sebastian Schipp |
A Novel Rekeying Message Authentication Procedure Based on Winternitz OTS and Reconfigurable Hardware Architectures. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
Winternitz, Security, FPGA, Key Management, Coprocessor, Rekeying |
1 | Ashwin A. Mendon, Ron Sass |
A Hardware Filesystem Implementation for High-Speed Secondary Storage. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
SATA, FPGA, Parallel Computing, Reconfigurable Computing, Filesystem |
1 | Christian A. Morillas, Juan Pedro Cobos, Francisco J. Pelayo, Alberto Prieto, Samuel F. Romero |
VIS2SOUND on Reconfigurable Hardware. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Alécio Pedro Delazari Binotto, Edison Pignaton de Freitas, Marcelo Götz, Carlos Eduardo Pereira, André Stork, Tony Larsson |
Dynamic Self-Rescheduling of Tasks over a Heterogeneous Platform. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Roque Alfredo Osornio-Rios, René de Jesús Romero-Troncoso, Luis Morales-Velazquez, J. Jesus de Santiago-Perez, Jesus Rooney Rivera-Guillen, Jose de Jesus Rangel-Magdaleno |
A Real-Time FPGA Based Platform for Applications in Mechatronics. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
FPGA Platform, IPcores, real-time, industrial applications |
1 | Jose Hugo Barron-Zambrano, Fernando Martin del Campo-Ramirez, Miguel O. Arias-Estrada |
Parallel Processor for 3D Recovery from Optical Flow. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Victor Lomné, Thomas Ordas, Philippe Maurine, Lionel Torres, Michel Robert, Rafael Soares, Ney Calazans |
Triple Rail Logic Robustness against DPA. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
STTL, DPA, SCA, CPA |
1 | Christophe Desmouliers, Erdal Oruklu, Jafar Saniie |
Universal Wavelet Kernel Implementation Using Reconfigurable Hardware. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Rachid Dafali, Jean-Philippe Diguet, Marc Sevaux |
Key Research Issues for Reconfigurable Network-on-Chip. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Suhaib A. Fahmy |
Generalised Parallel Bilinear Interpolation Architecture for Vision Systems. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
fpga, computer vision, image processing, bilinear interpolation |
1 | Ruzica Jevtic, Carlos Carreras, Domenik Helms |
A Comparison of Approaches for High-Level Power Estimation of LUT-Based DSP Components. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
FPGA, low power, power estimation, high-level modelling |
1 | Nikolay Yu. Sorokin |
Parallel Backprojector for Cone-Beam Computer Tomography. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
Parallel backprojector, FPGA, Computer Tomography |
1 | Paulo Sérgio Brandão do Nascimento, Victor Wanderley Costa de Medeiros, Viviane Lucy Santos de Souza, Abner Corrêa Barros, Manoel Eusébio de Lima |
A Temporal Partitioning Methodology for Reconfigurable High Performance Computers. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
FPGAs, Reconfigurable Computers, Temporal Partitioning |
1 | Fernando Martin del Campo, René Cumplido, Roberto Perez-Andrade, Aldo G. Orozco-Lugo |
Hybrid Architecture for Data-Dependent Superimposed Training in Digital Receivers. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
Data-dependent Superimposed Training, Hardware Accelerators, Hybrid Architecture, Communications Algorithms |
1 | Zain-ul-Abdin, Bertil Svensson |
Using a CSP Based Programming Model for Reconfigurable Processor Arrays. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
CSP, Programming Models, Coarse-grained Reconfigurable Architectures |
1 | Yana Esteves Krasteva, Francisco Criado, Eduardo de la Torre, Teresa Riesgo |
A Fast Emulation-Based NoC Prototyping Framework. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
Partial Reconfiguratin, FPGA, Rapid Prototyping, Emulation, NoC, SoC design |
1 | Zai Jian Jia, Tomás Bautista, Antonio Núñez, Cayetano Guerra, Mario Hernández |
Design Space Exploration and Performance Analysis for the Modular Design of CVS in a Heterogeneous MPSoC. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
Design space exploration, platform-based design, tracking algorithm, heterogeneous MPSoC |
1 | Carlos R. Sanchez-Ortiz, Ramón Parra-Michel, Manuel E. Guzman-Renteria |
Design and Implementation of a Multi-standard Interleaver for 802.11a, 802.11n, 802.16e & DVB Standards. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
Reconfigurable HW, wireless communication system, interleaver |
1 | Bin Zhou, David Hwang |
Implementations and Optimizations of Pipeline FFTs on Xilinx FPGAs. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
Pipeline FFTs, FPGAs |
1 | Ersin Öksüzoglu, Erkay Savas |
Parametric, Secure and Compact Implementation of RSA on FPGA. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
FPGA, RSA, Public key cryptography |
1 | Francesco Redaelli, Marco D. Santambrogio, Seda Ogrenci Memik |
An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-dimensional Reconfigurable Architectures. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
2D dynamically and partially reconfigurable architecture, ILP scheduling model |
1 | Dimitrios Meintanis, Ioannis Papaefstathiou |
Power Consumption Estimations vs Measurements for FPGA-Based Security Cores. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
|
1 | Umer Farooq 0001, Zied Marrakchi, Hayder Mrabet, Habib Mehrez |
The Effect of LUT and Cluster Size on a Tree Based FPGA Architecture. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
CAD tools, FPGA design |
1 | Jean-Christophe Prévotet, Mohamed El Amine Benkhelifa, Bertrand Granado, Emmanuel Huck, Benoît Miramond, François Verdier, Daniel Chillet, Sébastien Pillement |
A Framework for the Exploration of RTOS Dedicated to the Management of Hardware Reconfigurable Resources. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
dynamically reconfigurable architectures, RTOS, high-level modelling |
1 | |
ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 3-5 December 2008, Cancun, Mexico, Proceedings |
ReConFig |
2008 |
DBLP BibTeX RDF |
|
1 | Husain Parvez, Zied Marrakchi, Habib Mehrez |
Enhanced Methodology and Tools for Exploring Domain-Specific Coarse-Grained FPGAs. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
Coarse-grained FPGA, Exploration environment, Floor-planning |
1 | Övünç Kocabas, Erkay Savas, Johann Großschädl |
Enhancing an Embedded Processor Core with a Cryptographic Unit for Speed and Security. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
architectural enhancements, cryptographic unit, cryptography, extensible processors |
1 | Juan Antonio Clemente, Carlos González 0002, Javier Resano, Daniel Mozos |
A Hardware Task-Graph Scheduler for Reconfigurable Multi-tasking Systems. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
Hardware multitasking, FPGAs, Reconfigurable architectures, Task scheduling |
1 | Juan Galindo, Eric Peskin, Brad Larson, Gene Roylance |
Leveraging Firmware in Multichip Systems to Maximize FPGA Resources: An Application of Self-Partial Reconfiguration. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
color-space conversion, CSC, FPGA, dynamic reconfiguration, partial reconfiguration, self reconfiguration, ICAP |
1 | Armando Astarloa, Unai Bidarte, Jesús Lázaro 0001, Jon Andreu, José Luis Martín 0001 |
Configurable-System-on-Programmable-Chip for Power Electronics Control Applications. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
CSoPC, SVM, dynamic reconfiguration, partial reconfiguration, SoPC, matrix converter |
1 | Harold Ishebabi, Philipp Mahr, Christophe Bobda |
Automatic Synthesis of Multiprocessor Systems from Parallel Programs under Preemptive Scheduling. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
Parallel Computing, Reconfigurable Computing, Multiprocessor Systems |
1 | Mohamed El-Hadedy 0001, Danilo Gligoroski, Svein J. Knapskog |
High Performance Implementation of a Public Key Block Cipher - MQQ, for FPGA Platforms. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
Ultra Fast Public Key Cryptosystems, Multivariate Quadratic Quasigroup, MQQ |
1 | Yuken Kishimoto, Shinichiro Haruyama, Hideharu Amano |
Design and Implementation of Adaptive Viterbi Decoder for Using A Dynamic Reconfigurable Processor. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
Software-Defined Radio, Reconfigurable Processor, Viterbi Decoder |
1 | David M. Cambre, Eduardo I. Boemo, Elias Todorovich |
Arithmetic Operations and Their Energy Consumption in the Nios II Embedded Processor. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
energy evaluation, embedded processor |
1 | Ilker Yavuz, Siddika Berna Örs Yalçin, Çetin Kaya Koç |
FPGA Implementation of an Elliptic Curve Cryptosystem over GF(3^m). |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
Galois field of characteristic 3, FPGA, Elliptic curve cryptography, systolic array, Montgomery |
1 | Alessio Montone, Francesco Redaelli, Marco D. Santambrogio, Seda Ogrenci Memik |
A Reconfiguration-Aware Floorplacer for FPGAs. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
floorplacer, FPGA, reconfiguration |
1 | Knut Wold, Chik How Tan |
Analysis and Enhancement of Random Number Generator in FPGA Based on Oscillator Rings. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
Field Programmable Gate Array, Ring Oscillator, True Random Number Generator |
1 | Lars Baunegaard With Jensen, Anders Kjær-Nielsen, Javier Díaz Alonso, Eduardo Ros 0001, Norbert Krüger |
A Hybrid FPGA/Coarse Parallel Processing Architecture for Multi-modal Visual Feature Descriptors. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
early cognitive vision, FPGA, biological vision |
1 | Syed Zahid Ahmed, Julien Eydoux, Michael Fernández, Laurent Rouge, Gilles Sassatelli, Lionel Torres |
Power Consumption Reduction Explorations in Processors by Enhancing Performance Using Small ESL Reprogrammable eFPGAs. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
embedded FPGA, eFPGA accelerator, Reconfigurable computing, Power Consumption, MIPS |
1 | Günter Knittel, Stefanie Mayer, Christian Rothländer |
Integrating Logic Analyzer Functionality into VHDL Designs. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
On-chip logic analyzer, FPGA, VHDL |
1 | Yi-Hua E. Yang, Viktor K. Prasanna |
Automatic Construction of Large-Scale Regular Expression Matching Engines on FPGA. |
ReConFig |
2008 |
DBLP DOI BibTeX RDF |
BRAM, FPGA, finite state machine, Regular expression, NFA |
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