Search results for "bottlenecks"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
16	Jin-Fu Li 0001, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu, Peir-Yuan Tsai, Archer Hsu, Eugene Chow	A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy.	ITC	2003	DBLP DOI BibTeX RDF	built-in redundancy-analysis, built-in self-test, memory testing, semiconductor memory, built-in self-repair
16	Robert F. Molyneaux	Debug and Diagnosis in the Age of System-on-a-Chip.	ITC	2003	DBLP DOI BibTeX RDF
16	Theresa Maudie, Alex Hardt, Rick Nielsen, Dennis Stanerson, Ron Bieschke, Mike Miller	MEMS Manufacturing Testing: An Accelerometer Case Study.	ITC	2003	DBLP DOI BibTeX RDF	Electrical Trim, Measurements, Accelerometers, MEMS
16	Rubin A. Parekhji	Panel Synopsis - How (In)Adequate is One Time Testing?	ITC	2003	DBLP DOI BibTeX RDF
16	Kwang-Ting Cheng	The Confluence of Manufacturing Test and Design Validation.	ITC	2003	DBLP DOI BibTeX RDF
16	Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell	A New Methodology For ADC Test Flow Optimization.	ITC	2003	DBLP DOI BibTeX RDF
16	Peter Ehlig	How (In)Adequate is One-time Testing.	ITC	2003	DBLP DOI BibTeX RDF
16	Xiaoyun Sun, Larry L. Kinney, Bapiraju Vinnakota	Test Vector Generation Based on Correlation Model for Ratio-Iddq.	ITC	2003	DBLP DOI BibTeX RDF
16	L. Forli, Jean-Michel Portal, Didier Née, Bertrand Borot	Infrastructure IP for Back-End Yield Improvement.	ITC	2003	DBLP DOI BibTeX RDF
16	Lei Li 0036, Krishnendu Chakrabarty	Deterministic BIST Based on a Reconfigurable Interconnection Network.	ITC	2003	DBLP DOI BibTeX RDF
16	Oleg Semenov, Arman Vassighi, Manoj Sachdev, Ali Keshavarzi, Charles F. Hawkins	Burn-in Temperature Projections for Deep Sub-micron Technologies.	ITC	2003	DBLP DOI BibTeX RDF
16	Zhen Shi, Peter Sandborn	Optimization of Test/Diagnosis/Rework Location(s) and Characteristics in Electronic Systems Assembly Using Real-Coded Genetic Algorithms.	ITC	2003	DBLP DOI BibTeX RDF
16	Tamal Mukherjee	MEMS Design And Verification.	ITC	2003	DBLP DOI BibTeX RDF	MEMS CAD, MEMS design methodology, composable design, integrated MEMS design, modular design
16	Thomas P. Warwick	Mitigating the Effects of The DUT Interface board and Test System Parasitics in Gigabit-Plus Measurements.	ITC	2003	DBLP DOI BibTeX RDF
16	Ian G. Harris	The Confluence of Manufacturing Test and Design Validation.	ITC	2003	DBLP DOI BibTeX RDF
16	Seongmoon Wang, Srimat T. Chakradhar	A Scalable Scan-Path Test Point Insertion Technique to Enhance Delay Fault Coverage for Standard Scan Designs.	ITC	2003	DBLP DOI BibTeX RDF
16	Wangqi Qiu, D. M. H. Walker	An Efficient Algorithm for Finding the K Longest Testable Paths Through Each Gate in a Combinational Circuit.	ITC	2003	DBLP DOI BibTeX RDF
16	Jim Paviol	Improving Wireless Product Testing: An Opportunity for University and Industry Collaboratio.	ITC	2003	DBLP DOI BibTeX RDF
16	Wouter Rijckaert, Frans G. M. de Jong	Board Test Coverage: The Value of Prediction and How to Compare Numbers.	ITC	2003	DBLP DOI BibTeX RDF
16	Erik Larsson, Zebo Peng	A Reconfigurable Power-Conscious Core Wrapper and its Application to SOC Test Scheduling.	ITC	2003	DBLP DOI BibTeX RDF
16	Janusz Rajski	Test Challenges of Nanometer Technology.	ITC	2003	DBLP DOI BibTeX RDF
16	Fei Su, Sule Ozev, Krishnendu Chakrabarty	Testing of Droplet-Based Microelectrofluidic Systems.	ITC	2003	DBLP DOI BibTeX RDF
16	Jeremy A. Rowlette, Travis M. Eiles	Critical Timing Analysis in Microprocessors Using Near-IR Laser Assisted Device Alteration (LADA).	ITC	2003	DBLP DOI BibTeX RDF
16	Achintya Halder, Soumendu Bhattacharya, Abhijit Chatterjee	Automatic Multitone Alternate Test Generation For RF Circuits Using Behavioral Models.	ITC	2003	DBLP DOI BibTeX RDF
16	Thomas J. Vogels, Wojciech Maly, R. D. (Shawn) Blanton	Progressive Bridge Identification.	ITC	2003	DBLP DOI BibTeX RDF
16	Kenneth P. Parker	Defect Coverage of Boundary-Scan Tests: What does it mean when a Boundary-Scan test passes?	ITC	2003	DBLP DOI BibTeX RDF
16	Jay J. Nejedlo	TRIBuTETM Board and Platform Test Methodology: Intel's Next-Generation Test and Validation Methodology for Platforms.	ITC	2003	DBLP DOI BibTeX RDF
16	John Ferrario, Randy Wolf, Steve Moss	Architecting Millisecond Test Solutions for Wireless Phone RFIC's.	ITC	2003	DBLP DOI BibTeX RDF
16	Kaijie Wu 0001, Ramesh Karri	Register Transfer Level Approach to Hybrid Time and Hardware Redundancy Based Fault Secure Datapath Synthesis.	ITC	2003	DBLP DOI BibTeX RDF
16	Wojciech Maly, Anne E. Gattiker, Thomas Zanon, Thomas J. Vogels, R. D. (Shawn) Blanton, Thomas M. Storey	Deformations of IC Structure in Test and Yield Learning.	ITC	2003	DBLP DOI BibTeX RDF	yield learning, defect characterization, diagnosis, fault modeling, defects
16	Cheng Jia, Linda S. Milor	A BIST Solution for The Test of I/O Speed.	ITC	2003	DBLP DOI BibTeX RDF
16	Geir Eide, Kenneth E. Posse	Open Microphone - My DFT is better than yours ...	ITC	2003	DBLP DOI BibTeX RDF
16	Alfredo Benso	Self-Testing and Self-Healing via Mobile Agents.	ITC	2003	DBLP DOI BibTeX RDF
16	Jayashree Saxena, Kenneth M. Butler, Vinay B. Jayaram, Subhendu Kundu, N. V. Arvind, Pravin Sreeprakash, Manfred Hachinger	A Case Study of IR-Drop in Structured At-Speed Testing.	ITC	2003	DBLP DOI BibTeX RDF
16	Rahul Kundu, R. D. (Shawn) Blanton	Path Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk.	ITC	2003	DBLP DOI BibTeX RDF
16	Armin Würtenberger, Christofer S. Tautermann, Sybille Hellebrand	A Hybrid Coding Strategy For Optimized Test Data Compression.	ITC	2003	DBLP DOI BibTeX RDF
16	Rakesh N. Joshi, Kenneth L. Williams, Lee Whetsel	Evolution of IEEE 1149.1 Addressable Shadow Protocol Devices.	ITC	2003	DBLP DOI BibTeX RDF
16	Haihua Yan, Adit D. Singh	Experiments in Detecting Delay Faults using Multiple Higher Frequency Clocks and Results from Neighboring Die.	ITC	2003	DBLP DOI BibTeX RDF
16	Derek Wright, Manoj Sachdev	Transistor-Level Fault Analysis and Test Algorithm Development for Ternary Dynamic Content Addressable Memorie.	ITC	2003	DBLP DOI BibTeX RDF
16	Zhen Guo, Jacob Savir	Analog Circuit Test using Transfer Function Coe .cient Estimates.	ITC	2003	DBLP DOI BibTeX RDF	Fault detection, Monte-Carlo simulation, System identification, Parametric faults
16	Takahiro J. Yamaguchi	Open Architecture ATE and 250 Consecutive UIs.	ITC	2003	DBLP DOI BibTeX RDF
16	Frank Poehl, Matthias Beck, Ralf Arnold, Peter Muhmenthaler, Nagesh Tamarapalli, Mark Kassab, Nilanjan Mukherjee 0001, Janusz Rajski	Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions.	ITC	2003	DBLP DOI BibTeX RDF
16	Henry C. Lin, Karen Taylor, Alan Chong, Eddie Chan, Mani Soma, Hosam Haggag, Jeff Huard, Jim Braatz	CMOS Built-In Test Architecture for High-Speed Jitter Measurement.	ITC	2003	DBLP DOI BibTeX RDF
16	Mike Li	Requirements, Challenges, And Solutions For Testing Multiple GB/s ICs In Production.	ITC	2003	DBLP DOI BibTeX RDF
16	Mahesh A. Iyer	Race: A Word-Level ATPG-Based Constraints Solver System For Smart Random Simulation.	ITC	2003	DBLP DOI BibTeX RDF
16	John Roberts	Test Outsourcing - A Subcontract Manufacturer's Perspective.	ITC	2003	DBLP DOI BibTeX RDF
16	Yu Huang 0005, Wu-Tung Cheng, Sudhakar M. Reddy, Cheng-Ju Hsieh, Yu-Ting Hung	Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault.	ITC	2003	DBLP DOI BibTeX RDF
16	Ahmed Rashid Syed	RIC/DICMOS - Multi-channel CMOS Formatter.	ITC	2003	DBLP DOI BibTeX RDF
16	Masashi Shimanouchi	Periodic Jitter Injection with Direct Time Synthesis by SPPTM ATE for SerDes Jitter Tolerance Test in Production.	ITC	2003	DBLP DOI BibTeX RDF
16	Brady Benware, Chris Schuermyer, Sreenevasan Ranganathan, Robert Madge, Prabhu Krishnamurthy, Nagesh Tamarapalli, Kun-Han Tsai, Janusz Rajski	Impact of Multiple-Detect Test Patterns on Product Quality.	ITC	2003	DBLP DOI BibTeX RDF
16	Olivier Caty, Ismet Bayraktaroglu, Amitava Majumdar 0002, Richard Lee, John Bell, Lisa Curhan	Instruction Based BIST for Board/System Level Test of External Memories and Internconnects.	ITC	2003	DBLP DOI BibTeX RDF
16	A. T. Sivaram, Daniel Fan, Jon Pryce	XML And Java For Open ATE Programming Environment.	ITC	2003	DBLP DOI BibTeX RDF
16	Henk D. L. Hollmann, Erik Jan Marinissen, Bart Vermeulen	Optimal Interconnect ATPG Under a Ground-Bounce Constraint.	ITC	2003	DBLP DOI BibTeX RDF
16	Fidel Muradali	Future ATE: Perspectives & Requirements.	ITC	2003	DBLP DOI BibTeX RDF
16	Kendrick Baker	Constructive Pattern Generation Heuristic for Meeting SSO Limits.	ITC	2003	DBLP DOI BibTeX RDF
16	Yannick Bonhomme, Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	Efficient Scan Chain Design for Power Minimization During Scan Testing Under Routing Constraint.	ITC	2003	DBLP DOI BibTeX RDF
16	Romain Desplats, Felix Beaudoin, Philippe Perdu, Nagamani Nataraj, Ted R. Lundquist, Ketan Shah	Fault Localization using Time Resolved Photon Emission and STIL Waveforms.	ITC	2003	DBLP DOI BibTeX RDF
16	Abhijit Chatterjee	Seamless Research Between Academia And Industry To Facilitate Test Of Integrated High-Speed Wireless Systems: Is This An Illusion?	ITC	2003	DBLP DOI BibTeX RDF
16	Tom Newsom	Future ATE for System on a Chip... Some Perspectives.	ITC	2003	DBLP DOI BibTeX RDF
16	Cliff Ma	DFM - An Industry Paradigm Shift.	ITC	2003	DBLP DOI BibTeX RDF
16	Michael G. Wahl, Sudipta Bhawmik, Kamran Zarrineh, Pradipta Ghosh, Scott Davidson 0001, Peter Harrod	The P1500 DFT Disclosure Document: A Standard to Communicate Mergeable Core DFT Data.	ITC	2003	DBLP DOI BibTeX RDF
16	Lee Whetsel	Adapting JTAG for AC Interconnect Testing.	ITC	2003	DBLP DOI BibTeX RDF
16	Ivan Duzevik	Design and Implementation of IEEE 1149.6.	ITC	2003	DBLP DOI BibTeX RDF
16	José Pineda de Gyvez, Guido Gronthoud, Rashid Amine	VDD Ramp Testing for RF Circuits.	ITC	2003	DBLP DOI BibTeX RDF
16	Clayton Gibbs	Backplane Test Bus Applications For IEEE STD 1149.1.	ITC	2003	DBLP DOI BibTeX RDF
16	William R. Eisenstadt	Improving Wireless Product Testing via University and Industry Collaboration.	ITC	2003	DBLP DOI BibTeX RDF
16	Hamidreza Hashempour, Fred J. Meyer, Fabrizio Lombardi, Farzin Karimi	Hybrid Multisite Testing at Manufacturing.	ITC	2003	DBLP DOI BibTeX RDF
16	Kartik Mohanram, Nur A. Touba	Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits.	ITC	2003	DBLP DOI BibTeX RDF
16	Haluk Konuk, Leon Xiao	DFFT : Design For Functional Testability.	ITC	2003	DBLP DOI BibTeX RDF
16	Qiang Xu 0001, Nicola Nicolici	On Reducing Wrapper Boundary Register Cells in Modular SOC Testing.	ITC	2003	DBLP DOI BibTeX RDF
16	Adit D. Singh	Should Nanometer Circuits be Periodically Tested in the Field?	ITC	2003	DBLP DOI BibTeX RDF
16	Yi Cai	Jitter Test in Production for High Speed Serial Links.	ITC	2003	DBLP DOI BibTeX RDF
16	Chris Schuermyer, Brady Benware, Kevin Cota, Robert Madge, W. Robert Daasch, L. Ning	Screening VDSM Outliers using Nominal and Subthreshold Supply Voltage IDDQ.	ITC	2003	DBLP DOI BibTeX RDF
16	Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, T. M. Mak	Diagnosis-Based Post-Silicon Timing Validation Using Statistical Tools and Methodologies.	ITC	2003	DBLP DOI BibTeX RDF
16	Nektarios Kranitis, George Xenoulis, Antonis M. Paschalis, Dimitris Gizopoulos, Yervant Zorian	Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores.	ITC	2003	DBLP DOI BibTeX RDF
16	Charles E. Stroud, Keshia N. Leach, Thomas A. Slaughter	BIST for Xilinx 4000 and Spartan Series FPGAs: A Case Study.	ITC	2003	DBLP DOI BibTeX RDF
16	Liang Zhang 0012, Indradeep Ghosh, Michael S. Hsiao	Efficient Sequential ATPG for Functional RTL Circuits.	ITC	2003	DBLP DOI BibTeX RDF
16	Lee Y. Song	Future ATE: Perspectives & Requirements.	ITC	2003	DBLP DOI BibTeX RDF
16	Tapio Koivukangas	Testing Challenges of Future Wireless World.	ITC	2003	DBLP DOI BibTeX RDF
16	Donald L. Wheater	ATE-Customer Perspectives & Requirements Panel.	ITC	2003	DBLP DOI BibTeX RDF
16	Teresa L. McLaurin, Frank Frederick, Rich Slobodnik	The Testability Features of The ARM1026EJ Microprocessor Core.	ITC	2003	DBLP DOI BibTeX RDF
16	Chih-Wea Wang, Kuo-Liang Cheng, Jih-Nung Lee, Yung-Fa Chou, Chih-Tsun Huang, Cheng-Wen Wu, Frank Huang, Hong-Tzer Yang	Fault Pattern Oriented Defect Diagnosis for Memories.	ITC	2003	DBLP DOI BibTeX RDF	failure analysis (FA), fault pattern, memory diagnostics, memory testing, bitmap, semiconductor memory
16	Jitendra Khare	DFM - A Fabless Perspective.	ITC	2003	DBLP DOI BibTeX RDF
16	Keneth R. Wilsher	Designed -in-diagnostics: A new optical method.	ITC	2003	DBLP DOI BibTeX RDF
16	Mike Li	Production Test Challenges And Possible Solutions For Multiple GB/s ICs.	ITC	2003	DBLP DOI BibTeX RDF
16	Mahim Mishra, Seth Copen Goldstein	Defect Tolerance at the End of the Roadmap.	ITC	2003	DBLP DOI BibTeX RDF
16	Davide Appello, Paolo Bernardi, Alessandra Fudoli, Maurizio Rebaudengo, Matteo Sonza Reorda, Vincenzo Tancorre, Massimo Violante	Exploiting Programmable BIST For The Diagnosis of Embedded Memory Cores.	ITC	2003	DBLP DOI BibTeX RDF
16	Eric L. Smitt	Selecting PXI Architecture for Board (System) Functional Test.	ITC	2003	DBLP DOI BibTeX RDF
16	Michael A. Jones	Ultra Low Cost Linear Testing.	ITC	2003	DBLP DOI BibTeX RDF
16	Jeremy A. Walraven	Introduction to Applications and Industries for Microelectromechanical Systems (MEMS).	ITC	2003	DBLP DOI BibTeX RDF
16	Moray Rumney	Testing 3G-controlled systems: time to rejoice or time to feel pain?	ITC	2003	DBLP DOI BibTeX RDF
16	Wanli Jiang, Eric Peterson, Bob Robotka	Effectiveness Improvement of ECR Tests.	ITC	2003	DBLP DOI BibTeX RDF
16	Mustapha Slamani	RF Test 101: Defining the Problem, Finding Solutions.	ITC	2003	DBLP DOI BibTeX RDF
16	Xiaoliang Bai, Sujit Dey, Angela Krstic	HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk.	ITC	2003	DBLP DOI BibTeX RDF
16	Stephen K. Sunter	Testing High Frequency ADCs and DACs with a Low Frequency Analog Bus.	ITC	2003	DBLP DOI BibTeX RDF
16	Miroslav N. Velev	Collection of High-Level Microprocessor Bugs from Formal Verification of Pipelined and Superscalar Designs.	ITC	2003	DBLP DOI BibTeX RDF
16	Franco Stellari, Peilin Song, Moyra K. McManus, Robert Gauthier 0002, Alan J. Weger, Kiran V. Chatty, Mujahid Muhammad, Pia N. Sanda	Optical and Electrical Testing of Latchup in I/O Interface Circuits.	ITC	2003	DBLP DOI BibTeX RDF
16	Zhiyuan Wang, Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski	An Efficient and Effective Methodology on the Multiple Fault Diagnosis.	ITC	2003	DBLP DOI BibTeX RDF
16	Qingwei Wu, Michael S. Hsiao	Efficient Sequential ATPG Based on Partitioned Finite-State-Machine Traversal.	ITC	2003	DBLP DOI BibTeX RDF
16	Fidel Muradali	Diagnosis in Modern Design - Just the Tip of the Iceberg.	ITC	2003	DBLP DOI BibTeX RDF