Search results for "designs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
12	Miriam Leeser, Richard Chapman 0001, Mark D. Aagaard, Mark H. Linderman, Stephan Meier	High level synthesis and generating FPGAs with the BEDROC system.	J. VLSI Signal Process.	1993	DBLP DOI BibTeX RDF
12	Neff Walker, John B. Smelcer	A comparison of selection time from walking and pull-down menus.	CHI	1990	DBLP DOI BibTeX RDF
12	Terry Winograd	What can we teach about human-computer interaction? (plenary address).	CHI	1990	DBLP DOI BibTeX RDF
12	Hans Brunner	A snapshot of natural language interfaces (panel).	CHI	1990	DBLP DOI BibTeX RDF
12	Jakob Nielsen	Designing for international use (panel).	CHI	1990	DBLP DOI BibTeX RDF
12	S. Joy Mountford	Designers: meet your users (panel).	CHI	1990	DBLP DOI BibTeX RDF	Apple Computer, HyperCard, Inc
12	Marcy Telles	Updating an older interface.	CHI	1990	DBLP DOI BibTeX RDF	WordStar
12	Nikolay Petkov Turkedjiev	Synthesis of Systolic Algorithms and Processor Arrays.	CONPAR	1986	DBLP DOI BibTeX RDF
12	Chyuan Shiun Lin, Diane C. P. Smith, John Miles Smith	The Design of a Rotating Associative Array Memory for a Relational Database Management Application.	ACM Trans. Database Syst.	1976	DBLP DOI BibTeX RDF	head-per-track disks, rotating devices, search logic, sorting technique, relational database, associative memory, memory systems, data organization, content addressability
11	Jonathan M. Johnson, Michael J. Wirthlin	Voter insertion algorithms for FPGA designs using triple modular redundancy.	FPGA	2010	DBLP DOI BibTeX RDF	scc, tmr, voter insertion, fpga, algorithm, reliability, synchronization
11	Larry Howard, Julie Johnson, Carin Neitzel	Reflecting on online learning designs using observed behavior.	ITiCSE	2010	DBLP DOI BibTeX RDF	design reflection, inquiry-based learning, instructional design patterns, learning environments, self-regulated learning
11	Tak-Yung Kim, Taewhan Kim	Clock tree synthesis with pre-bond testability for 3D stacked IC designs.	DAC	2010	DBLP DOI BibTeX RDF	optimization, routing, buffer insertion, 3D ICs, clock tree
11	Christos-Savvas Bouganis, Sung-Boem Park, George A. Constantinides, Peter Y. K. Cheung	Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	2D filter design, FPGA, Singular Value Decomposition, reconfigurable logic
11	Dieter Jungnickel, Vladimir D. Tonchev	Polarities, quasi-symmetric designs, and Hamada's conjecture.	Des. Codes Cryptogr.	2009	DBLP DOI BibTeX RDF	Mathematics Subject Classifications (2000) 05B05, 51E20, 94B27
11	Kuljit Kaur Chahal, Hardeep Singh	Metrics to study symptoms of bad software designs.	ACM SIGSOFT Softw. Eng. Notes	2009	DBLP DOI BibTeX RDF
11	Richard W. Selby	Analytics-Driven Dashboards Enable Leading Indicators for Requirements and Designs of Large-Scale Systems.	IEEE Softw.	2009	DBLP DOI BibTeX RDF
11	Rebecca Wirfs-Brock	Creating Sustainable Designs.	IEEE Softw.	2009	DBLP DOI BibTeX RDF
11	Jeffrey M. Carver, Richard Neil Pittman, Alessandro Forin	Automatic bus macro placement for partially reconfigurable FPGA designs.	FPGA	2009	DBLP DOI BibTeX RDF	emips, reconfigurable computing, dynamic partial reconfiguration, floor-planning
11	Andrew DeOrio, Ilya Wagner, Valeria Bertacco	Dacota: Post-silicon validation of the memory subsystem in multi-core designs.	HPCA	2009	DBLP DOI BibTeX RDF
11	David Rodríguez Rueda, Carlos Cotta, Antonio J. Fernández 0001	Finding Balanced Incomplete Block Designs with Metaheuristics.	EvoCOP	2009	DBLP DOI BibTeX RDF
11	Sushmita Ruj, Jennifer Seberry, Bimal K. Roy	Key Predistribution Schemes Using Block Designs in Wireless Sensor Networks.	CSE (2)	2009	DBLP DOI BibTeX RDF
11	Percy V. Gilbert	Advances in process technology & IBM collaborative ecosystem for leadership power performance SOC designs.	ISLPED	2009	DBLP DOI BibTeX RDF	keynote
11	Michael J. Anderson, Azadeh Davoodi, Jungseob Lee, Abhishek A. Sinkar, Nam Sung Kim	Statistical static timing analysis considering leakage variability in power gated designs.	ISLPED	2009	DBLP DOI BibTeX RDF	process variations, leakage, power gating, ssta
11	George Michelogiannakis, William J. Dally	Router designs for elastic buffer on-chip networks.	SC	2009	DBLP DOI BibTeX RDF	on-chip networks
11	Min-Young Nam, Rodolfo Pellizzoni, Lui Sha, Richard M. Bradford	ASIIST: Application Specific I/O Integration Support Tool for Real-Time Bus Architecture Designs.	ICECCS	2009	DBLP DOI BibTeX RDF
11	Lijun Yu, Robert B. France, Indrakshi Ray, Sudipto Ghosh	A Rigorous Approach to Uncovering Security Policy Violations in UML Designs.	ICECCS	2009	DBLP DOI BibTeX RDF
11	Andrew Manches, Claire O'Malley, Steve Benford	Physical manipulation: evaluating the potential for tangible designs.	TEI	2009	DBLP DOI BibTeX RDF	physical manipulation, problem solving, tangibles
11	Hoojin Lee, Jeffrey G. Andrews, Edward J. Powers	Information outage probability and diversity order of symmetric coordinate interleaved orthogonal designs.	IEEE Trans. Wirel. Commun.	2008	DBLP DOI BibTeX RDF
11	Hlaing Minn, Yinghui Li, Naofal Al-Dhahir	PAR-Constrained Training Signal Designs for MIMO OFDM Channel Estimation in the Presence of Frequency Offsets.	IEEE Trans. Wirel. Commun.	2008	DBLP DOI BibTeX RDF
11	Weiwu Hu, Jian Wang	Making Effective Decisions in Computer Architects' Real-World: Lessons and Experiences with Godson-2 Processor Designs.	J. Comput. Sci. Technol.	2008	DBLP DOI BibTeX RDF	correlation design, balanced design, Pico-architecture design, work-on-silicon, optimized design, superscalar architecture
11	Han-Xin Sun, Kun-Peng Yang, Yulai Zhao 0003, Dong Tong 0001, Xu Cheng 0001	CASA: A New IFU Architecture for Power-Efficient Instruction Cache and TLB Designs.	J. Comput. Sci. Technol.	2008	DBLP DOI BibTeX RDF	instruction TLB, instruction fetch unit, power-efficient design, computer architecture, dynamic voltage scaling, instruction cache
11	Yifang Liu, Jiang Hu, Weiping Shi	Buffering Interconnect for Multicore Processor Designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
11	Abhijit Jas, Yi-Shing Chang, Sreejit Chakravarty	A Methodology for Handling Complex Functional Constraints for Large Industrial Designs.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Untestability analysis, Pseudo-functional tests, Functional constraints
11	Yong Zhan, Sachin S. Sapatnekar	Automated module assignment in stacked-Vdd designs for high-efficiency power delivery.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF
11	Yen-Kuang Chen, Sun-Yuan Kung	Trend and Challenge on System-on-a-Chip Designs.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	SoC design trend, SoC design challenge, VLSI, SoC, system-on-a-chip
11	Rui Wang 0007, Vincent K. N. Lau	Robust Optimal Cross-Layer Designs for TDD-OFDMA Systems with Imperfect CSIT and Unknown Interference: State-Space Approach Based on 1-bit ACK/NAK Feedbacks.	IEEE Trans. Commun.	2008	DBLP DOI BibTeX RDF
11	Kee Sup Kim, Ming Zhang 0017	Hierarchical Test Compression for SoC Designs.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	SoC, hierarchical, test compression
11	J. Andrés Díaz Pace, Marcelo R. Campo	Exploring Alternative Software Architecture Designs: A Planning Perspective.	IEEE Intell. Syst.	2008	DBLP DOI BibTeX RDF
11	Xuejin Chen, Sing Bing Kang, Ying-Qing Xu, Julie Dorsey, Heung-Yeung Shum	Sketching reality: Realistic interpretation of architectural designs.	ACM Trans. Graph.	2008	DBLP DOI BibTeX RDF	realistic imagery, Sketching, shape
11	Glenn Shafer, Amos Tversky	Languages and Designs for Probability Judgment.	Classic Works of the Dempster-Shafer Theory of Belief Functions	2008	DBLP DOI BibTeX RDF
11	Steven Floyd, Serhat Adilak, Steven Ramirez, Raphael Rogman, Metin Sitti	Performance of different foot designs for a water running robot.	ICRA	2008	DBLP DOI BibTeX RDF
11	German L. Vazquez, Marcelo R. Campo, J. Andrés Díaz Pace	A case-based reasoning approach for materializing software architectures onto object-oriented designs.	SAC	2008	DBLP DOI BibTeX RDF	architecture materialization, object-oriented design, case-based reasoning, architecture design
11	Ilya Wagner, Valeria Bertacco	MCjammer: Adaptive Verification for Multi-core Designs.	DATE	2008	DBLP DOI BibTeX RDF
11	Sanghamitra Roy, Yu Hen Hu, Charlie Chung-Ping Chen, Shih-Pin Hung, Tse-Yu Chiang, Jiuan-Guei Tseng	An optimal algorithm for sizing sequential circuits for industrial library based designs.	ASP-DAC	2008	DBLP DOI BibTeX RDF
11	David Z. Pan, Minsik Cho	Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond.	ASP-DAC	2008	DBLP DOI BibTeX RDF
11	Ansuman Banerjee, Sayak Ray, Pallab Dasgupta, Partha Pratim Chakrabarti, S. Ramesh 0002, P. Vignesh V. Ganesan	A Dynamic Assertion-Based Verification Platform for Validation of UML Designs.	ATVA	2008	DBLP DOI BibTeX RDF
11	Sofiane Aouag	A Mulimodeling Framework for Complex Learning Activity Designs.	ICWL	2008	DBLP DOI BibTeX RDF	learning to read, learning object, Learning activity, individualizing learning, Multimodeling
11	Yuankun Yao	Comparing the Impact of Two Different Designs for Online Discussion.	ICWL	2008	DBLP DOI BibTeX RDF	instructional design, Online discussion
11	Yan Wan 0001, Sandip Roy 0002, Xu Wang 0005, Ali Saberi, Tao Yang 0003, Mengran Xue, Babak Malek	On the structure of graph edge designs that optimize the algebraic connectivity.	CDC	2008	DBLP DOI BibTeX RDF
11	Paul Schumacher, Pradip Jha	Fast and accurate resource estimation of RTL-based designs targeting FPGAS.	FPL	2008	DBLP DOI BibTeX RDF
11	Stephen H. Muggleton	Developing Robust Synthetic Biology Designs Using a Microfluidic Robot Scientist.	SBIA	2008	DBLP DOI BibTeX RDF
11	Conrado Pilotto, José Rodrigo Azambuja, Fernanda Lima Kastensmidt	Synchronizing triple modular redundant designs in dynamic partial reconfiguration applications.	SBCCI	2008	DBLP DOI BibTeX RDF	fault tolerance, FPGA, TMR, dynamic partial reconfiguration
11	Yifang Liu, Jiang Hu, Weiping Shi	Multi-scenario buffer insertion in multi-core processor designs.	ISPD	2008	DBLP DOI BibTeX RDF	multi-core design, buffer insertion
11	Rachel T. Johnson, Bradley A. Jones, John W. Fowler, Douglas C. Montgomery	Comparing designs for computer simulation experiments.	WSC	2008	DBLP DOI BibTeX RDF
11	Selim Ciraci, Pim van den Broek, Mehmet Aksit	Framework for Computer-Aided Evolution of Object-Oriented Designs.	COMPSAC	2008	DBLP DOI BibTeX RDF	Object-Oriented Evolution, Design patterns, Software Evolution, Graph Transformation
11	Ka Lun Eddie Law, Adam Kohn	Topology designs with controlled interference for multi-radio wireless mesh networks.	Mobility Conference	2008	DBLP DOI BibTeX RDF	IEEE 802.11 protocol, controlled interference, multi-radio multi-channel wireless protocol, medium access control, wireless mesh networks, packet loss probability
11	Mike Bennett, Aaron J. Quigley	Perceptual usability: predicting changes in visual interfaces & designs due to visual acuity differences.	AVI	2008	DBLP DOI BibTeX RDF	evaluation, methodology, methods, screen design
11	Barnabas C. Okeke, Ka Lun Eddie Law	Multi-level clustering architecture and protocol designs for wireless sensor networks.	WICON	2008	DBLP DOI BibTeX RDF	multi-level clustering (MLC), clusters, wireless sensor networks, sensors, energy model, LEACH
11	Éric Bel, Emma Bradburn	Reframing Teachers' Conceptions of Accessible E-Learning Designs.	ICALT	2008	DBLP DOI BibTeX RDF
11	Bernd Becker 0001, Marc Herbstritt, Natalia Kalinnik, Matthew Lewis 0004, Juri Lichtner, Tobias Nopper, Ralf Wimmer 0001	Propositional approximations for bounded model checking of partial circuit designs.	ICCD	2008	DBLP DOI BibTeX RDF
11	Shih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang, Malgorzata Marek-Sadowska	Timing analysis considering IR drop waveforms in power gating designs.	ICCD	2008	DBLP DOI BibTeX RDF
11	Ning Chen 0004, Zhiyuan Yan 0001	Compact designs of mixcolumns and subbytes using a novel common subexpression elimination algorithm.	ISCAS	2008	DBLP DOI BibTeX RDF
11	Yi Yu 0008, Junwei Yan, Min Liu 0002, Bensheng Yun	A Semantic Paradigm to Integrate Customer Demands and Product Designs Based on Model-Driven Architecture.	CSSE (1)	2008	DBLP DOI BibTeX RDF
11	Mark Hammerquist, Roman L. Lysecky	Design space exploration for application specific FPGAS in system-on-a-chip designs.	SoCC	2008	DBLP DOI BibTeX RDF
11	Rong-Xian Yue, Xin Liu	Minimax Designs for Approximately Linear Multiresponse Models.	FSKD (1)	2008	DBLP DOI BibTeX RDF
11	Guanling Chen, Faruq Rahman	Analyzing Privacy Designs of Mobile Social Networking Applications.	EUC (2)	2008	DBLP DOI BibTeX RDF
11	Tom Kean, David McLaren, Carol Marsh	Verifying the Authenticity of Chip Designs with the DesignTag System.	HOST	2008	DBLP DOI BibTeX RDF
11	Shianling Wu, Laung-Terng Wang, Zhigang Jiang, Jiayong Song, Boryau Sheu, Xiaoqing Wen, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Ravi Apte	On Optimizing Fault Coverage, Pattern Count, and ATPG Run Time Using a Hybrid Single-Capture Scheme for Testing Scan Designs.	DFT	2008	DBLP DOI BibTeX RDF
11	Zhonglei Wang, Wolfgang Haberl, Stefan Kugele, Michael Tautschnig	Automatic generation of systemc models from component-based designs for early design validation and performance analysis.	WOSP	2008	DBLP DOI BibTeX RDF	cola, simulation, code generation, systemc
11	Sandeep Gupta, Jaya Singh, Abhijit Roy	A Novel Cell-Based Heuristic Method for Leakage Reduction in Multi-Million Gate VLSI Designs.	ISQED	2008	DBLP DOI BibTeX RDF	Dual-Vt Technology, Cell-Based Approach, Cell-swapping, Leakage Power
11	Ludovic Charvier, Fabien Bourgeois, Jacques Jacot, Grégoire Genolet, Hubert Lorenz	New Designs for Submillimetric Press-Fitting.	IPAS	2008	DBLP DOI BibTeX RDF
11	Jong Kang Park, Hyun Suk Choi, Jong Tae Kim	A soft error analysis tool for high-speed digital designs.	ICUIMC	2008	DBLP DOI BibTeX RDF
11	Weidong Li, Lequan Min	Robust Designs for Shadow Projection CNN.	ICNSC	2008	DBLP DOI BibTeX RDF
11	Zhe-Wei Jiang, Bor-Yiing Su, Yao-Wen Chang	Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs.	DAC	2008	DBLP DOI BibTeX RDF	placement, physical design, routability
11	Anand Rajaram, David Z. Pan	Robust chip-level clock tree synthesis for SOC designs.	DAC	2008	DBLP DOI BibTeX RDF	chip-level CTS, physical design, clock network
11	Alberto González Téllez, Miguel A. Mateo Pla	Multithreaded Translation of Ptolemy II Designs on Multicore Platforms.	CISIS	2008	DBLP DOI BibTeX RDF
11	Martin Hell, Thomas Johansson 0001, Alexander Maximov, Willi Meier	The Grain Family of Stream Ciphers.	The eSTREAM Finalists	2008	DBLP DOI BibTeX RDF
11	Hazem Hiary, Kia Ng	A system for segmenting and extracting paper-based watermark designs.	Int. J. Digit. Libr.	2007	DBLP DOI BibTeX RDF	Paper watermark, Image processing, Preservation, Graphical representation, Digitisation
11	Andrea Blunck, Hans Havlicek, Corrado Zanella	Lifting of divisible designs.	Des. Codes Cryptogr.	2007	DBLP DOI BibTeX RDF	AMS Classifications 05B30, 51E20, 20B25
11	Sanjeevani Gharge, Sharad S. Sane	Quasi-affine symmetric designs.	Des. Codes Cryptogr.	2007	DBLP DOI BibTeX RDF	AMS Classifications Primary 05B05, Secondary 05B15, Secondary 05B25
11	Sabine Giese, Ralph-Hardo Schulz	Divisible designs with dual translation group.	Des. Codes Cryptogr.	2007	DBLP DOI BibTeX RDF	51N10, AMS Classification 05B05, 05B30, 20B25
11	Asma Al-Tamimi, Murad Abu-Khalaf, Frank L. Lewis	Adaptive Critic Designs for Discrete-Time Zero-Sum Games With Application to Hinfty Control.	IEEE Trans. Syst. Man Cybern. Part B	2007	DBLP DOI BibTeX RDF
11	Chuan Lin 0002, Hai Zhou 0001	Tradeoff Between Latch and Flop for Min-Period Sequential Circuit Designs With Crosstalk.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
11	Miquel Payaró, Antonio Pascual-Iserte, Miguel Angel Lagunas	Robust Power Allocation Designs for Multiuser and Multiantenna Downlink Communication Systems through Convex Optimization.	IEEE J. Sel. Areas Commun.	2007	DBLP DOI BibTeX RDF
11	Shobha Vasudevan, E. Allen Emerson, Jacob A. Abraham	Improved verification of hardware designs through antecedent conditioned slicing.	Int. J. Softw. Tools Technol. Transf.	2007	DBLP DOI BibTeX RDF	LTL property, Antecedent conditioned slicing, Verilog RTL, Model checking, Program slicing, Hardware description languages, Hardware verification
11	Angela Sara Cacciapuoti, Giacinto Gelli, Francesco Verde	FIR Zero-Forcing Multiuser Detection and Code Designs for Downlink MC-CDMA.	IEEE Trans. Signal Process.	2007	DBLP DOI BibTeX RDF
11	Jeremy Lee, Mohammad Tehranipoor, Chintan Patel, Jim Plusquellic	Securing Designs against Scan-Based Side-Channel Attacks.	IEEE Trans. Dependable Secur. Comput.	2007	DBLP DOI BibTeX RDF	Security and Privacy Protection, Scan-Based Design, Secure Design, Reliability and Testing
11	Mikhail Perepletchikov, Caspar Ryan, Keith Frampton, Zahir Tari	Coupling Metrics for Predicting Maintainability in Service-Oriented Designs.	ASWEC	2007	DBLP DOI BibTeX RDF
11	Shuming Chen, Xiangyuan Liu	A Low-Latency and Low-Power Hybrid Insertion Methodology for Global Interconnects in VDSM Designs.	NOCS	2007	DBLP DOI BibTeX RDF	differential-signaling, insertion methodology, on-chip interconnects, low-swing
11	Robert G. Pettit IV, Hassan Gomaa	Analyzing Behavior of Concurrent Software Designs for Embedded Systems.	ISORC	2007	DBLP DOI BibTeX RDF
11	Julie A. Street, Robert G. Pettit IV, Hassan Gomaa	Independent Model-Driven Software Performance Assessments of UML Designs.	ISORC	2007	DBLP DOI BibTeX RDF
11	B. P. Harish, Navakanta Bhat, Mahesh B. Patil	Process Variability-Aware Statistical Hybrid Modeling of Dynamic Power Dissipation in 65 nm CMOS Designs.	ICCTA	2007	DBLP DOI BibTeX RDF	mixed-mode simulations, hybrid model, Least Squares Method, Response Surface Methodology
11	Allan Crone, Gabriel Chidolue	Functional Verification of Low Power Designs at RTL.	PATMOS	2007	DBLP DOI BibTeX RDF	Low power aware management, Corruption, UPF, Simulation, Retention, PCF
11	Prashant Agrawal, Srinivasa R. S. T. G, Ajit N. Oke, Saurabh Vijay	A Scalable Modeling Technique to Estimate Dynamic Thermal Design Power of Datapath Intensive Designs.	ISVLSI	2007	DBLP DOI BibTeX RDF
11	Alair Dias Jr., Diógenes Cecilio da Silva Jr.	Code-coverage Based Test Vector Generation for SystemC Designs.	ISVLSI	2007	DBLP DOI BibTeX RDF
11	Naouel Moha	Detection and correction of design defects in object-oriented designs.	OOPSLA Companion	2007	DBLP DOI BibTeX RDF	specification, refactorings, detection, correction, meta-modelling, code smells, antipatterns, design defects
11	Juan C. Quiroz, Anil Shankar, Sergiu M. Dascalu, Sushil J. Louis	Software Environment for Research on Evolving User Interface Designs.	ICSEA	2007	DBLP DOI BibTeX RDF
11	Siddharth Garg, Diana Marculescu	Interactive presentation: System-level process variation driven throughput analysis for single and multiple voltage-frequency island designs.	DATE	2007	DBLP DOI BibTeX RDF
11	Federico Angiolini, M. Haykel Ben Jamaa, David Atienza, Luca Benini, Giovanni De Micheli	Interactive presentation: Improving the fault tolerance of nanometric PLA designs.	DATE	2007	DBLP DOI BibTeX RDF
11	Ghiath Al Sammane, Mohamed H. Zaki, Sofiène Tahar	A symbolic methodology for the verification of analog and mixed signal designs.	DATE	2007	DBLP DOI BibTeX RDF