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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 3674 occurrences of 1433 keywords
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Results
Found 5812 publication records. Showing 5812 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
17 | Yu-Ju Hong, Ya-Shih Huang, Juinn-Dar Huang |
Simultaneous data transfer routing and scheduling for interconnect minimization in multicycle communication architecture. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi |
A Novel Local Interconnect Architecture for Variable Grain Logic Cell. |
ARC |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Saroj K. Nayak |
Carbon nanotube, graphene and atomic wires as next generation interconnects: current status and future promise. |
SLIP |
2009 |
DBLP DOI BibTeX RDF |
quantum simulation, performance, design, reliability |
17 | Xu He, Sheqin Dong, Xianlong Hong, Satoshi Goto |
Integrated interlayer via planning and pin assignment for 3D ICs. |
SLIP |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Jonggab Kil, Jie Gu 0003, Chris H. Kim |
A High-Speed Variation-Tolerant Interconnect Technique for Sub-Threshold Circuits Using Capacitive Boosting. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Matthias Kühnle, Michael Hübner 0001, Jürgen Becker 0001, Antonio Deledda, Claudio Mucci, Florian Ries, Marcello Coppola, Lorenzo Pieralisi, Riccardo Locatelli, Giuseppe Maruccia, Tommaso DeMarco, Fabio Campi |
An Interconnect Strategy for a Heterogeneous, Reconfigurable SoC. |
IEEE Des. Test Comput. |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Mladen Berekovic, Frank Bouwens, Tom Vander Aa, Diederik Verkest |
Interconnect Power Analysis for a Coarse-Grained Reconfigurable Array Processor. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong |
FPGA interconnect design using logical effort. |
FPGA |
2008 |
DBLP DOI BibTeX RDF |
FPGA, logical effort |
17 | M. Frank Chang, Jason Cong, Adam Kaplan, Mishali Naik, Glenn Reinman, Eran Socher, Sai-Wang Tam |
CMP network-on-chip overlaid with multi-band RF-interconnect. |
HPCA |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Quan Chen, Ngai Wong |
Efficient numerical modeling of random rough surface effects for interconnect internal impedance extraction. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Luca P. Carloni, Andrew B. Kahng, Swamy Muddu, Alessandro Pinto, Kambiz Samadi, Puneet Sharma |
Interconnect modeling for improved system-level design optimization. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Guofei Zhou, Li Su 0001, Depeng Jin, Lieguang Zeng |
A delay model for interconnect trees based on ABCD matrix. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Saihua Lin, Yu Wang 0002, Rong Luo, Huazhong Yang |
A capacitive boosted buffer technique for high-speed process-variation-tolerant interconnect in UDVS application. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Wei-Sheng Huang, Yu-Ru Hong, Juinn-Dar Huang, Ya-Shih Huang |
A multicycle communication architecture and synthesis flow for Global interconnect Resource Sharing. |
ASP-DAC |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Ruben Filipe Cardoso da Fonseca, Daniela Carneiro da Cruz, Pedro Rangel Henriques, Maria João Varanda Pereira |
How to Interconnect Operational and Behavioral Views of Web Applications. |
ICPC |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Heiner Giefers |
Reconfigurable many-cores with lean interconnect. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong |
FPGA interconnect design using logical effort. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Konrad J. Kulikowski, Vyas Venkataraman, Zhen Wang 0001, Alexander Taubin, Mark G. Karpovsky |
Asynchronous balanced gates tolerant to interconnect variability. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Charbel J. Akl, Magdy A. Bayoumi |
Assumers for high-speed single and multi-cycle on-chip interconnect with low repeater count. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
high-speed signaling, repeater, wires |
17 | Yu Zhou, Somnath Paul, Swarup Bhunia |
Towards Uniform Temperature Distribution in SOI Circuits Using Carbon Nanotube Based Thermal Interconnect. |
ISQED |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Thomas Lenart, Henrik Svensson, Viktor Öwall |
A Hybrid Interconnect Network-on-Chip and a Transaction Level Modeling Approach for Reconfigurable Computing. |
DELTA |
2008 |
DBLP DOI BibTeX RDF |
SCENIC, Network-on-Chip, Reconfigurable Computing, TLM, 2D Mesh |
17 | James Psota, Anant Agarwal |
rMPI: Message Passing on Multicore Processors with On-Chip Interconnect. |
HiPEAC |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Jerry Bautista |
Tera-scale computing and interconnect challenges. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
die stacking, parallel computing, many core |
17 | Tarek Moselhy, Luca Daniel |
Stochastic integral equation solver for efficient variation-aware interconnect extraction. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
Neumann expansion, polynomial chaos expansion, stochastic field solvers, variation-aware extraction, surface roughness |
17 | Wim Heirman, Joni Dambre, Dirk Stroobandt, Jan M. Van Campenhout |
Rent's rule and parallel programs: characterizing network traffic behavior. |
SLIP |
2008 |
DBLP DOI BibTeX RDF |
network traffic behavior, locality, network-on-chip, characterization, Rent's rule |
17 | Tuhina Samanta, Prasun Ghosal, Hafizur Rahaman 0001, Parthasarathi Dasgupta |
Revisiting fidelity: a case of elmore-based Y-routing trees. |
SLIP |
2008 |
DBLP DOI BibTeX RDF |
routing, Steiner trees, fidelity, rank correlation |
17 | Shiyan Hu, Qiuyang Li, Jiang Hu, Peng Li 0001 |
Utilizing Redundancy for Timing Critical Interconnect. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Wenyi Feng, Jonathan W. Greene |
Post-Placement Interconnect Entropy. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar |
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. |
Int. J. Parallel Program. |
2007 |
DBLP DOI BibTeX RDF |
Performance evaluation, VLIW, ASIP, Clustered VLIW processors |
17 | Amitabh Chaudhary, Danny Z. Chen, Xiaobo Sharon Hu, Michael T. Niemier, Ramprasad Ravichandran, Kevin Whitton |
Fabricatable Interconnect and Molecular QCA Circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Lili Zhou, Cherry Wakayama, C.-J. Richard Shi |
CASCADE: A Standard Supercell Design Methodology With Congestion-Driven Placement for Three-Dimensional Interconnect-Heavy Very Large-Scale Integrated Circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Drew Wingard |
Reflections on 10 Years as a Commercial On-Chip Interconnect Provider. |
NOCS |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Xin Hu 0007, Tarek Moselhy, Jacob K. White 0001, Luca Daniel |
Optimization-based wideband basis functions for efficient interconnect extraction. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Thuyen Le, Tilman Glökler, Jason Baumgartner |
Formal verification of a pervasive interconnect bus system in a high-performance microprocessor. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Jingye Xu, Abinash Roy, Masud H. Chowdhury |
Interactive presentation: Analysis of power consumption and BER of flip-flop based interconnect pipelining. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong |
Statistical model order reduction for interconnect circuits considering spatial correlations. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Junki Seita, Hiroyuki Ito, Kenichi Okada, Takashi Sato, Kazuya Masu |
A Multi-Drop Transmission-Line Interconnect in Si LSI. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Arthur Nieuwoudt, Mehboob Alam, Yehia Massoud |
Reduced-Order Wide-Band Interconnect Model Realization using Filter-Based Spline Interpolation. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Farshad Safaei, Ahmad Khonsari, Mahmood Fathy, Amirhossein Shantia, Mohamed Ould-Khaoua |
Evaluating the Performance of Adaptive Fault-Tolerant Routing Algorithms for Wormhole-Switched Mesh Interconnect Networks. |
IPDPS |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Hong Li, Jitesh Jain, Cheng-Kok Koh, Venkataramanan Balakrishnan |
A fast band-matching technique for interconnect inductance modeling. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Frank Huebbers, Ali Dasdan, Yehea I. Ismail |
Multi-layer interconnect performance corners for variation-aware timing analysis. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Taha Amiralli, Anestis Dounavis |
Macromodeling for Nonlinear Distributed Interconnect Networks. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Abinash Roy, Masud H. Chowdhury |
Global Interconnect Optimization in the Presence of On-chip Inductance. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Ming-Hong Lai, Chia-Chi Chu, Wu-Shiung Feng |
Applications of AOGL Model-Order Reduction Techniques in Interconnect Analysis. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Jingye Xu, Abinash Roy, Masud H. Chowdhury |
Power Consumption Analysis of Flip-flop Based Interconnect Pipelining. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
17 | H. J. Kadim |
Analytical Modelling for Adaptive Multi-Purpose On-Chip Optical Interconnect. |
AHS |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Farshad Safaei, Mahmood Fathy, Ahmad Khonsari, Mohamed Ould-Khaoua, Hosein Shafiei, S. Khosravipour |
On Quantifying Fault Patterns of the Mesh Interconnect Networks. |
AINA |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Kyoung-Hwan Lim, YongHwan Kim, Taewhan Kim |
Interconnect and Communication Synthesis for Distributed Register-File Microarchitecture. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Louis Scheffer |
CAD Implications of New Interconnect Technologies. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
17 | J. Balachandran, Steven Brebels, Geert Carchon, Maarten Kuijk, Walter De Raedt, Bart Nauwelaers, Eric Beyne |
Wafer-level package interconnect options. |
IEEE Trans. Very Large Scale Integr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Soroush Abbaspour, Massoud Pedram, Amir H. Ajami, Chandramouli V. Kashyap |
Fast Interconnect and Gate Timing Analysis for Performance Optimization. |
IEEE Trans. Very Large Scale Integr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Girish Venkataramani, Tobias Bjerregaard, Tiberiu Chelcea, Seth Copen Goldstein |
Hardware compilation of application-specific memory-access interconnect. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Yan Lin 0001, Lei He 0001 |
Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Wenjian Yu, Mengsheng Zhang, Zeyi Wang |
Efficient 3-D extraction of interconnect capacitance considering floating metal fills with boundary element method. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Shih-Yu Yang, Christos A. Papachristou |
A method for detecting interconnect DSM defects in systems on chip. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Supreet Joshi, Dinesh Sharma |
A Novel Low Power Multilevel Current Mode Interconnect System. |
ISVLSI |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Olaf Schneider, Frank Schmitz, Ivan Kondov, Thomas Brandel |
OpusIB - Grid Enabled Opteron Cluster with InfiniBand Interconnect. |
PARA |
2006 |
DBLP DOI BibTeX RDF |
Cluster, Middleware, Grid, File system, InfiniBand, SAN |
17 | Wenyi Feng, Jonathan W. Greene |
Post-placement interconnect entropy. |
FPGA |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Se-Joong Lee, Kwanho Kim, Hyejung Kim, Namjun Cho, Hoi-Jun Yoo |
A network-on-chip with 3Gbps/wire serialized on-chip interconnect using adaptive control schemes. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Federico Angiolini, Paolo Meloni, Salvatore Carta, Luca Benini, Luigi Raffo |
Contrasting a NoC and a traditional interconnect fabric with layout awareness. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Frank Liu 0001 |
A practical method to estimate interconnect responses to variabilities. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Michal Kopec, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka |
Test-per-Clock Detection, Localization and Identification of Interconnect Faults. |
ETS |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Rahul Nagpal, Y. N. Srikant |
Exploring Energy-Performance Trade-Offs for Heterogeneous Interconnect Clustered VLIW Processors. |
HiPC |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Mark R. Greenstreet, Jihong Ren |
Surfing Interconnect. |
ASYNC |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Ya-Chi Yang, Cheng-Kok Koh, Venkataramanan Balakrishnan |
Adaptive admittance-based conductor meshing for interconnect analysis. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Konstantin Moiseev, Shmuel Wimer, Avinoam Kolodny |
Timing optimization of interconnect by simultaneous net-ordering, wire sizing and spacing. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Chia-Chi Chu, Ming-Hong Lai, Wu-Shiung Feng |
The global Lanczos method for MIMO interconnect order reductions. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Shuji Tsukiyama, Masahiko Tomita |
An algorithm for calculating correlation coefficients between Elmore interconnect delays. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Thomas D. Richardson, Chrysostomos Nicopoulos, Dongkook Park, Narayanan Vijaykrishnan, Yuan Xie 0001, Chita R. Das, Vijay Degalahal |
A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks. |
VLSI Design |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Lele Jiang, Junfa Mao |
Global Interconnect Analysis and Optimization for Nanometer Scale VLSI. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Ming-Hong Lai, Chia-Chi Chu, Wu-Shiung Feng |
The Multiple Point Global Lanczos Method for MIMO Interconnect Model-Order Reductions. |
APCCAS |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Wolfgang Klingauf, Robert Günzel, Oliver Bringmann 0001, Pavel Parfuntseu, Mark Burton |
GreenBus: a generic interconnect fabric for transaction level modelling. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
SoC, SystemC, TLM, on-chip communication |
17 | Jin Guo 0001, Antonis Papanikolaou, Pol Marchal, Francky Catthoor |
Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture. |
SLIP |
2006 |
DBLP DOI BibTeX RDF |
segmented bus, floorplanning, trade-offs |
17 | Avinash Karanth Kodi, Ahmed Louri |
Design of a High-Speed Optical Interconnect for Scalable Shared-Memory Multiprocessors. |
IEEE Micro |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Yu Cao 0001, Xuejue Huang, Dennis Sylvester, Tsu-Jae King 0001, Chenming Hu |
Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design. |
IEEE Trans. Very Large Scale Integr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla |
Global Passivity Enforcement Algorithm for Macromodels of Interconnect Subnetworks Characterized by Tabulated Data. |
IEEE Trans. Very Large Scale Integr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
17 | T. Yamashita, C. J. Summers |
Evaluation of self-collimated beams in photonic crystals for optical interconnect. |
IEEE J. Sel. Areas Commun. |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Giorgos Dimitrakopoulos, Dimitris Nikolos |
Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar |
Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Junpei Inoue, Hiroyuki Ito, Shinichiro Gomi, Takanori Kyogoku, Takumi Uezono, Kenichi Okada, Kazuya Masu |
Evaluation of on-chip transmission line interconnect using wire length distribution. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Jia Wang 0003, Hai Zhou 0001 |
Interconnect estimation without packing via ACG floorplans. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Bang Liu, Xuan Zeng 0001, Yangfeng Su, Jun Tao 0001, Zhaojun Bai, Charles C. Chiang, Dian Zhou |
Block SAPOR: block Second-order Arnoldi method for Passive Order Reduction of multi-input multi-output RCS interconnect circuits. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Min Ma, Mourad Oulmane, Nicholas C. Rumin |
Explicit delay metric for interconnect optimization. |
ISCAS (3) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Alexandre Landry, Mohamed Nekili, Yvon Savaria |
A novel 2 GHz multi-layer AMBA high-speed bus interconnect matrix for SoC platforms. |
ISCAS (4) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Yunfeng Wang, Jinian Bian, Xianlong Hong |
Interconnect delay optimization via high level re-synthesis after floorplanning. |
ISCAS (6) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Yici Cai, Yibo Wang, Xianlong Hong |
A global interconnect optimization algorithm under accurate delay model using solution space smoothing. |
ISCAS (1) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Chia-Chi Chu, Herng-Jer Lee, Wu-Shiung Feng, Ming-Hong Lai |
Interconnect model reductions by using the AORA algorithm with considering the adjoint network. |
ISCAS (2) |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Vasilis F. Pavlidis, Eby G. Friedman |
Interconnect delay minimization through interlayer via placement in 3-D ICs. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
RC interconnects, elmore delay, 3-D ICs |
17 | Hao Yu 0001, Lei He 0001 |
Staggered Twisted-Bundle Interconnect for Crosstalk and Delay Reduction. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Jiaxing Sun, Yun Zheng, Qing Ye, Tianchun Ye 0001 |
Interconnect Delay and Slew Metrics Using the First Three Moments. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
D3M, ID3M, SS3M, SIS3M |
17 | Chun-Chieh Wang, Jing-Jia Liou, Yen-Lin Peng, Chih-Tsun Huang, Cheng-Wen Wu |
A BIST Scheme for FPGA Interconnect Delay Faults. |
VTS |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Takumi Uezono, Junpei Inoue, Takanori Kyogoku, Kenichi Okada, Kazuya Masu |
Prediction of delay time for future LSI using on-chip transmission line interconnects. |
SLIP |
2005 |
DBLP DOI BibTeX RDF |
|
17 | Katherine Shu-Min Li, Chung-Len Lee 0001, Yao-Wen Chang, Chauchin Su, Jwu E. Chen |
Multilevel full-chip routing with testability and yield enhancement. |
SLIP |
2005 |
DBLP DOI BibTeX RDF |
multilevel routing, yield, testability |
17 | Young-Su Kwon, Payam Lajevardi, Anantha P. Chandrakasan, Frank Honoré, Donald E. Troxel |
A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool. |
SLIP |
2005 |
DBLP DOI BibTeX RDF |
3-D FPGA, wire resource prediction |
17 | György Miklós, Ferenc Kubinszky, András Rácz, Zoltán Richard Turányi, András Gergely Valkó, Miklós Aurél Rónai, Sándor Molnár |
A novel scheme to interconnect multiple frequency hopping channels into an ad hoc network. |
ACM SIGMOBILE Mob. Comput. Commun. Rev. |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Chao-Yang Yeh, Malgorzata Marek-Sadowska |
Sequential delay budgeting with interconnect prediction. |
IEEE Trans. Very Large Scale Integr. Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
17 | André DeHon, Raphael Rubin |
Design of FPGA interconnect for multilevel metallization. |
IEEE Trans. Very Large Scale Integr. Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Hong-Yi Huang, Shih-Lun Chen |
Interconnect accelerating techniques for sub-100-nm gigascale systems. |
IEEE Trans. Very Large Scale Integr. Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Atsushi Kurokawa, Nobuto Ono, Tetsuro Kage, Hiroo Masuda |
DEPOGIT: dense power-ground interconnect architecture for physical design integrity. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
17 | Xiren Wang, Deyan Liu, Wenjian Yu, Zeyi Wang |
Fast and accurate extraction of 3-D interconnect resistance: improved quasi-multiple medium accelerated BEM method. |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
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