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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 4401 occurrences of 2030 keywords
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Results
Found 5686 publication records. Showing 5677 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
20 | Qin Zhao, Bart Mesman, Henk Corporaal |
Limited Address Range Architecture for Reducing Code Size in Embedded Processors. |
SCOPES |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Mark Stephenson, Una-May O'Reilly, Martin C. Martin, Saman P. Amarasinghe |
Genetic Programming Applied to Compiler Heuristic Optimization. |
EuroGP |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Yi Qian, Steve Carr 0001, Philip H. Sweany |
Optimizing Loop Performance for Clustered VLIW Architectures. |
IEEE PACT |
2002 |
DBLP DOI BibTeX RDF |
|
20 | Ho-Seop Kim, James E. Smith 0001 |
An Instruction Set and Microarchitecture for Instruction Level Distributed Processing. |
ISCA |
2002 |
DBLP DOI BibTeX RDF |
|
20 | Roman L. Lysecky, Frank Vahid, Tony Givargis |
Techniques for Reducing Read Latency of Core Bus Wrappers. |
DATE |
2000 |
DBLP DOI BibTeX RDF |
bus wrapper, interfacing, system-on-a-chip, intellectual property, Cores, design reuse, on-chip bus |
20 | Santanu Dutta, Wayne H. Wolf |
A circuit-driven design methodology for video signal-processing datapath elements. |
IEEE Trans. Very Large Scale Integr. Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
20 | Kaisheng Wang, Ted Zhihong Yu, Edwin Hsing-Mean Sha |
RCRS: A Framework for Loop Scheduling with Limited Number of Registers. |
Great Lakes Symposium on VLSI |
1998 |
DBLP DOI BibTeX RDF |
retiming, rotation, data-flow graphs, Loop scheduling, registers |
20 | Dilip K. Bhavsar |
Testing Interconnections to Static RAMs. |
IEEE Des. Test Comput. |
1991 |
DBLP DOI BibTeX RDF |
|
20 | Vladimir V. Chepyzhov, Ben J. M. Smeets |
On A Fast Correlation Attack on Certain Stream Ciphers. |
EUROCRYPT |
1991 |
DBLP DOI BibTeX RDF |
|
20 | Jørgen Brandt, Ivan Damgård, Peter Landrock |
Anonymous and Verifiable Registration in Databases. |
EUROCRYPT |
1988 |
DBLP DOI BibTeX RDF |
|
20 | Donald W. Davies, Graeme I. P. Parkin |
The average Cycle size of the Key-Stream in Output Feedback Encipherment. |
EUROCRYPT |
1982 |
DBLP DOI BibTeX RDF |
|
20 | Vincent J. DiGri, Jane E. King |
The Share 709 System: Input-Output Translation. |
J. ACM |
1959 |
DBLP DOI BibTeX RDF |
|
16 | Brahim Al Farisi, Karel Bruneel, Harald Devos, Dirk Stroobandt |
Automatic tool flow for shift-register-LUT reconfiguration: making run-time reconfiguration fast and easy (abstract only). |
FPGA |
2010 |
DBLP DOI BibTeX RDF |
parameterizable configurations, tmap, fpga, reconfigurable computing, run-time reconfiguration, srl, icap |
16 | Pey-Chang Kent Lin, Sunil P. Khatri |
VLSI implementation of a non-linear feedback shift register for high-speed cryptography applications. |
ACM Great Lakes Symposium on VLSI |
2010 |
DBLP DOI BibTeX RDF |
NLFSR, stream cipher, pseudo-random sequence |
16 | Baris Taskin, Andy Chiu, Jonathan Salkind, Daniel Venutolo |
A shift-register-based QCA memory architecture. |
ACM J. Emerg. Technol. Comput. Syst. |
2009 |
DBLP DOI BibTeX RDF |
clocking, Quantum-dot cellular automata, memory design |
16 | Shih Yu Chang, Hsiao-Chun Wu, Ai-Chun Pang |
Theoretical exploration of pattern attributes for maximum-length shift-register sequences. |
IWCMC |
2009 |
DBLP DOI BibTeX RDF |
berlekamp's algorithm, pattern attribute, finite fields, traveling salesman problem, m-sequences |
16 | Jongeun Lee, Aviral Shrivastava |
Compiler-managed register file protection for energy-efficient soft error reduction. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Raju Halder, Parthasarathi Dasgupta, Saptarshi Naskar, Samar Sen-Sarma |
An internet-based IP protection scheme for circuit designs using linear feedback shift register (LFSR)-based locking. |
SBCCI |
2009 |
DBLP DOI BibTeX RDF |
intellectual property protection (IPP), watermarking, encryption, decryption |
16 | Khushboo Kanjani, Hyunyoung Lee, Jennifer L. Welch |
Byzantine fault-tolerant implementation of a multi-writer regular register. |
IPDPS |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Jyh-Shian Wang, I-Wei Wu, Yu-Sheng Chen, Jean Jyh-Jiun Shann, Wei-Chung Hsu |
Reducing Code Size by Graph Coloring Register Allocation and Assignment Algorithm for Mixed-Width ISA Processor. |
CSE (2) |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Wenting Hou, Dick Liu, Pei-Hsin Ho |
Automatic register banking for low-power clock trees. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Héctor Navarro, Saeid Nooshabadi, Juan A. Montiel-Nelson, Victor Navarro-Botello, Javier Sosa, José C. García 0001 |
A geometric approach to register transfer level satisfiability. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
16 | Xuejun Yang, Li Wang 0027, Jingling Xue, Yu Deng 0001, Ying Zhang 0032 |
Comparability graph coloring for optimizing utilization of stream register files in stream processors. |
PPoPP |
2009 |
DBLP DOI BibTeX RDF |
comparability graph coloring, stream programming, stream processor, software-managed cache |
16 | Lei Wang 0003, Niral Patel |
Improving Error Tolerance for Multithreaded Register Files. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi |
A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Felipe Machado, Teresa Riesgo, Yago Torroja |
Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level. |
PATMOS |
2008 |
DBLP DOI BibTeX RDF |
activity estimation, CAD, VHDL, BDD, power estimation, RTL, Switching activity, circuit partition, digital circuit design |
16 | David B. Whalley, Gary S. Tyson |
Enhancing the effectiveness of utilizing an instruction register file. |
IPDPS |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Andrea Masini, Luca Viganò 0001, Margherita Zorzi |
A Qualitative Modal Representation of Quantum Register Transformations. |
ISMVL |
2008 |
DBLP DOI BibTeX RDF |
quantum registers, modal logic, quantum logic |
16 | Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri |
A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Anish Muttreja, Srivaths Ravi 0001, Niraj K. Jha |
Variability-Tolerant Register-Transfer Level Synthesis. |
VLSI Design |
2008 |
DBLP DOI BibTeX RDF |
|
16 | Shih-Chang Hsia, Szu-Hong Wang |
Shift-Register-Based Data Transposition for Cost-Effective Discrete Cosine Transform. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Loganathan Lingappan, Niraj K. Jha |
Efficient Design for Testability Solution Based on Unsatisfiability for Register-Transfer Level Circuits. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Mona Safar, Mohamed Shalan, M. Watheq El-Kharashi, Ashraf Salem |
Interactive presentation: A shift register based clause evaluator for reconfigurable SAT solver. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Florent Bouchez, Alain Darte, Fabrice Rastello |
On the Complexity of Register Coalescing. |
CGO |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Richard Stern, Nikhil Joshi, Kaijie Wu 0001, Ramesh Karri |
Register Transfer Level Concurrent Error Detection in Elliptic Curve Crypto Implementations. |
FDTC |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton |
Fast Minimum-Register Retiming via Binary Maximum-Flow. |
FMCAD |
2007 |
DBLP DOI BibTeX RDF |
Sequential Verification, Retiming, Maximum Flow, State Minimization |
16 | Hiroyuki Iwata, Tomokazu Yoneda, Hideo Fujiwara |
A DFT Method for Time Expansion Model at Register Transfer Level. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
16 | Kaijie Wu 0001, Ramesh Karri |
Algorithm-level recomputing with shifted operands-a register transfer level concurrent error detection technique. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Chiranjeev Kumar, Hemant Kumar Pande, Rajeev Tripathi |
A New Boundary Location Register Signalling Protocol for Inter-system Roaming. |
CNSR |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri |
Delay Constrained Register Transfer Level Dynamic Power Estimation. |
PATMOS |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Jamel Tayeb, Smaïl Niar |
Adapting EPIC Architecture's Register Stack for Virtual Stack Machines. |
DSD |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Xiaoyao Liang, David M. Brooks |
Mitigating the Impact of Process Variations on Processor Register Files and Execution Units. |
MICRO |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Christopher Lupo, Kent D. Wilken |
Post Register Allocation Spill Code Optimization. |
CGO |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Solomon W. Golomb |
Shift Register Sequences - A Retrospective Account. |
SETA |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Li-Ping Wang 0001 |
The Vector Key Equation and Multisequence Shift Register Synthesis. |
AAECC |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Abhinav Das, Rao Fu, Antonia Zhai, Wei-Chung Hsu |
Issues and Support for Dynamic Register Allocation. |
Asia-Pacific Computer Systems Architecture Conference |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis |
Accelerating Color Space Conversion Using Extended Subwords and the Matrix Register File. |
ISM |
2006 |
DBLP DOI BibTeX RDF |
Color space conversion, SIMD architectures, multimedia extensions |
16 | Yong Shim, Youngkwon Jo, Soo Hwan Kim, Suki Kim, Kwanjun Cho |
A register controlled delay locked loop using a TDC and a new fine delay line scheme. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Fabio Campi, Paolo Zoffoli, Claudio Mucci, Massimo Bocchi, Antonio Deledda, Mario de Dominicis, Arseni Vitkovski |
A stream register file unit for reconfigurable processors. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Youcef Bouchebaba, Gabriela Nicolescu, El Mostapha Aboulhamid, Fabien Coelho |
Buffer and register allocation for memory space optimization. |
ASAP |
2006 |
DBLP DOI BibTeX RDF |
|
16 | Noureddine Chabini, El Mostapha Aboulhamid, Ismaïl Chabini, Yvon Savaria |
Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques. |
ACM Trans. Design Autom. Electr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
multiphase, sequential circuit, software pipelining, clock, Retiming |
16 | Shadi T. Khasawneh, Kanad Ghose |
An Adaptive Technique for Reducing Leakage and Dynamic Power in Register Files and Reorder Buffers. |
PATMOS |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Nastaran Baradaran, Pedro C. Diniz |
A Register Allocation Algorithm in the Presence of Scalar Replacement for Fine-Grain Configurable Architectures. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Ho Fai Ko, Qiang Xu 0001, Nicola Nicolici |
Register-transfer level functional scan for hierarchical designs. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Berndt M. Gammel, Rainer Göttfert |
Linear Filtering of Nonlinear Shift-Register Sequences. |
WCC |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Loganathan Lingappan, Niraj K. Jha |
Unsatisfiability Based Efficient Design for Testability Solution for Register-Transfer Level Circuits. |
VTS |
2005 |
DBLP DOI BibTeX RDF |
|
16 | Daniel L. Rosenband |
The ephemeral history register: flexible scheduling for rule-based designs. |
MEMOCODE |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Fernand Feltz, Patrik Hitzelberger |
Towards the Idea of a One-Stop-Administration: Experiences from the Reorganisation of the Register of Companies in Luxembourg. |
EGOV |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Nuwan Jayasena, Mattan Erez, Jung Ho Ahn, William J. Dally |
Stream Register Files with Indexed Access. |
HPCA |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Markus Holzer 0001, Martin Kutrib |
Register Complexity of LOOP-, WHILE-, and GOTO-Programs. |
MCU |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Fernando Rodríguez Salazar, John R. Barker |
Linear Feedback Shift Register Interconnection Networks. |
IPDPS |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Jae-Sun Han, Tae-Jin Kim, Chanho Lee |
High performance Viterbi decoder using modified register exchange methods. |
ISCAS (3) |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Claus Weihs, Christoph Reuter, Uwe Ligges |
Register Classification by Timbre. |
GfKl |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Jan Müller 0001, Dirk Fimmel, Renate Merker |
Optimal Loop Scheduling with Register Constraints Using Flow Graphs. |
ISPAN |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Fernanda Kri, Marc Feeley |
Genetic Instruction Scheduling and Register Allocation. |
SCCC |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul |
A test evaluation technique for VLSI circuits using register-transfer level fault modeling. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Jaume Abella 0001, Antonio González 0001 |
Power-Aware Adaptive Issue Queue and Register File. |
HiPC |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Michael V. Boldasov, Elena G. Sokolova |
QGen - Generation Module for the Register Restricted InBASE System. |
CICLing |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Christian Andersson |
Register Allocation by Optimal Graph Coloring. |
CC |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Kaijie Wu 0001, Ramesh Karri |
Register Transfer Level Approach to Hybrid Time and Hardware Redundancy Based Fault Secure Datapath Synthesis. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Ramesh Karri, Kaijie Wu 0001 |
Algorithm level re-computing using implementation diversity: a register transfer level concurrent error detection technique. |
IEEE Trans. Very Large Scale Integr. Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Bruce S. Greene, Samiha Mourad |
Partial Scan Testing on the Register-Transfer Level. |
J. Electron. Test. |
2002 |
DBLP DOI BibTeX RDF |
RT-level, fault coverage, partial scan, scan design, graph reduction |
16 | Jaewook Shin, Jacqueline Chame, Mary W. Hall |
Compiler-Controlled Caching in Superword Register Files for Multimedia Extension Architectures. |
IEEE PACT |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Adam Smyk, Marek Tudruj |
Irregular Fine-Grain Parallel Computing Based on the Slide Register Window Architecture of Hitachi SR2201. |
PARELEC |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Stefan R. Meier, Mario Steinert, Steffen Buch |
Testability of path history memories with register-exchange architecture used in Viterbi-decoders. |
ISCAS (3) |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Jarmo Takala, Tuomas Järvinen, Jari Nikara |
Register-based reordering networks for matrix transpose. |
ISCAS (4) |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Giorgos Dimitrakopoulos, Dimitris Nikolos, Dimitris Bakalis |
Bit-Serial Test Pattern Generation by an Accumulator Behaving as a Non-Linear Feedback Shift Register. |
IOLTW |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Indradeep Ghosh, Krishna Sekar, Vamsi Boppana |
Design for Verification at the Register Transfer Level. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Dipankar Sarkar 0001 |
Register Transfer Operation Analysis during Data Path Verification. |
ASP-DAC/VLSI Design |
2002 |
DBLP DOI BibTeX RDF |
Sequential Circuit Verification, Control Part - Data Path, Data Path Verification, RTL Behaviours |
16 | Tsuyoshi Isshiki, Akihisa Ohta, T. Watanabe, T. Nakada, K. Akahane, I. Sisla, Dongju Li, Hiroaki Kunieda |
High density bit-serial FPGA with LUT embedding shift register function. |
APCCAS (1) |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha |
TAO: regular expression-based register-transfer level testability analysis and optimization. |
IEEE Trans. Very Large Scale Integr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Indradeep Ghosh, Masahiro Fujita |
Automatic test pattern generation for functional register-transferlevel circuits using assignment decision diagrams. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Jan A. Bergstra, Alban Ponse |
Register-machine based processes. |
J. ACM |
2001 |
DBLP DOI BibTeX RDF |
Kleene star, push-down operation, concurrency, computability, process algebra, expressivity, iteration, Bisimulation equivalence |
16 | Matthew J. Clarkson, Daniel Rueckert, Derek L. G. Hill, David J. Hawkes |
Using Photo-Consistency to Register 2D Optical Images of the Human Face to a 3D Surface Model. |
IEEE Trans. Pattern Anal. Mach. Intell. |
2001 |
DBLP DOI BibTeX RDF |
2D-3D registration, photo-consistency, extrinsic parameter calibration, similarity measures, pose estimation |
16 | Guilherme Ottoni, Sandro Rigo, Guido Araujo, Subramanian Rajagopalan, Sharad Malik |
Optimal Live Range Merge for Address Register Allocation in Embedded Programs. |
CC |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Alvin R. Albrecht, Alan J. Hu |
Register Transformations with Multiple Clock Domains. |
CHARME |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Tuomas Järvinen, Jarmo Takala, David Akopian, Jukka Saarinen |
Register-based multi-port perfect shuffle networks. |
ISCAS (4) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Dilip K. Bhavsar, Rishan Tan |
Observability Register Architecture For Efficient Production Test And Debug Of Vlsi Circuits. |
VLSI Design |
2001 |
DBLP DOI BibTeX RDF |
|
16 | David May 0001, Henk L. Muller, Nigel P. Smart |
Random Register Renaming to Foil DPA. |
CHES |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Jens Schönherr, Bernd Straube |
Automatic Equivalence Check of Circuit Descriptions at Clocked Algorithmic and Register Transfer Level. |
DATE |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Pierre L'Ecuyer, François Panneton |
A new class of linear feedback shift register generators. |
WSC |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Suhyun Kim, Soo-Mook Moon, Jinpyo Park, Kemal Ebcioglu |
Unroll-based register coalescing. |
ICS |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Yoochang Jung, Stefan G. Berg, Donglok Kim, Yongmin Kim 0001 |
A Register File with Transposed Access Mode. |
ICCD |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Anand Raghunathan, Sujit Dey, Niraj K. Jha |
Register transfer level power optimization with emphasis on glitch analysis and reduction. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Klaus Eckl, Christian Legl |
Retiming Sequential Circuits with Multiple Register Classes. |
DATE |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Priyank Kalla, Maciej J. Ciesielski |
Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence. |
DATE |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Mehul Motani, Chris Heegard |
Computing Weight Distributions of Convolutional Codes via Shift Register Synthesis. |
AAECC |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Yumin Zhang, Xiaobo Hu 0001, Danny Z. Chen |
Low energy register allocation beyond basic blocks. |
ISCAS (1) |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Khaled M. Elleithy, E. G. Abd-El-Fattah |
A Genetic Algorithm for Register Allocation. |
Great Lakes Symposium on VLSI |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Stephan Avery, Marwan A. Jabri |
A three-port adiabatic register file suitable for embedded applications. |
ISLPED |
1998 |
DBLP DOI BibTeX RDF |
|
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