Search results for "designs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
11	Xiaoyuan Suo, Ying Zhu 0001, G. Scott Owen	Measuring the Complexity of Computer Security Visualization Designs.	VizSEC	2007	DBLP DOI BibTeX RDF
11	Luis A. Castillo, Lluvia Morales, Arturo González-Ferrer, Juan Fernández-Olivares, Óscar García-Pérez	Knowledge Engineering and Planning for the Automated Synthesis of Customized Learning Designs.	CAEPIA	2007	DBLP DOI BibTeX RDF
11	Ying Rao Wei, M. Z. Wang	Performance Analysis of Full-rate STBCs from Coordinate Interleaved Orthogonal Designs.	ICC	2007	DBLP DOI BibTeX RDF
11	Juan Manuel Dodero, Colin Tattersall, Daniel Burgos, Rob Koper	Transformational Techniques for Model-Driven Authoring of Learning Designs.	ICWL	2007	DBLP DOI BibTeX RDF	learning design patterns, unit of learning, Model-driven development, IMS Learning Design
11	Christian Dehlendorff, Murat Kulahci, Klaus K. Andersen	Combining Latin hypercube designs and discrete event simulation in a study of a surgical unit.	WSC	2007	DBLP DOI BibTeX RDF
11	Ann E. Kelley Sobel, Sherrie Campbell	Supporting the Formal Analysis of Software Designs.	CSEE&T	2007	DBLP DOI BibTeX RDF
11	Bing Zhao, Weidong Li, Shu Jian, Lequan Min	Two Theorems on the Robust Designs for Pattern Matching CNNs.	ISNN (3)	2007	DBLP DOI BibTeX RDF
11	Yong Zhan, Tianpei Zhang, Sachin S. Sapatnekar	Module assignment for pin-limited designs under the stacked-Vdd paradigm.	ICCAD	2007	DBLP DOI BibTeX RDF
11	Steve J. Westerman, E. J. Sutherland, L. Robinson, H. Powell, Gareth C. Tuck	A Multi-method Approach to the Assessment of Web Page Designs.	ACII	2007	DBLP DOI BibTeX RDF
11	Juan M. Cebrian, Juan L. Aragón, José M. García 0001, Stefanos Kaxiras	Adaptive VP decay: making value predictors leakage-efficient designs for high performance processors.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	leakage, value prediction, energy efficient architectures, cache decay
11	Martin Kuhlemann, Sven Apel, Thomas Leich	Streamlining Feature-Oriented Designs.	SC@ETAPS	2007	DBLP DOI BibTeX RDF
11	Esther Guerra, Daniel Sanz, Paloma Díaz 0001, Ignacio Aedo	A Transformation-Driven Approach to the Verification of Security Policies in Web Designs.	ICWE	2007	DBLP DOI BibTeX RDF
11	Shih-Hsu Huang, Chu-Liao Wang, Man-Lin Huang	A Floorplan-Based Power Network Analysis Methodology for System-on-Chip Designs.	EUC	2007	DBLP DOI BibTeX RDF	Reused Block, Modeling, Power Consumption, Voltage Drop
11	Kaijian Shi, Zhian Lin, Yi-Min Jiang	A Power Network Synthesis Method for Industrial Power Gating Designs.	ISQED	2007	DBLP DOI BibTeX RDF
11	Yici Cai, Bin Liu 0007, Jin Shi, Qiang Zhou 0001, Xianlong Hong	Power Delivery Aware Floorplanning for Voltage Island Designs.	ISQED	2007	DBLP DOI BibTeX RDF
11	David Zaretsky, Gaurav Mittal, Robert P. Dick, Prith Banerjee	Balanced Scheduling and Operation Chaining in High-Level Synthesis for FPGA Designs.	ISQED	2007	DBLP DOI BibTeX RDF
11	Frederic Worm, Patrick Thiran, Paolo Ienne	Optimizing Checking-Logic for Reliability-Agnostic Control of Self-Calibrating Designs.	ISQED	2007	DBLP DOI BibTeX RDF
11	Marcus Seifert, Klaus-Dieter Thoben	Maintaining Dynamic Product Designs To Enable Effective Consortium Building In Virtual Breeding Envionments.	Virtual Enterprises and Collaborative Networks	2007	DBLP DOI BibTeX RDF
11	Andris Ambainis, Joseph Emerson	Quantum t-designs: t-wise Independence in the Quantum World.	CCC	2007	DBLP DOI BibTeX RDF
11	Simon Miles, Paul Groth, Steve Munroe, Michael Luck, Luc Moreau 0001	AgentPrIMe: Adapting MAS Designs to Build Confidence.	AOSE	2007	DBLP DOI BibTeX RDF
11	Tien Nguyen	EmVC: Managing Changes and Configurations in Designs of Complex, Embedded Computing Systems.	ICECCS	2007	DBLP DOI BibTeX RDF
11	Hiren D. Patel, Sandeep K. Shukla	Model-driven Validation of SystemC Designs.	DAC	2007	DBLP DOI BibTeX RDF
11	Peter Sawyer, Ricardo Gacitúa, Andrew Stone	Profiling and Tracing Stakeholder Needs.	Monterey Workshop	2007	DBLP DOI BibTeX RDF	information retrieval, natural language processing, Requirements engineering, tacit knowledge
11	Djamel Bouchaffra, Jun Tan	Structural Hidden Markov Models Using a Relation of Equivalence: Application to Automotive Designs.	Data Min. Knowl. Discov.	2006	DBLP DOI BibTeX RDF	relation of equivalence, statistical decoding, structural decoding, Hidden Markov models, local structures
11	Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman	Extraction error modeling and automated model debugging in high-performance custom designs.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
11	Masaaki Harada	Self-Orthogonal 3-(56, 12, 65) Designs and Extremal Doubly-Even Self-Dual Codes of Length 56.	Des. Codes Cryptogr.	2006	DBLP DOI BibTeX RDF	self-orthogonal design, extremal doubly-even self-dual code
11	Carl Bracken	New classes of self-complementary codes and quasi-symmetric designs.	Des. Codes Cryptogr.	2006	DBLP DOI BibTeX RDF	AMS Classification 05E20
11	Jaime Jimenez, José Luis Martín 0001, Aitzol Zuloaga, Unai Bidarte, Jagoba Arias	Comparison of two designs for the multifunction vehicle bus.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
11	Behzad Akbarpour, Sofiène Tahar	An approach for the formal verification of DSP designs using Theorem proving.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
11	Seongmoon Wang, Srimat T. Chakradhar	A scalable scan-path test point insertion technique to enhance delay fault coverage for standard scan designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
11	Wu-An Kuo, TingTing Hwang, Allen C.-H. Wu	Decomposition of instruction decoders for low-power designs.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	instruction decoder, Low power
11	Thomas Brandtner	Chip-Package Codesign Flow for Mixed-Signal SiP Designs.	IEEE Des. Test Comput.	2006	DBLP DOI BibTeX RDF	Mixed-Signal System-in-Package design, SiP
11	Carolyn B. Seaman	Combining Study Designs and Techniques Working Group Results.	Empirical Software Engineering Issues	2006	DBLP DOI BibTeX RDF
11	Marc Herbstritt, Bernd Becker 0001, Christoph Scholl 0001	Advanced SAT-Techniques for Bounded Model Checking of Blackbox Designs.	MTV	2006	DBLP DOI BibTeX RDF
11	Nagarajan Ranganathan, Ravi Namballa, Narender Hanchate	CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDL.	ISVLSI	2006	DBLP DOI BibTeX RDF
11	Edward Clarkson, James D. Foley	Browsing affordance designs for the human-centered computing education digital library.	JCDL	2006	DBLP DOI BibTeX RDF	ScentTrails, education, digital libraries, browsing, treemap
11	Daniel Karlsson, Petru Eles, Zebo Peng	Formal verification of systemc designs using a petri-net based representation.	DATE	2006	DBLP DOI BibTeX RDF
11	Roberto Cordone, Fabrizio Ferrandi, Marco D. Santambrogio, Gianluca Palermo, Donatella Sciuto	Using speculative computation and parallelizing techniques to improve scheduling of control based designs.	ASP-DAC	2006	DBLP DOI BibTeX RDF
11	Bin Liu 0007, Yici Cai, Qiang Zhou 0001, Xianlong Hong	Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs.	ASP-DAC	2006	DBLP DOI BibTeX RDF
11	Shunitsu Kohara, Naoki Tomono, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki	An interface-circuit synthesis method with configurable processor core in IP-based SoC designs.	ASP-DAC	2006	DBLP DOI BibTeX RDF
11	Natarajan Viswanathan, Min Pan, Chris C. N. Chu	FastPlace 2.0: an efficient analytical placer for mixed-mode designs.	ASP-DAC	2006	DBLP DOI BibTeX RDF
11	Moshe Deutsch, Martin C. Henson	A Relational Investigation of UTP Designs and Prescriptions.	UTP	2006	DBLP DOI BibTeX RDF
11	Simon McNicol, Serdar Boztas, Asha Rao	Traitor Tracing Against Powerful Attacks Using Combinatorial Designs.	AAECC	2006	DBLP DOI BibTeX RDF
11	Lan Lan 0005, Ying Yu Tai, Shu Lin 0001, Behshad Memari, Bahram Honary	New Constructions of Quasi-cyclic LDPC Codes Based on Two Classes of Balanced Incomplete Block Designs: For AWGN and Binary Erasure Channels.	AAECC	2006	DBLP DOI BibTeX RDF
11	Mikhail Perepletchikov, Caspar Ryan, Keith Frampton	Towards the Definition and Validation of Coupling Metrics for Predicting Maintainability in Service-Oriented Designs.	OTM Workshops (1)	2006	DBLP DOI BibTeX RDF
11	Valeria Bertacco	Formal verification for real-world designs.	SBCCI	2006	DBLP DOI BibTeX RDF
11	Jack P. C. Kleijnen	White noise assumptions revisited: regression metamodels and experimental designs in practice.	WSC	2006	DBLP DOI BibTeX RDF
11	Sami J. Habib	A Monte Carlo simulator for evaluating server placement within network topology designs.	VALUETOOLS	2006	DBLP DOI BibTeX RDF	simulation, optimization, computer-aided design, Monte Carlo, queuing theory, evolutionary approach, formulation
11	Adriana J. Berlanga, Francisco J. García-Peñalvo, Jorge Carabias	Authoring Adaptive Learning Designs Using IMS LD.	AH	2006	DBLP DOI BibTeX RDF
11	Andreas Harrer	An Approach to Organize Re-usability of Learning Designs and Collaboration Scripts of Various Granularities.	ICALT	2006	DBLP DOI BibTeX RDF
11	Peter Fröhlich 0003, Rainer Simon, Lynne Baillie, Hermann Anegg	Comparing conceptual designs for mobile access to geo-spatial information.	Mobile HCI	2006	DBLP DOI BibTeX RDF	mobile computing, augmented reality, location based services, context aware computing, user interaction, orientation
11	Sébastien Lahaie	An analysis of alternative slot auction designs for sponsored search.	EC	2006	DBLP DOI BibTeX RDF	rank by bid, rank by revenue, slot allocation, search engines, sponsored search, auction theory
11	Emma Eliason, Jonas Lundberg	The appropriateness of Swedish municipality web site designs.	NordiCHI	2006	DBLP DOI BibTeX RDF	inherited values, web site design, municipality, genre analysis
11	Chia-Tsun Wu, Wei Wang 0252, I-Chyn Wey, An-Yeu Wu	A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time.	ISCAS	2006	DBLP DOI BibTeX RDF
11	Jinping Wang, Shengjuan Huang, Xiqin He	Observer-Based Hinfinity Controller Designs for T-S Fuzzy Systems.	FSKD	2006	DBLP DOI BibTeX RDF
11	Fengming Zhang, Warren Necoechea, Peter Reiter, Yong-Bin Kim, Fabrizio Lombardi	Load Board Designs Using Compound Dot Technique and Phase Detector for Hierarchical ATE Calibrations.	DFT	2006	DBLP DOI BibTeX RDF
11	Michael Santarini, Pallab K. Chatterjee	Session EP1: Power Management and Optimization Challenges for Sub 90nm CMOS Designs- What is the Real Cost of Long Battery Life?.	ISQED	2006	DBLP DOI BibTeX RDF
11	Xiongfei Meng, Resve A. Saleh, Karim Arabi	Novel Decoupling Capacitor Designs for sub- 90nm CMOS Technology.	ISQED	2006	DBLP DOI BibTeX RDF
11	Suriyaprakash Natarajan, Srinivas Patil, Sreejit Chakravarty	Path Delay Fault Simulation on Large Industrial Designs.	VTS	2006	DBLP DOI BibTeX RDF
11	G. Girishankar, Shitanshu Tiwari	Generating Scalable Polynomial Models: Key to Low Power High Performance Designs.	VLSI Design	2006	DBLP DOI BibTeX RDF
11	Orest Pilskalns, Gunay Uyan, Anneliese Amschler Andrews	Regression Testing UML Designs.	ICSM	2006	DBLP DOI BibTeX RDF
11	Rouwaida Kanj, Rajiv V. Joshi, Sani R. Nassif	Mixture importance sampling and its application to the analysis of SRAM designs in the presence of rare failure events.	DAC	2006	DBLP DOI BibTeX RDF	statistical performance analysis, SRAM, yield prediction
11	Andrew B. Kahng	CAD challenges for leading-edge multimedia designs.	DAC	2006	DBLP DOI BibTeX RDF
11	Jaekwon Kim, Robert W. Heath Jr., Edward J. Powers	Receiver designs for Alamouti coded OFDM systems in fast fading channels.	IEEE Trans. Wirel. Commun.	2005	DBLP DOI BibTeX RDF
11	Rob Roy, Debashis Bhattacharya, Vamsi Boppana	Transistor-Level Optimization of Digital Designs with Flex Cells.	Computer	2005	DBLP DOI BibTeX RDF	ASIC design methodology, integrated circuit design, power optimization, design and test, high-performance design
11	Yury J. Ionin, Hadi Kharaghani	A Recursive Construction for New Symmetric Designs.	Des. Codes Cryptogr.	2005	DBLP DOI BibTeX RDF	regular Hadamard matrix, balanced generalized weighing matrix, symmetric design
11	Rajendra M. Pawale	Non Existence of Triangle Free Quasi-symmetric Designs.	Des. Codes Cryptogr.	2005	DBLP DOI BibTeX RDF	AMS Classification: Primary 05 B05, Secondary 05 B30, 05 B25
11	Yuanyuan Yang 0001, Jianchao Wang	Cost-Effective Designs of WDM Optical Interconnects.	IEEE Trans. Parallel Distributed Syst.	2005	DBLP DOI BibTeX RDF	multicast, permutation, network architectures, optical interconnects, Wavelength-division-multiplexing (WDM), optical switches, wavelength conversion, multistage networks, sparse crossbars
11	Kejie Lu, Shengli Fu, Xiang-Gen Xia 0001	Closed-form designs of complex orthogonal space-time block codes of rates (k+1)/(2k) for 2k-1 or 2k transmit antennas.	IEEE Trans. Inf. Theory	2005	DBLP DOI BibTeX RDF
11	Hiyam Al-Kilidar, Peter Parkin, Aybüke Aurum, D. Ross Jeffery	Evaluation of Effects of Pair Work on Quality of Designs.	Australian Software Engineering Conference	2005	DBLP DOI BibTeX RDF
11	Miroslaw Staron, Ludwik Kuzniarz	Properties of Stereotypes from the Perspective of Their Role in Designs.	MoDELS	2005	DBLP DOI BibTeX RDF
11	Kelly Nasi, Martin Danek, Theodoros Karoubalis, Zdenek Pohl	Figaro: an automatic tool flow for designs with dynamic reconfiguration (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
11	Roman Bartosinski, Martin Danek, Petr Honzík, Rudolf Matousek	Dynamic reconfiguration in FPGA-based SoC designs (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
11	Himanshu Kaul, Dennis Sylvester, David T. Blaauw, Trevor N. Mudge, Todd M. Austin	DVS for On-Chip Bus Designs Based on Timing Error Correction.	DATE	2005	DBLP DOI BibTeX RDF
11	Tom Gilb	Design Evaluation: Estimating Multiple Critical Performance and Cost Impacts of Designs.	SAFECOMP	2005	DBLP DOI BibTeX RDF
11	Hyoung-iel Park, Sungwon Kang, Yoonsuk Choi, Danhyung Lee	Developing Object Oriented Designs from Component and Connector Architectures.	APSEC	2005	DBLP DOI BibTeX RDF
11	Ho Fai Ko, Qiang Xu 0001, Nicola Nicolici	Register-transfer level functional scan for hierarchical designs.	ASP-DAC	2005	DBLP DOI BibTeX RDF
11	Subramanian K. Iyer, Jawahar Jain, Debashis Sahoo, Takeshi Shimizu	Verification of Industrial Designs Using A Computing Grid With More than 100 Nodes.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
11	Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki, Shinji Kimura	Low Power Test Compression Technique for Designs with Multiple Scan Chain.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
11	Ali Habibi, Sofiène Tahar	An Approach for the Verification of SystemC Designs Using AsmL.	ATVA	2005	DBLP DOI BibTeX RDF
11	Nick Savoiu	MTP: A Petri Net-Based Framework for the Analysis and Transformation of SystemC Designs.	SCOPES	2005	DBLP DOI BibTeX RDF
11	Tung-Chieh Chen, Tien-Chang Hsu, Zhe-Wei Jiang, Yao-Wen Chang	NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs.	ISPD	2005	DBLP DOI BibTeX RDF	mincut, ratio cut, placement
11	Shao-Ming Yu, Yiming Li 0005	A Pattern-Based Domain Partition Approach to Parallel Optical Proximity Correction in VLSI Designs.	IPDPS	2005	DBLP DOI BibTeX RDF
11	James E. Stine, Johannes Grad, Ivan D. Castellanos, Jeff M. Blank, Vibhuti B. Dave, Mallika Prakash, Nick Iliev, Nathan Jachimiec	A Framework for High-Level Synthesis of System-on-Chip Designs.	MSE	2005	DBLP DOI BibTeX RDF
11	Olivera Marjanovic	Modeling of Process-Oriented Learning Designs.	ICALT	2005	DBLP DOI BibTeX RDF
11	Luke Demoracski, Dimiter R. Avresky	An Approach for Functional Decomposition Applied to State-Based Designs.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
11	Benjamin P.-C. Yen, Paul Jen-Hwa Hu, May D. Wang	Towards Effective Web Site Designs: A Framework for Modeling, Design Evaluation and Enhancement.	EEE	2005	DBLP DOI BibTeX RDF
11	José Miguel Valiente, Francisco Albert, José María Gomis	A Computational Model for Pattern and Tile Designs Classification Using Plane Symmetry Groups.	CIARP	2005	DBLP DOI BibTeX RDF
11	Daniel Große, Rolf Drechsler	CheckSyC: an efficient property checker for RTL SystemC designs.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
11	Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou	Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designs.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
11	Abhishek Mitra, Marcello Lajolo, Kanishka Lahiri	SOFTENIT: a methodology for boosting the software content of system-on-chip designs.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	embedded systems, partitioning, RTOS, HW/SW codesign
11	Zhuo Zhang 0008, Sudhakar M. Reddy, Irith Pomeranz	On Generating Pseudo-Functional Delay Fault Tests for Scan Designs.	DFT	2005	DBLP DOI BibTeX RDF
11	John R. Koza, Sameer H. Al-Sakran, Lee W. Jones	Cross-Domain Features of Runs of Genetic Programming Used to Evolve Designs for Analog Circuits, Optical Lens Systems, Controllers, Antennas, Mechanical Systems, and Quantum Computing Circuits.	Evolvable Hardware	2005	DBLP DOI BibTeX RDF
11	Suvodeep Gupta, Srinivas Katkoori, Hariharan Sankaran	Floorplan-Based Crosstalk Estimation for Macrocell-Based Designs.	VLSI Design	2005	DBLP DOI BibTeX RDF
11	Mei Yang, Yingtao Jiang, Tao Li, Yulu Yang	Fault-Tolerant Routing Schemes in RDT(2, 2, 1)/a-Based Interconnection Network for Networks-on-Chip Designs.	ISPAN	2005	DBLP DOI BibTeX RDF
11	Russell Klein, Tomasz Piekarz	Accelerating Functional Simulation for Processor Based Designs, invited.	IWSOC	2005	DBLP DOI BibTeX RDF
11	Marvin Tom, Guy G. Lemieux	Logic block clustering of large designs for channel-width constrained FPGAs.	DAC	2005	DBLP DOI BibTeX RDF	channel width constraints, clustering, field-programmable gate arrays (FPGA), packing
11	Defeng Huang, Khaled Ben Letaief, Jianhua Lu	A receive space diversity architecture for OFDM systems using orthogonal designs.	IEEE Trans. Wirel. Commun.	2004	DBLP DOI BibTeX RDF
11	Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand	Interpretation of rent's rule for ultralarge-scale integrated circuit designs, with an application to wirelength distribution models.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
11	Joonseok Park, Pedro C. Diniz, K. R. Shesha Shayee	Performance and Area Modeling of Complete FPGA Designs in the Presence of Loop Transformations.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Performance analysis and modeling, loop transformations and high-level synthesis, Field-Programmable-Gate-Arrays (FPGAs), configurable computing