Search results for "DFT"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Toshinori Sato	Exploiting Instruction Redundancy for Transient Fault Tolerance.	DFT	2003	DBLP DOI BibTeX RDF
1	Dan Zhao 0001, Shambhu J. Upadhyaya, Martin Margala	Control Constrained Resource Partitioning for Complex SoCs.	DFT	2003	DBLP DOI BibTeX RDF
1	Hamidreza Hashempour, Fabrizio Lombardi	ATE-Amenable Test Data Compression with No Cyclic Scan.	DFT	2003	DBLP DOI BibTeX RDF
1	Xiaopeng Wang, Marco Ottavi, Fabrizio Lombardi	Yield Analysis of Compiler-Based Arrays of Embedded SRAMs.	DFT	2003	DBLP DOI BibTeX RDF
1	Haruhiko Kaneko, Eiji Fujiwara	Array Codes Correcting a Cluster of Unidirectional Errors for Two-Dimensional Matrix Symbols.	DFT	2003	DBLP DOI BibTeX RDF
1	Noh-Jin Park, Byoungjae Jin, K. M. George, Nohpill Park, Minsu Choi	Regressive Testing for System-on-Chip with Unknown-Good-Yield.	DFT	2003	DBLP DOI BibTeX RDF
1	Olga Goloubeva, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante	Soft-Error Detection Using Control Flow Assertions.	DFT	2003	DBLP DOI BibTeX RDF
1	Yukiya Miura, Daisuke Kato	Analysis and Testing of Analog and Mixed-Signal Circuits by an Operation-Region Model: A Case Study of Application and Implementation.	DFT	2003	DBLP DOI BibTeX RDF
1	Xiaoling Sun, Bruce F. Cockburn, Duncan G. Elliott	An Efficient Functional Test for the Massively-Parallel C ?RAM Logic-Enhanced Memory Architecture.	DFT	2003	DBLP DOI BibTeX RDF
1	Sagar S. Sabade, D. M. H. Walker	CROWNE: Current Ratio Outliers with Neighbor Estimator.	DFT	2003	DBLP DOI BibTeX RDF
1	Bogdan Nicolescu, Yvon Savaria, Raoul Velazco	SIED: Software Implemented Error Detection.	DFT	2003	DBLP DOI BibTeX RDF
1	Shervin Sharifi, Mohammad Hosseinabady, Pedram A. Riahi, Zainalabedin Navabi	Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture.	DFT	2003	DBLP DOI BibTeX RDF
1	Charles F. Hawkins, Ali Keshavarzi, Jaume Segura 0001	A View from the Bottom: Nanometer Technology AC Parametric Failures -- Why, Where, and How to Detect.	DFT	2003	DBLP DOI BibTeX RDF
1	Yung-Yuan Chen, Shi-Jinn Horng, Hung-Chuan Lai	An Integrated Fault-Tolerant Design Framework for VLIW Processors.	DFT	2003	DBLP DOI BibTeX RDF
1	Sobeeh Almukhaizim, Yiorgos Makris	Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code.	DFT	2003	DBLP DOI BibTeX RDF
1	Bogdan Nicolescu, Paul Peronnard, Raoul Velazco, Yvon Savaria	Efficiency of Transient Bit-Flips Detection by Software Means: A Complete Study.	DFT	2003	DBLP DOI BibTeX RDF
1	Kranthi K. Pinjala, Bruce C. Kim	An Approach for Selection of Test Points for Analog Fault Diagnosis.	DFT	2003	DBLP DOI BibTeX RDF
1	Vinu Vijay Kumar, John C. Lach	Heterogeneous Redundancy for Fault and Defect Tolerance with Complexity Independent Area Overhead.	DFT	2003	DBLP DOI BibTeX RDF
1	Hamid R. Zarandi, Seyed Ghassem Miremadi, Ali Reza Ejlali	Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models.	DFT	2003	DBLP DOI BibTeX RDF
1	Xiao Liu 0010, Michael S. Hsiao	Constrained ATPG for Broadside Transition Testing.	DFT	2003	DBLP DOI BibTeX RDF
1	Tianxu Zhao, Xuchao Duan, Yue Hao, Peijun Ma	Reliability Estimation Model of ICs Interconnect Based on Uniform Distribution of Defects on a Chip.	DFT	2003	DBLP DOI BibTeX RDF	interconnection lifetime, electromigration effect, defect
1	Yassine Hariri, Claude Thibeault	3DSDM: A 3 Data-Source Diagnostic Method.	DFT	2003	DBLP DOI BibTeX RDF
1	Sandeep Bhatia	Test Compaction by Using Linear-Matrix Driven Scan Chains.	DFT	2003	DBLP DOI BibTeX RDF
1	C. V. Krishna, Nur A. Touba	Hybrid BIST Using an Incrementally Guided LFSR.	DFT	2003	DBLP DOI BibTeX RDF
1	Fabrizio Lombardi, Nohpill Park	Testing Layered Interconnection Networks.	DFT	2002	DBLP DOI BibTeX RDF	Fault Tolerance, Interconnection Networks, Fault Detection, Network Flow, Switch
1	Cecilia Metra, Stefano Di Francescantonio, Giuseppe Marrale	On-Line Testing of Transient Faults Affecting Functional Blocks of FCMOS, Domino and FPGA-Implemented Self-Checking Circuits.	DFT	2002	DBLP DOI BibTeX RDF
1	Viera Stopjaková, Daniel Micusík, Lubica Benusková, Martin Margala	Neural Networks-Based Parametric Testing of Analog IC.	DFT	2002	DBLP DOI BibTeX RDF
1	Ozgur Sinanoglu, Alex Orailoglu	Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation.	DFT	2002	DBLP DOI BibTeX RDF
1	Stanislaw J. Piestrak	Feasibility Study of Designing TSC Sequential Circuits with 100% Fault Coverage.	DFT	2002	DBLP DOI BibTeX RDF
1	Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McCluskey	Testing Digital Circuits with Constraints.	DFT	2002	DBLP DOI BibTeX RDF
1	Fabio Salice, Mariagiovanna Sami, Renato Stefanelli	Fault-Tolerant CAM Architectures: A Design Framework.	DFT	2002	DBLP DOI BibTeX RDF
1	Hamidreza Hashempour, Fred J. Meyer, Fabrizio Lombardi	Test Time Reduction in a Manufacturing Environment by Combining BIST and ATE.	DFT	2002	DBLP DOI BibTeX RDF
1	A. Castelnuovo, Alessandro Fin, Franco Fummi, F. Sforza	Emulation-Based Design Errors Identification.	DFT	2002	DBLP DOI BibTeX RDF
1	Witold A. Pleskacz, Tomasz Borejko, Wieslaw Kuzmicz	CMOS Standard Cells Characterization for IDDQ Testing.	DFT	2002	DBLP DOI BibTeX RDF
1	Kedarnath J. Balakrishnan, Nur A. Touba	Matrix-Based Test Vector Decompression Using an Embedded Processor.	DFT	2002	DBLP DOI BibTeX RDF
1	Jimson Mathew, Elena Dubrova	Self-Checking 1-out-of-n CMOS Current-Mode Checker.	DFT	2002	DBLP DOI BibTeX RDF
1	Jennifer Dworak, James Wingfield, Brad Cobb, Sooryong Lee, Li-C. Wang, M. Ray Mercer	Fortuitous Detection and its Impact on Test Set Sizes Using Stuck-at and Transition Faults.	DFT	2002	DBLP DOI BibTeX RDF
1	Pedram Khademsameni, Marek Syrzycki	Manufacturability Analysis of Analog CMOS ICs through Examination of Multiple Layout Solutions.	DFT	2002	DBLP DOI BibTeX RDF
1	Francisco Rodríguez 0003, José Carlos Campelo, Juan José Serrano	A Memory Overhead valuation of the Interleaved Signature Instruction Stream.	DFT	2002	DBLP DOI BibTeX RDF
1	Horng-Bin Wang, Shi-Yu Huang, Jing-Reng Huang	Gate-Delay Fault Diagnosis Using the Inject-and-Evaluate Paradigm.	DFT	2002	DBLP DOI BibTeX RDF
1	Farzin Karimi, Waleed Meleis, Zainalabedin Navabi, Fabrizio Lombardi	Data Compression for System-on-Chip Testing Using ATE.	DFT	2002	DBLP DOI BibTeX RDF
1	Ching-Hwa Cheng	Adaptable Voltage Scan Testing of Charge-Sharing Faults for Domino Circuits.	DFT	2002	DBLP DOI BibTeX RDF
1	Thomas Verdel, Yiorgos Makris	Duplication-Based Concurrent Error Detection in Asynchronous Circuits: Shortcomings and Remedies.	DFT	2002	DBLP DOI BibTeX RDF
1	Fernando M. Gonçalves, Marcelino B. Santos, Isabel C. Teixeira, João Paulo Teixeira 0001	Self-Checking and Fault Tolerance Quality Assessment Using Fault Sampling.	DFT	2002	DBLP DOI BibTeX RDF
1	Sagar S. Sabade, D. M. H. Walker	Neighbor Current Ratio (NCR): A New Metric for IDDQ Data Analysis.	DFT	2002	DBLP DOI BibTeX RDF
1	Raoul Velazco, A. Corominas, Pablo A. Ferreyra	Injecting Bit Flip Faults by Means of a Purely Software Approach: A Case Studied.	DFT	2002	DBLP DOI BibTeX RDF
1	Sara Blanc, Joaquin Gracia, Pedro J. Gil	A Fault Hypothesis Study on the TTP/C Using VHDL-Based and Pin-Level Fault Injection Techniques.	DFT	2002	DBLP DOI BibTeX RDF
1	Hamidreza Hashempour, Yong-Bin Kim, Nohpill Park	A Test-Vector Generation Methodology for Crosstalk Noise Faults.	DFT	2002	DBLP DOI BibTeX RDF
1	Arman Vassighi, Oleg Semenov, Manoj Sachdev, Ali Keshavarzi	Effect of Static Power Dissipation in Burn-In Environment on Yield of VLSI.	DFT	2002	DBLP DOI BibTeX RDF
1	Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante	A New Functional Fault Model for FPGA Application-Oriented Testing.	DFT	2002	DBLP DOI BibTeX RDF
1	Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici	Scan Architecture for Shift and Capture Cycle Power Reduction.	DFT	2002	DBLP DOI BibTeX RDF
1	Bogdan M. Maziarz, Vijay K. Jain	Yield Estimates for the TESH Multicomputer Network.	DFT	2002	DBLP DOI BibTeX RDF
1	Dan Alexandrescu, Lorena Anghel, Michael Nicolaidis	New Methods for Evaluating the Impact of Single Event Transients in VDSM ICs.	DFT	2002	DBLP DOI BibTeX RDF
1	Yuichi Hamamura, Kazunori Nemoto, Takaaki Kumazawa, Hisafumi Iwata, Kousuke Okuyama, Shiro Kamohara, Aritoshi Sugimoto	Repair Yield Simulation with Iterative Critical Area Analysis for Different Types of Failure.	DFT	2002	DBLP DOI BibTeX RDF
1	Lörinc Antoni, Régis Leveugle, Béla Fehér	Using Run-Time Reconfiguration for Fault Injection in Hardware Prototypes.	DFT	2002	DBLP DOI BibTeX RDF
1	Tian Xia, Jien-Chung Lo	On-Chip Jitter Measurement for Phase Locked Loops.	DFT	2002	DBLP DOI BibTeX RDF
1		17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 6-8 November 2002, Vancouver, BC, Canada, Proceedings	DFT	2002	DBLP BibTeX RDF
1	Kartik Mohanram, Nur A. Touba	Input Ordering in Concurrent Checkers to Reduce Power Consumption.	DFT	2002	DBLP DOI BibTeX RDF
1	Pierluigi Civera, Luca Macchiarulo, Massimo Violante	A Simplified Gate-Level Fault Model for Crosstalk Effects Analysis.	DFT	2002	DBLP DOI BibTeX RDF
1	Xiaoling Sun, A. Alimohammad, Pieter M. Trouborst	Modeling of FPGA Local/Global Interconnect Resources and Derivation of Minimal Test Configurations.	DFT	2002	DBLP DOI BibTeX RDF	global/local interconnect testing, modeling, graph coloring, greedy algorithms, FPGA testing
1	Guido Bertoni, Luca Breveglieri, Israel Koren, Paolo Maistri, Vincenzo Piuri	A Parity Code Based Fault Detection for an Implementation of the Advanced Encryption Standard.	DFT	2002	DBLP DOI BibTeX RDF
1	Daniel Marienfeld, Vitalij Ocheretnij, Michael Gössel, Egor S. Sogomonyan	Partially Duplicated Code-Disjoint Carry-Skip Adder.	DFT	2002	DBLP DOI BibTeX RDF
1	Y. Chang, Minsu Choi, Nohpill Park, Fabrizio Lombardi	Repairability Evaluation of Embedded Multiple Region DRAMs.	DFT	2002	DBLP DOI BibTeX RDF
1	Bing Qiu 0003, Yvon Savaria, Meng Lu, Chunyan Wang 0004, Claude Thibeault	Yield Modeling of a WSI Telecom Router Architecture.	DFT	2002	DBLP DOI BibTeX RDF
1	Dan Zhao 0001, Shambhu J. Upadhyaya	Adaptive Test Scheduling in SoC's by Dynamic Partitioning.	DFT	2002	DBLP DOI BibTeX RDF
1	Susumu Horiguchi, Yasuyuki Miura	Performance of Deadlock-Free Adaptive Routing for Hierarchical Interconnection Network TESH.	DFT	2002	DBLP DOI BibTeX RDF
1	Matteo Sonza Reorda, Massimo Violante	Fault List Compaction through Static Timing Analysis for Efficient Fault Injection Experiments.	DFT	2002	DBLP DOI BibTeX RDF
1	Ranganathan Sankaralingam, Nur A. Touba	Inserting Test Points to Control Peak Power During Scan Testing.	DFT	2002	DBLP DOI BibTeX RDF
1	Cristiana Bolchini, Fabio Salice, Donatella Sciuto	Designing Self-Checking FPGAs through Error Detection Codes.	DFT	2002	DBLP DOI BibTeX RDF
1	Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri	Balanced Redundancy Utilization in Embedded Memory Cores for Dependable Systems.	DFT	2002	DBLP DOI BibTeX RDF
1	Pradeep Nagaraj, Shambhu Upadhaya, Kamran Zarrineh, R. Dean Adams	Defect Analysis and a New Fault Model for Multi-port SRAMs.	DFT	2001	DBLP DOI BibTeX RDF	dual-port, SDDRF, electrical fault model, SRAM, defect analysis, multi-port
1	Wei-Je Huang, Subhasish Mitra, Edward J. McCluskey	Fast Run-Time Fault Location in Dependable FPGA-Based Applications.	DFT	2001	DBLP DOI BibTeX RDF	Run-time fault location, Field-Programmable Gate Array (FPGA), concurrent error detection, on-line testing
1	Joaquin Gracia, Juan Carlos Baraza, Daniel Gil, Pedro J. Gil	Comparison and Application of Different VHDL-Based Fault Injection Techniques.	DFT	2001	DBLP DOI BibTeX RDF	VHDL-Based Fault Injection, Fault Tolerant Validation
1	Xiangdong Xuan, Abhijit Chatterjee	Sensitivity and Reliability Evaluation for Mixed-Signal ICs under Electromigration and Hot-Carrier Effects.	DFT	2001	DBLP DOI BibTeX RDF	hot-carrier, hierarchical analysis, hot-spot, performance degradation, Electromigration
1	Régis Leveugle	A Low-Cost Hardware Approach to Dependability Validation of Ips.	DFT	2001	DBLP DOI BibTeX RDF	VHDL, emulation, fault injection, dependability analysis
1	S. K. Tewksbury	Challenges Facing Practical DFT for MEMS.	DFT	2001	DBLP DOI BibTeX RDF	Microelectromechanical systems, microsystems technologies, fault tolerance, defect tolerance
1	Mykola Blyzniuk, Irena Kazymyra	Development of the Special Software Tools for the Defect/Fault Analysis in the Complex Gates from Standard Cell Library.	DFT	2001	DBLP DOI BibTeX RDF	Test Vector Components, Software Tool, VLSI Circuit, Spot Defect, Fault Identification, Complex Gate
1	John Marty Emmert, Jason A. Cheatham	On-Line Incremental Routing for Interconnect Fault Tolerance in FPGAs Minus the Router .	DFT	2001	DBLP DOI BibTeX RDF
1	Hiroyuki Yotsuyanagi, Masaki Hashizume, Taisuke Iwakiri, Masahiro Ichimiya, Takeomi Tamesada	Test Pattern for Supply Current Test of Open Defects by Applying Time-Variable Electric Field.	DFT	2001	DBLP DOI BibTeX RDF	supply current test, time-variable electric field, test pattern generation, CMOS IC, open defects
1	Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell	Analog BIST Generator for ADC Testing.	DFT	2001	DBLP DOI BibTeX RDF
1	Cristiana Bolchini, Fabio Salice	A Software Methodology for Detecting Hardware Faults in VLIW Data Paths.	DFT	2001	DBLP DOI BibTeX RDF	Software code scheduling, VLIW processors, Hardware fault detection
1	Cecilia Metra, Stefano Di Francescantonio, Bruno Riccò, T. M. Mak	Evaluation of Clock Distribution Networks' Most Likely Faults and Produced Effects.	DFT	2001	DBLP DOI BibTeX RDF	clock faults, testing, microprocessor, Clock distribution network
1	Nobuo Tsuda	ABL-Tree: A Constant Diameter Interconnection Network for Reconfigurable Processor Arrays Capable of Distributed Communication .	DFT	2001	DBLP DOI BibTeX RDF	generalized ABL, fault tolerance, interconnection network, reconfiguration, tree, mesh, ring, PC cluster, parallel and distributed processing
1	Thomas S. Barnett, Adit D. Singh, Victor P. Nelson	Yield-Reliability Modeling for Fault Tolerant Integrated Circuits.	DFT	2001	DBLP DOI BibTeX RDF	infant mortality, negative binomial distribution, clustering, reliability, redundancy, yield, defects, defect tolerance, burn-in
1	Parag K. Lala, Alvernon Walker	On-Line Error Detectable Carry-Free Adder Design.	DFT	2001	DBLP DOI BibTeX RDF	carry-free adder, signed binary digits, 1-out-of-3 code, on-line error detection
1	Monica Alderighi, Fabio Casini, Sergio D'Angelo, Davide Salvi, Giacomo R. Sechi	A Fault-Tolerance Strategy for an FPGA-Based Multi-stage Interconnection Network in a Multi-sensor System for Space Application.	DFT	2001	DBLP DOI BibTeX RDF
1	Xiaowei Li 0001, Huawei Li 0001, Yinghua Min	Reducing Power Dissipation during At-Speed Test Application.	DFT	2001	DBLP DOI BibTeX RDF	Test-pair Ordering, Power Dissipation, At-speed Test
1	Shugang Wei, Kensuke Shimizu	Error Detection of Arithmetic Circuits Using a Residue Checker with Signed-Digit Number System.	DFT	2001	DBLP DOI BibTeX RDF	residue addition, residue multiplication, signed-digit(SD) number representation, SD adder, error detection, residue number system(RNS)
1	Yves Audet, Glenn H. Chapman	Design of a Self-Correcting Active Pixel Sensor.	DFT	2001	DBLP DOI BibTeX RDF	defect tolerance, digital cameras, Active Pixel Sensors
1	Eleftherios Kolonis, Michael Nicolaidis	Fail-Safe Synchronization Circuit for Duplicated Systems.	DFT	2001	DBLP DOI BibTeX RDF	fail-safe systems, fail-safe synchronization, duplicated systems, actuator control
1	Shu-Yi Yu, Edward J. McCluskey	Permanent Fault Repair for FPGAs with Limited Redundant Area.	DFT	2001	DBLP DOI BibTeX RDF	Permanent Fault Repair, Adaptive Computing System, Reconfigurable Computing System, Fault Tolerance, FPGA, Recovery
1	Marco Ottavi, Gian Carlo Cardarilli, D. Cellitti, Salvatore Pontarelli, Marco Re, Adelio Salsano	Design of a Totally Self Checking Signature Analysis Checker for Finite State Machines.	DFT	2001	DBLP DOI BibTeX RDF	SSMM, fault tolerance, finite state machine, VHDL, signature analysis, self checking
1	Hans A. R. Manhaeve, Stefaan Kerckenaere	An On-Chip Detection Circuit for the Verification of IC Supply Connections.	DFT	2001	DBLP DOI BibTeX RDF	IC connections, connection verification, supply current measurements, on-chip monitor, reliability, DFT, CMOS, Scan, Boundary Scan, IP core, Current monitor
1	Kazuteru Namba, Eiji Fujiwara	Unequal Error Protection Codes with Two-Level Burst and Bit Error Correcting Capabilities.	DFT	2001	DBLP DOI BibTeX RDF	error correcting-detecting code, unequal error protection code, burst error
1	Jayabrata Ghosh-Dastidar, Nur A. Touba	Improving Diagnostic Resolution of Delay Faults in FPGAs by Exploiting Reconfigurability.	DFT	2001	DBLP DOI BibTeX RDF
1		16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings	DFT	2001	DBLP BibTeX RDF
1	Andreas Steininger, Christoph Scherrer	How to Tune the MTTF of a Fail-Silent System.	DFT	2001	DBLP DOI BibTeX RDF	Fail-Silent Embedded System, Markov Modeling, Sensitivity Analysis, Mean Time To Failure
1	Paul Lee, Alfred Chen, Dilip Mathew	A Speed-Dependent Approach for Delta IDDQ Implementation.	DFT	2001	DBLP DOI BibTeX RDF	Self-scaling IDDQ, Speed Performance Index, characterization, Delta IDDQ
1	Amir Kazéminéjad, Eric Belhaire	Fast, Minimal Decoding Complexity, System Level, Binary Systematic (41, 32) Single-Error-Correcting Codes for On-Chip DRAM Applications.	DFT	2001	DBLP DOI BibTeX RDF	Extended Hamming codes, Error correcting codes, Hamming codes
1	Stanislaw J. Piestrak, Abbas Dandache, Fabrice Monteiro	Design of Fault-Secure Encoders for a Class of Systematic Error Correcting Codes.	DFT	2001	DBLP DOI BibTeX RDF

Publications at "DFT"( http://dblp.L3S.de/Venues/DFT )