Search results for "FPGA"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
26	Ian Kuon, Navid Azizi, Ahmad Darabiha, Aaron Egier, Paul Chow	FPGA-based supercomputing: an implementation for molecular dynamics.	FPGA	2004	DBLP DOI BibTeX RDF
26	Sanat Kamal Bahl, Jim Plusquellic	FPGA implementation of a fast Hadamard transformer for WCDMA.	FPGA	2003	DBLP DOI BibTeX RDF
26	Hossam A. ElGindy, George Ferizis	On hiding latency in reconfigurable systems: the case of merge-sort for an FPGA-based system.	FPGA	2003	DBLP DOI BibTeX RDF
26	Gang Chen 0020, Jason Cong	Simultaneous logic decomposition with technology mapping in FPGA designs.	FPGA	2001	DBLP DOI BibTeX RDF
26	Andrés D. García, Jean-Luc Danger, Wayne P. Burleson	Low power digital design in FPGAs (poster abstract): a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption.	FPGA	2000	DBLP DOI BibTeX RDF
26	F. S. Ogrenci, Aggelos K. Katsaggelos, Majid Sarrafzadeh	FPGA implementation and analysis of image restoration.	FPGA	2000	DBLP DOI BibTeX RDF
26	William Fornaciari, Vincenzo Piuri, Luigi Ripamonti	Virtualization of FPGA via segmentation (poster abstract).	FPGA	2000	DBLP DOI BibTeX RDF
26	Barry Shackleford, Etsuko Okushi, Mitsuhiro Yasuda, Hisao Koizumi, Katsuhiko Seo, Takashi Iwamoto, Hiroto Yasuura	An FPGA-based genetic algorithm machine (poster abstract).	FPGA	2000	DBLP DOI BibTeX RDF
26	Ian Brynjolfson, Zeljko Zilic	FPGA clock management for low power applications (poster abstract).	FPGA	2000	DBLP DOI BibTeX RDF
26	V. S. Balakrishnan, Hardy J. Pottinger, Fikret Erçal, Mukesh Agarwal	Design and implementation of an FPGA based processor for compressed images (poster abstract).	FPGA	2000	DBLP DOI BibTeX RDF
26	Kun-Ming Ho, Allen C.-H. Wu	Module Generation of High Performance FPGA-Based Multipliers.	FPGA	1999	DBLP DOI BibTeX RDF
26	Enrica Filippi, Archille Montanaro, Maurizio Paolini, Maura Turolla	FPGA Design Experiences Using the CSELT VIP (TM) Library.	FPGA	1999	DBLP DOI BibTeX RDF
26	John McCluskey	Practical Applications of Recursive VHDL Components in FPGA Synthesis.	FPGA	1999	DBLP DOI BibTeX RDF
26	Jason Cong, Chang Wu, Yuzheng Ding	Cut Ranking and Pruning: Enabling a General and Efficient FPGA Mapping Solution.	FPGA	1999	DBLP DOI BibTeX RDF
26	Emeka Mosanya, Eduardo Sanchez	A FPGA-Based Hardware Implementation of Generalized Profile Search Using Online Arithmetic.	FPGA	1999	DBLP DOI BibTeX RDF
26	Lirida A. B. Naviner, Jean-Luc Danger, C. Laurent	High-Performance Low-Cost Implementation of Two-Dimensional DCT Processor nn FPGA.	FPGA	1999	DBLP DOI BibTeX RDF
26	Karlheinz Weiß, Thorsten Steckstor, Gernot Koch, Wolfgang Rosenstiel	Exploiting FPGA-Features During the Emulation of a Fast Reactive Embedded System.	FPGA	1999	DBLP DOI BibTeX RDF
26	Zhiyuan Li 0008, Scott Hauck	Don't Care Discovery for FPGA Configuration Compression.	FPGA	1999	DBLP DOI BibTeX RDF
26	Takahiro Murooka, Atsushi Takahara, Toshiaki Miyazaki	Why a CAD-Verified FPGA Makes Routing so Simple and Fast! A Result of Co-Designing FPGAs and CAD Algorithms.	FPGA	1999	DBLP DOI BibTeX RDF
26	Guang-Ming Wu, Michael Shyu, Yao-Wen Chang	Universal Switch Blocks for Three-Dimensional FPGA Design.	FPGA	1999	DBLP DOI BibTeX RDF
26	Alexander Marquardt, Vaughn Betz, Jonathan Rose	Using Cluster-Based Logic Blocks and Timing-Driven Packing to Improve FPGA Speed and Density.	FPGA	1999	DBLP DOI BibTeX RDF
26	Jose Luis Nunez, Claudia Feregrino, Stephen Bateman, Simon R. Jones	The X-MatchLITE FPGA-Based Data Compressor.	FPGA	1999	DBLP DOI BibTeX RDF
26	Chris Dick	High-Performance 2-D FPGA DCTs Using Polynomial Transforms.	FPGA	1999	DBLP DOI BibTeX RDF
26	John C. Lach, William H. Mangione-Smith, Miodrag Potkonjak	Efficient Support of Hardware Debugging Through FPGA Physical Design Partitioning.	FPGA	1999	DBLP DOI BibTeX RDF
26	Valery Sklyarov, José A. Fonseca, Ricardo Sal Monteiro, Arnaldo S. R. Oliveira, Andreia Melo, Nuno Lau, Konstantin Kondratjuk, Iouliia Skliarova, Paulo A. C. S. Neves, António de Brito Ferrari	FPGA-Targeted Development System for Embedded Applications.	FPGA	1999	DBLP DOI BibTeX RDF
26	Klaus Kornmesser, Torsten Kuberka, Andreas Kugel, Reinhard Männer, Stephan Rühl, M. Sessler, Holger Singpiel	ATLANTIS - A Hybrid Approach Combining the Power of FPGA and RISC Processors Based on CompactPCI.	FPGA	1999	DBLP DOI BibTeX RDF
26	Vaughn Betz, Jonathan Rose	FPGA Routing Architecture: Segmentation and Buffering to Optimize Speed and Density.	FPGA	1999	DBLP DOI BibTeX RDF
26	Sinan Kaptanoglu, Greg Bakker, Arun Kundu, Ivan Corneillet, Ben Ting	A New High Density and Very Low Cost Reprogrammable FPGA Architecture.	FPGA	1999	DBLP DOI BibTeX RDF
26	Vinoo Srinivasan, Ranga Vemuri	Throughput Optimization with Design Space Exploration During Partitioning for Multi-FPGA Architectures.	FPGA	1999	DBLP DOI BibTeX RDF
26	A. Lecerf, François Vachon, D. Ouellet, Miguel O. Arias-Estrada	FPGA Based Computer Vision Camera.	FPGA	1999	DBLP DOI BibTeX RDF
26	Om Agrawal, Herman Chang, Brad Sharpe-Geisler, Nick Schmitz, Bai Nguyen 0002, Jack Wong, Giap Tran, Fabiano Fontana, Bill Harding	An Innovative, Segmented High Performance FPGA Family with Variable-Grain-Architecture and Wide-Gating Functions.	FPGA	1999	DBLP DOI BibTeX RDF
26	Ray Andraka	A Survey of CORDIC Algorithms for FPGA Based Computers.	FPGA	1998	DBLP DOI BibTeX RDF	polar conversion, vector magnitude, CORDIC, sine, cosine
26	Franco Fummi, A. Marshall, Laura Pozzi, Mariagiovanna Sami	Minimizing the Application Time for Manufacturer Testing of FPGA (Abstract).	FPGA	1998	DBLP DOI BibTeX RDF	VERIFY
26	Tsuyoshi Isshiki, Takenobu Shimizugashira, Akihisa Ohta, Imanuddin Amril, Hiroaki Kunieda	A New FPGA Architecture for High-Performance bit-Serial Pipeline Datapath (Abstract).	FPGA	1998	DBLP DOI BibTeX RDF
26	Jesus Crespo, Juan Carlos Diaz, Pimitivo Matas	FPGA Implementation of an ATM Traffic Shaper: ATS (Abstract).	FPGA	1998	DBLP DOI BibTeX RDF
26	Wai-Kei Mak, D. F. Wong 0001	Performance-Driven Board-Level Routing for FPGA-Based Logic Emulation (Abstract).	FPGA	1998	DBLP DOI BibTeX RDF
26	Oliver Diessel, Hossam A. ElGindy	Partial FPGA Rearrangement by Local Repacking (Abstract).	FPGA	1998	DBLP DOI BibTeX RDF
26	Takenori Kouda, Yahiko Kambayashi	FPGA Circuit Optimization Based on Block Integration (Abstract).	FPGA	1998	DBLP DOI BibTeX RDF
26	Silviu M. S. A. Chiricescu, Mankuan Michael Vai	Design of a Three-Dimensional FPGA for Reconfigurable Computing Machines (Abstract).	FPGA	1998	DBLP DOI BibTeX RDF
26	Paul T. Sasaki	A Fast FPGA (FFPGA) Using Active Interconnect (Abstract).	FPGA	1998	DBLP DOI BibTeX RDF
26	Hanho Lee, Sarvesh Shrivastava, Gerald E. Sobelman	FPGA Logic Block Architecture for Digit-Serial DSP Applications (Abstract).	FPGA	1998	DBLP DOI BibTeX RDF
26	Jo Depreitere, Herwig Van Marck, Jan Van Campenhout	GART: A New, Flexible Placement and Routing Tool for Research on FPGA Architectures (Abstract).	FPGA	1998	DBLP DOI BibTeX RDF
26	Kurt Keutzer	Challenges in CAD for the One Million Gate FPGA.	FPGA	1997	DBLP DOI BibTeX RDF
26	Akihiro Tsutsui, Toshiaki Miyazaki	YARDS: FPGA/MPU Hybrid Architecture for Telecommunication Data Processing.	FPGA	1997	DBLP DOI BibTeX RDF
26	Jason Cong, Yean-Yow Hwang	Partially-Dependent Functional Decomposition with Applications in FPGA Synthesis and Mapping.	FPGA	1997	DBLP DOI BibTeX RDF
26	R. Glenn Wood, Rob A. Rutenbar	FPGA Routing and Routability Estimation via Boolean Satisfiability.	FPGA	1997	DBLP DOI BibTeX RDF
26	Brian Von Herzen	Signal Processing at 250 MHz Using High-Performance FPGA's.	FPGA	1997	DBLP DOI BibTeX RDF
26	Monica Alderighi, E. L. Gummati, Vincenzo Piuri, Giacomo R. Sechi	A FPGA-Based Implementation of a Fault-Tolerant Neural Architecture for Photon Identification.	FPGA	1997	DBLP DOI BibTeX RDF
26	Glenn H. Chapman, Benoit Dufort	Laser Correcting Defects to Create Transparent Routing for Large Area FPGA's.	FPGA	1997	DBLP DOI BibTeX RDF
26	Jianzhong Shi, Dinesh Bhatia	Performance Driven Floorplanning for FPGA Based Designs.	FPGA	1997	DBLP DOI BibTeX RDF
26	Steven Trimberger, Khue Duong, Bob Conn	Architecture Issues and Solutions for a High-Capacity FPGA.	FPGA	1997	DBLP DOI BibTeX RDF
26	Frank Vahid	I/O and Performance Tradeoffs with the FunctionBus During Multi-FPGA Partitioning.	FPGA	1997	DBLP DOI BibTeX RDF
26	Kengo Azegami, Shoichiro Kashiwakura, Koichi Yamashita	Flexible FPGA Architecture Realized of General Purpose SOG.	FPGA	1996	DBLP DOI BibTeX RDF
26	Alireza Kaviani, Stephen Dean Brown	Hybrid FPGA Architecture.	FPGA	1996	DBLP DOI BibTeX RDF
26	Charles E. Stroud, Ping Chen, Srinivasa Konala, Miron Abramovici	Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks.	FPGA	1996	DBLP DOI BibTeX RDF
26	Chris Dick	Computing the Discrete Fourier Transform on FPGA Based Systolic Arrays.	FPGA	1996	DBLP DOI BibTeX RDF
26	Eduardo I. Boemo, Sergio López-Buedo, Juan M. Meneses	The Wave Pipeline Effect on LUT-Based FPGA Architectures.	FPGA	1996	DBLP DOI BibTeX RDF
26	Kalapi Roy-Neogi, Carl Sechen	Multiple FPGA Partitioning with Performance Optimization.	FPGA	1995	DBLP DOI BibTeX RDF
26	Tsuyoshi Isshiki, Wayne Wei-Ming Dai	High-Level Bit-Serial Datapath Synthesis for Multi-FPGA Systems.	FPGA	1995	DBLP DOI BibTeX RDF
26	Jason Cong, Yean-Yow Hwang	Simultaneous Depth and Area Minimization in LUT-based FPGA Mapping.	FPGA	1995	DBLP DOI BibTeX RDF
26	Françis Calmon, M. Fathallah, P. J. Viverge, Christian Gontrand, Jordi Carrabina, P. Foussier	FPGA and Mixed FPGA-DSP Implementations of Electrical Drive Algorithms.	FPL	2002	DBLP DOI BibTeX RDF
26	Ching-Dong Chen, Yuh-Sheng Lee, Allen C.-H. Wu, Youn-Long Lin	TRACER-fpga: a router for RAM-based FPGA's.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
26	Euripides Sotiriades, Apostolos Dollas	A General Reconfigurable Architecture for the BLAST Algorithm.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	FPGA BLAST, reconfigurable BLAST architecture, FPGA BLAST architecture, bioinformatic hardware, bioinformatic FPGA
25	Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry	A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.13 micron, timing-driven algorithm, MTCMOS FPGA, MTCMOS CAD methodology, subthreshold leakage power reduction, nanometer FPGA, circuit timing information, CMOS process
25	René Müller 0001, Jens Teubner	FPGAs: a new point in the database design space.	EDBT	2010	DBLP DOI BibTeX RDF	FPGA, VLSI, hardware acceleration, data processing
25	Roman L. Lysecky, Frank Vahid	Design and implementation of a MicroBlaze-based warp processor.	ACM Trans. Embed. Comput. Syst.	2009	DBLP DOI BibTeX RDF	soft processor cores, FPGA, dynamic optimization, hardware/software partitioning, configurable logic, Warp processors, just-in-time (JIT) compilation
25	Salvatore Pontarelli, Marco Ottavi, Vamsi Vankamamidi, Gian Carlo Cardarilli, Fabrizio Lombardi, Adelio Salsano	Analysis and Evaluations of Reliability of Reconfigurable FPGAs.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	FPGA, Reliability, Fault model, Defect tolerance
25	John D. Davis, Zhangxi Tan, Fang Yu 0002, Lintao Zhang	A practical reconfigurable hardware accelerator for Boolean satisfiability solvers.	DAC	2008	DBLP DOI BibTeX RDF	BCP, FPGA, reconfigurable, SAT solver, co-processor
25	Ehsan Atoofian, Zainalabedin Navabi	A Test Approach for Look-Up Table Based FPGAs.	J. Comput. Sci. Technol.	2006	DBLP DOI BibTeX RDF	LUT testing, TPG with LE, BIST, memory testing, FPGA testing
25	Heinz Mattes, Stéphane Kirmser, Sebastian Sattler	Next Generation ADC Massive Parallel Testing with Real Time Parameter Evaluation.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	delta-sigma-converter, ??-modulation, FPGA, mixed-signal test, ADC test
25	Gang Chen 0020, Jason Cong	Simultaneous placement with clustering and duplication.	ACM Trans. Design Autom. Electr. Syst.	2006	DBLP DOI BibTeX RDF	clustering, FPGA, Placement, legalization, duplication, redundancy removal
25	Manuel Saldaña, Lesley Shannon, Paul Chow	The routability of multiprocessor network topologies in FPGAs.	SLIP	2006	DBLP DOI BibTeX RDF	FPGA, multiprocessor, network-on-chip, topology, interconnect
25	Michael J. Wirthlin	Constant Coefficient Multiplication Using Look-Up Tables.	J. VLSI Signal Process.	2004	DBLP DOI BibTeX RDF	FPGA, DSP, multiplication, look-up table
25	Deming Chen, Jason Cong	Delay optimal low-power circuit clustering for FPGAs with dual supply voltages.	ISLPED	2004	DBLP DOI BibTeX RDF	circuit clustering, low-power FPGA, dual supply voltage
25	Nobuyuki Ohba, Kohji Takano	An SoC design methodology using FPGAs and embedded microprocessors.	DAC	2004	DBLP DOI BibTeX RDF	mixed-level verification, SoC, ASIC, FPGA prototyping
25	David Andrews 0001, Douglas Niehaus	Architectural Frameworks for MPP Systems on a Chip.	IPDPS	2003	DBLP DOI BibTeX RDF	thread programming, FPGA, embedded systems, reconfigurable architectures, computational frameworks
25	Kris Gaj, Tarek A. El-Ghazawi, Nikitas A. Alexandridis, Jacek R. Radzikowski, Mohamed Taher, Frederic Vroman	Effective Utilization and Reconfiguration of Distributed Hardware Resources Using Job Management Systems.	IPDPS	2003	DBLP DOI BibTeX RDF	distributed hardware resources, Job Management Systems, accelerator boards, FPGA, job scheduling, reconfigurable hardware
25	Uwe Meyer-Bäse, Antonio García 0001, Fred J. Taylor	Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	field-programmable logic (FPL), complex programmable logic devices (CPLD), zero-IF filter, field programmable gate array (FPGA), digital signal processing (DSP), residue number system (RNS), channelizer
25	Yohei Hori, Minenobu Seki, Reijer Grimbergen, Tsutomu Maruyama, Tsutomu Hoshino	A Shogi Processor with a Field Programmable Gate Array.	Computers and Games	2000	DBLP DOI BibTeX RDF	FPGA, Reconfigurable hardware, Shogi
25	Yajun Ha, Patrick Schaumont, Marc Engels, Serge Vernalde, Freddy Potargent, Luc Rijnders, Hugo De Man	A Hardware Virtual Machine for the Networked Reconfiguration.	IEEE International Workshop on Rapid System Prototyping	2000	DBLP DOI BibTeX RDF	FPGA, reconfiguration, computer architecture, placement and routing
25	Lijun Gao, Sarvesh Shrivastava, Hanho Lee, Gerald E. Sobelman	A Compact Fast Variable Key Size Elliptic Curve Cryptosystem Coprocessor.	FCCM	1999	DBLP DOI BibTeX RDF	FPGA, Elliptic curve cryptography, Reconfigurable hardware, Scalar multiplication, Galois field, Coprocessor
25	Charles E. Stroud, Srinivasa Konala, Ping Chen, Miron Abramovici	Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!).	VTS	1996	DBLP DOI BibTeX RDF	BIST architecture, programmable logic blocks, field programmable gate arrays, VLSI, logic testing, built-in self test, built-in self-test, integrated circuit testing, automatic testing, FPGA testing, field programmable gate array testing
25	Suthikshn Kumar, Kevin E. Forward, Marimuthu Palaniswami	A fast-multiplier generator for FPGAs.	VLSI Design	1995	DBLP DOI BibTeX RDF	fast-multiplier generator, variable word length multipliers, Booth encoded optimized Wallace tree architecture, field programmable gate arrays, FPGAs, parallel architectures, artificial neural networks, multiplying circuits, FPGA architecture, neural chips
25	Mark Hammerquist, Roman L. Lysecky	Design space exploration for application specific FPGAS in system-on-a-chip designs.	SoCC	2008	DBLP DOI BibTeX RDF
25	Jason Cong, Kirill Minkovich	Optimality Study of Logic Synthesis for LUT-Based FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
25	Xuejun Liang, Jack S. N. Jean	Mapping of generalized template matching onto reconfigurable computers.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
25	Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers	A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study.	Embedded Processor Design Challenges	2002	DBLP DOI BibTeX RDF
25	Moritoshi Yasunaga, Ikuo Yoshihara, Jung Hwan Kim	A High Speed and High Fault Tolerant Reconfigurable Reasoning System: Toward a Wafer Scale Reconfigurable Reasoning LSI.	DFT	2000	DBLP DOI BibTeX RDF
25	Jonathan Babb, Russell Tessier, Matthew Dahl, Silvina Hanono, David M. Hoki, Anant Agarwal	Logic emulation with virtual wires.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
24	Dimitris Theodoropoulos, Georgi Kuzmanov, Georgi Gaydadjiev	A 3d-audio reconfigurable processor.	FPGA	2010	DBLP DOI BibTeX RDF	reconfigurable computing, communication systems, beamforming, 3d-audio, wave field synthesis
24	Zefu Dai, Nick Ni, Jianwen Zhu	A 1 cycle-per-byte XML parsing accelerator.	FPGA	2010	DBLP DOI BibTeX RDF	bart, schema validation, string comparison, xml parsing, ethernet, bloom filter, dom, tree construction
24	Zhimin Chen 0002, Richard Neil Pittman, Alessandro Forin	Combining multicore and reconfigurable instruction set extensions.	FPGA	2010	DBLP DOI BibTeX RDF	extensible microprocessors, reconfigurable instruction set extensions, embedded, multi-core
24	Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton	The impact of interconnect architecture on via-programmed structured ASICs (VPSAs).	FPGA	2010	DBLP DOI BibTeX RDF	structured asics, via programmable fabric
24	Michael Brown, Cyrus Bazeghi, Matthew R. Guthaus, Jose Renau	Measuring and modeling variabilityusing low-cost FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	variability
24	Paul E. Marks, Cameron D. Patterson	Data streaming and simd support for the microblaze architecture.	FPGA	2009	DBLP DOI BibTeX RDF	streaming coprocessors, vector units, reconfigurability
24	Stephen Friedman, Allan Carroll, Brian Van Essen, Benjamin Ylvisaker, Carl Ebeling, Scott Hauck	SPR: an architecture-adaptive CGRA mapping tool.	FPGA	2009	DBLP DOI BibTeX RDF	modulo graph, spr, static sharing, clustering, scheduling, routing, placement, pathfinder
24	Kanupriya Gulati, Sunil P. Khatri, Peng Li 0001	Closed-loop modeling of power and temperature profiles of FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	sub-threshold leakage, dynamic power
24	Adrian Ludwin, Vaughn Betz, Ketan Padalia	High-quality, deterministic parallel placement for FPGAs on commodity hardware.	FPGA	2008	DBLP DOI BibTeX RDF	parallel placement, FPGAs, timing-driven placement
24	Jason Cong, Guoling Han, Wei Jiang	Synthesis of an application-specific soft multiprocessor system.	FPGA	2007	DBLP DOI BibTeX RDF	clustering, multiprocessor, pipeline, labeling, design space
24	Wenyi Feng, Sinan Kaptanoglu	Designing efficient input interconnect blocks for LUT clusters using counting and entropy.	FPGA	2007	DBLP DOI BibTeX RDF	cluster, FPGAs, entropy, interconnect, counting, PLDs, LUT