Search results for "MICRO"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
1	Christophe Dubach, Timothy M. Jones 0001, Edwin V. Bonilla, Michael F. P. O'Boyle	A Predictive Model for Dynamic Microarchitectural Adaptivity Control.	MICRO	2010	DBLP DOI BibTeX RDF
1	Shantanu Gupta, Shuguang Feng, Amin Ansari, Scott A. Mahlke	Erasing Core Boundaries for Robust and Configurable Performance.	MICRO	2010	DBLP DOI BibTeX RDF
1	Ali Bakhoda, John Kim, Tor M. Aamodt	Throughput-Effective On-Chip Networks for Manycore Accelerators.	MICRO	2010	DBLP DOI BibTeX RDF
1	Yoongu Kim, Michael Papamichael, Onur Mutlu, Mor Harchol-Balter	Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior.	MICRO	2010	DBLP DOI BibTeX RDF
1	Minjang Kim, Hyesoon Kim, Chi-Keung Luk	SD3: A Scalable Approach to Dynamic Data-Dependence Profiling.	MICRO	2010	DBLP DOI BibTeX RDF
1	Jaekyu Lee, Nagesh B. Lakshminarayana, Hyesoon Kim, Richard W. Vuduc	Many-Thread Aware Prefetching Mechanisms for GPGPU Applications.	MICRO	2010	DBLP DOI BibTeX RDF
1	Jie Yu 0016, Satish Narayanasamy	Tolerating Concurrency Bugs Using Transactions as Lifeguards.	MICRO	2010	DBLP DOI BibTeX RDF
1	Adrian Nistor, Darko Marinov, Josep Torrellas	InstantCheck: Checking the Determinism of Parallel Programs Using On-the-Fly Incremental Hashing.	MICRO	2010	DBLP DOI BibTeX RDF
1	Eric S. Chung, Peter A. Milder, James C. Hoe, Ken Mai	Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?	MICRO	2010	DBLP DOI BibTeX RDF
1	Aparna Kotha, Kapil Anand, Matthew Smithson, Greeshma Yellareddy, Rajeev Barua	Automatic Parallelization in a Binary Rewriter.	MICRO	2010	DBLP DOI BibTeX RDF
1	Hanjun Kim 0001, Arun Raman, Feng Liu, Jae W. Lee, David I. August	Scalable Speculative Parallelization on Commodity Clusters.	MICRO	2010	DBLP DOI BibTeX RDF
1	Yoav Etsion, Felipe Cabarcas, Alejandro Rico, Alex Ramírez, Rosa M. Badia, Eduard Ayguadé, Jesús Labarta, Mateo Valero	Task Superscalar: An Out-of-Order Task Pipeline.	MICRO	2010	DBLP DOI BibTeX RDF
1	Samira Manabi Khan, Yingying Tian, Daniel A. Jiménez	Sampling Dead Block Prediction for Last-Level Caches.	MICRO	2010	DBLP DOI BibTeX RDF
1	Matthew A. Watkins, David H. Albonesi	ReMAP: A Reconfigurable Heterogeneous Multicore Architecture.	MICRO	2010	DBLP DOI BibTeX RDF
1	Abdullah Muzahid, Norimasa Otsuki, Josep Torrellas	AtomTracker: A Comprehensive Approach to Atomic Region Inference and Violation Detection.	MICRO	2010	DBLP DOI BibTeX RDF
1	Daniel Y. Deng, Daniel Lo, Greg Malysa, Skyler Schneider, G. Edward Suh	Flexible and Efficient Instruction-Grained Run-Time Monitoring Using On-Chip Reconfigurable Fabric.	MICRO	2010	DBLP DOI BibTeX RDF
1	Timothy N. Miller, Renji Thomas, James Dinan, Bruce M. Adcock, Radu Teodorescu	Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches.	MICRO	2010	DBLP DOI BibTeX RDF
1	Jin Ouyang, Yuan Xie 0001	LOFT: A High Performance Network-on-Chip Providing Quality-of-Service Support.	MICRO	2010	DBLP DOI BibTeX RDF
1	Minseon Ahn, Eun Jung Kim 0001	Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks.	MICRO	2010	DBLP DOI BibTeX RDF
1	Vijay Janapa Reddi, Svilen Kanev, Wonyoung Kim, Simone Campanoni, Michael D. Smith 0001, Gu-Yeon Wei, David M. Brooks	Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling.	MICRO	2010	DBLP DOI BibTeX RDF
1	Erika Gunadi, Abhishek A. Sinkar, Nam Sung Kim, Mikko H. Lipasti	Combating Aging with the Colt Duty Cycle Equalizer.	MICRO	2010	DBLP DOI BibTeX RDF
1	Michael Steffen, Joseph Zambreno	Improving SIMT Efficiency of Global Rendering Algorithms with Architectural Support for Dynamic Micro-Kernels.	MICRO	2010	DBLP DOI BibTeX RDF
1	Michael Mihn-Jong Lee, John Kim, Dennis Abts, Michael R. Marty, Jae W. Lee	Probabilistic Distance-Based Arbitration: Providing Equality of Service for Many-Core CMPs.	MICRO	2010	DBLP DOI BibTeX RDF
1	Adrian M. Caulfield, Arup De, Joel Coburn, Todor I. Mollow, Rajesh K. Gupta 0001, Steven Swanson	Moneta: A High-Performance Storage Array Architecture for Next-Generation, Non-volatile Memories.	MICRO	2010	DBLP DOI BibTeX RDF
1	Syed Ali Raza Jafri, Yu-Ju Hong, Mithuna Thottethodi, T. N. Vijaykumar	Adaptive Flow Control for Robust Performance and Energy.	MICRO	2010	DBLP DOI BibTeX RDF
1	Jianwei Chen, Lakshmi Kumar Dabbiru, Daniel Wong 0001, Murali Annavaram, Michel Dubois 0001	Adaptive and Speculative Slack Simulations of CMPs on CMPs.	MICRO	2010	DBLP DOI BibTeX RDF
1	Meng Zhang 0017, Alvin R. Lebeck, Daniel J. Sorin	Fractal Coherence: Scalably Verifiable Cache Coherence.	MICRO	2010	DBLP DOI BibTeX RDF
1	Hsiang-Yun Cheng, Chung-Hsiang Lin, Jian Li, Chia-Lin Yang	Memory Latency Reduction via Thread Throttling.	MICRO	2010	DBLP DOI BibTeX RDF
1	Ryota Shioya, Kazuo Horio, Masahiro Goshima, Shuichi Sakai	Register Cache System Not for Latency Reduction Purpose.	MICRO	2010	DBLP DOI BibTeX RDF
1	Utku Aydonat, Tarek S. Abdelrahman	Hardware Support for Relaxed Concurrency Control in Transactional Memory.	MICRO	2010	DBLP DOI BibTeX RDF
1	Aamer Jaleel, Eric Borch, Malini Bhandaru, Simon C. Steely Jr., Joel S. Emer	Achieving Non-Inclusive Cache Performance with Inclusive Caches: Temporal Locality Aware (TLA) Cache Management Policies.	MICRO	2010	DBLP DOI BibTeX RDF
1		43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2010, 4-8 December 2010, Atlanta, Georgia, USA	MICRO	2010	DBLP BibTeX RDF
1	Dongyuan Zhan, Hong Jiang 0001, Sharad C. Seth	STEM: Spatiotemporal Management of Capacity for Intra-core Last Level Caches.	MICRO	2010	DBLP DOI BibTeX RDF
1	Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott A. Mahlke	ZerehCache: armoring cache architectures in high defect density technologies.	MICRO	2009	DBLP DOI BibTeX RDF	fault-tolerant cache, process variation, manufacturing yield
1	Wangyuan Zhang, Tao Li 0006	Characterizing and mitigating the impact of process variations on phase change based memory systems.	MICRO	2009	DBLP DOI BibTeX RDF	process variation, memory system, phase change memory
1	Adrian Nistor, Darko Marinov, Josep Torrellas	Light64: lightweight hardware support for data race detection during systematic testing of parallel programs.	MICRO	2009	DBLP DOI BibTeX RDF	execution history hash, data race, systematic testing
1	Christophe Dubach, Timothy M. Jones 0001, Edwin V. Bonilla, Grigori Fursin, Michael F. P. O'Boyle	Portable compiler optimisation across embedded programs and microarchitectures using machine learning.	MICRO	2009	DBLP DOI BibTeX RDF	architecture/compiler co-design, machine learning, design-space exploration
1	Hari Kannan	Ordering decoupled metadata accesses in multiprocessors.	MICRO	2009	DBLP DOI BibTeX RDF
1	Laura M. Grupp, Adrian M. Caulfield, Joel Coburn, Steven Swanson, Eitan Yaakobi, Paul H. Siegel, Jack K. Wolf	Characterizing flash memory: anomalies, observations, and applications.	MICRO	2009	DBLP DOI BibTeX RDF	flash memory, characterization, non-volatile
1	Mark Horowitz	Why design must change: rethinking digital design.	MICRO	2009	DBLP DOI BibTeX RDF
1	Vasileios Kontorinis, Amirali Shayan, Dean M. Tullsen, Rakesh Kumar 0002	Reducing peak power with a table-driven adaptive processor core.	MICRO	2009	DBLP DOI BibTeX RDF	resource resizing, voltage variation, peak power, adaptive architectures, decoupling capacitance
1	Sangyeun Cho, Hyunjin Lee	Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance.	MICRO	2009	DBLP DOI BibTeX RDF	memory write performance, phase-change memory
1	Asit K. Mishra, Reetuparna Das, Soumya Eachempati, Ravishankar R. Iyer 0001, Narayanan Vijaykrishnan, Chita R. Das	A case for dynamic frequency tuning in on-chip networks.	MICRO	2009	DBLP DOI BibTeX RDF
1	Sasa Tomic, Cristian Perfumo, Chinmay Eishan Kulkarni, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Tim Harris 0001, Mateo Valero	EazyHTM: eager-lazy hardware transactional memory.	MICRO	2009	DBLP DOI BibTeX RDF	EazyHTM, transactional memory
1	Ulya R. Karpuzcu, Brian Greskamp, Josep Torrellas	The BubbleWrap many-core: popping cores for sequential acceleration.	MICRO	2009	DBLP DOI BibTeX RDF	power wall, process scaling, processor aging, voltage scaling
1	George L. Yuan, Ali Bakhoda, Tor M. Aamodt	Complexity effective memory access scheduling for many-core accelerator architectures.	MICRO	2009	DBLP DOI BibTeX RDF	graphics processors, on-chip interconnection networks, memory controller
1	Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Wei Wu 0024, Shih-Lien Lu	Improving cache lifetime reliability at ultra-low voltages.	MICRO	2009	DBLP DOI BibTeX RDF
1	Alex Solomatnikov, Amin Firoozshahian, Ofer Shacham, Zain Asgar, Megan Wachs, Wajahat Qadeer, Stephen Richardson, Mark Horowitz	Using a configurable processor generator for computer architecture prototyping.	MICRO	2009	DBLP DOI BibTeX RDF	computer architecture prototyping, configurable/extensible processor generator, memory system architecture, reconfigurable architecture, VLSI design
1	Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha	In-network coherence filtering: snoopy coherence without broadcasts.	MICRO	2009	DBLP DOI BibTeX RDF
1	Ciji Isen, Lizy Kurian John	ESKIMO: Energy savings using Semantic Knowledge of Inconsequential Memory Occupancy for DRAM subsystem.	MICRO	2009	DBLP DOI BibTeX RDF	allocated and freed memory states, cross-boundary or cross-layer architecture optimizations, memory power and energy, program semantic aware architecture
1	Moinuddin K. Qureshi, John P. Karidis, Michele Franceschini, Vijayalakshmi Srinivasan, Luis A. Lastras, Bülent Abali	Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling.	MICRO	2009	DBLP DOI BibTeX RDF	phase change memory, wear leveling, endurance
1	Hyunchul Park 0001, Yongjun Park 0001, Scott A. Mahlke	Polymorphic pipeline array: a flexible multicore accelerator with virtualized execution for mobile multimedia applications.	MICRO	2009	DBLP DOI BibTeX RDF	programmable accelerator, virtualization, software pipelining
1	Hongbo Rong	Tree register allocation.	MICRO	2009	DBLP DOI BibTeX RDF	register allocation, chordal graph
1	Chang Joo Lee, Veynu Narasiman, Onur Mutlu, Yale N. Patt	Improving memory bank-level parallelism in the presence of prefetching.	MICRO	2009	DBLP DOI BibTeX RDF
1	David H. Albonesi, Margaret Martonosi, David I. August, José F. Martínez (eds.)	42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA	MICRO	2009	DBLP BibTeX RDF
1	Shekhar Srikantaiah, Mahmut T. Kandemir, Qian Wang	SHARP control: controlled shared cache management in chip multiprocessors.	MICRO	2009	DBLP DOI BibTeX RDF
1	Mahesh Ketkar, Eli Chiprout	A microarchitecture-based framework for pre- and post-silicon power delivery analysis.	MICRO	2009	DBLP DOI BibTeX RDF
1	Boris Grot, Stephen W. Keckler, Onur Mutlu	Preemptive virtual clock: a flexible, efficient, and cost-effective QOS scheme for networks-on-chip.	MICRO	2009	DBLP DOI BibTeX RDF
1	Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das	Application-aware prioritization mechanisms for on-chip networks.	MICRO	2009	DBLP DOI BibTeX RDF	multi-core, packet scheduling, memory systems, arbitration, prioritization, on-chip networks
1	Jaume Abella 0001, Javier Carretero, Pedro Chaparro, Xavier Vera, Antonio González 0001	Low Vccmin fault-tolerant cache with highly predictable performance.	MICRO	2009	DBLP DOI BibTeX RDF	Vccmin, cache, faults, predictable performance
1	Wonsun Ahn, Shanxiang Qi, M. Nicolaides, Josep Torrellas, Jae-Woo Lee, Xing Fang, Samuel P. Midkiff, David C. Wong 0001	BulkCompiler: high-performance sequential consistency through cooperative compiler and hardware support.	MICRO	2009	DBLP DOI BibTeX RDF	atomic region, chunk-based architecture, compiler optimization, sequential consistency
1	Dana Vantrease, Nathan L. Binkert, Robert Schreiber, Mikko H. Lipasti	Light speed arbitration and flow control for nanophotonic interconnects.	MICRO	2009	DBLP DOI BibTeX RDF
1	Vladimir Cakarevic, Petar Radojkovic, Javier Verdú, Alex Pajuelo, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero	Characterizing the resource-sharing levels in the UltraSPARC T2 processor.	MICRO	2009	DBLP DOI BibTeX RDF	Sun Nigara T2, CMP, job scheduling, simultaneous multithreading, performance characterization, CMT
1	Mahmut T. Kandemir, Sai Prashanth Muralidhara, Sri Hari Krishna Narayanan, Yuanrui Zhang, Ozcan Ozturk 0001	Optimizing shared cache behavior of chip multiprocessors.	MICRO	2009	DBLP DOI BibTeX RDF
1	Daniel Hackenberg, Daniel Molka, Wolfgang E. Nagel	Comparing cache architectures and coherency protocols on x86-64 multicore SMP systems.	MICRO	2009	DBLP DOI BibTeX RDF	Nehalem, Shanghai, benchmark, multi-core, coherency
1	Haibo Chen 0001, Liwei Yuan, Xi Wu 0001, Binyu Zang, Bo Huang 0002, Pen-Chung Yew	Control flow obfuscation with information flow tracking.	MICRO	2009	DBLP DOI BibTeX RDF	control flow obfuscation, opaque predicate, information flow tracking, control speculation
1	Jason Zebchuk, Vijayalakshmi Srinivasan, Moinuddin K. Qureshi, Andreas Moshovos	A tagless coherence directory.	MICRO	2009	DBLP DOI BibTeX RDF	directory coherence, cache coherence, Bloom filters
1	Alex Shye, Benjamin Scholbrock, Gokhan Memik	Into the wild: studying real user activity patterns to guide power optimizations for mobile architectures.	MICRO	2009	DBLP DOI BibTeX RDF
1	Mainak Chaudhuri	Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches.	MICRO	2009	DBLP DOI BibTeX RDF	chip-multiprocessor, replacement policy, last-level cache
1	Mitchell Hayenga, Natalie D. Enright Jerger, Mikko H. Lipasti	SCARAB: a single cycle adaptive routing and bufferless network.	MICRO	2009	DBLP DOI BibTeX RDF	routing, interconnection networks, multi-core
1	John Kim	Low-cost router microarchitecture for on-chip networks.	MICRO	2009	DBLP DOI BibTeX RDF	router microarchitecture, complexity, on-chip network
1	Efraim Rotem, Avi Mendelson, Ran Ginosar, Uri C. Weiser	Multiple clock and voltage domains for chip multi processors.	MICRO	2009	DBLP DOI BibTeX RDF	clock domains, voltage domain, power management, DVFS, chip multi processor
1	Siva Kumar Sastry Hari, Man-Lap Li, Pradeep Ramachandran, Byn Choi, Sarita V. Adve	mSWAT: low-cost hardware fault detection and diagnosis for multicore systems.	MICRO	2009	DBLP DOI BibTeX RDF	architecture, error detection, fault injection, multicore processors
1	Dongyoon Lee, Mahmoud Said, Satish Narayanasamy, Zijiang Yang 0006, Cristiano Pereira	Offline symbolic analysis for multi-processor execution replay.	MICRO	2009	DBLP DOI BibTeX RDF	multi-processor replay, shared-memory dependencies, SMT solver
1	Eiman Ebrahimi, Onur Mutlu, Chang Joo Lee, Yale N. Patt	Coordinated control of multiple prefetchers in multi-core systems.	MICRO	2009	DBLP DOI BibTeX RDF	prefetching, multi-core, feedback control, memory systems
1	Geoffrey Blake, Ronald G. Dreslinski, Trevor N. Mudge	Proactive transaction scheduling for contention management.	MICRO	2009	DBLP DOI BibTeX RDF	proactive scheduling, software runtime, hardware transactional memory
1	Gabriel H. Loh	Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy.	MICRO	2009	DBLP DOI BibTeX RDF
1	Changhee Jung, Nathan Clark	DDT: design and evaluation of a dynamic program analysis for optimizing data structure usage.	MICRO	2009	DBLP DOI BibTeX RDF	data structure identification, interface functions, memory graphs
1	Gilles Pokam, Cristiano Pereira, Klaus Danne, Rolf Kassa, Ali-Reza Adl-Tabatabai	Architecting a chunk-based memory race recorder in modern CMPs.	MICRO	2009	DBLP DOI BibTeX RDF	memory race recorder, determinism, deterministic replay
1	Mohit Tiwari, Xun Li 0001, Hassan M. G. Wassel, Frederic T. Chong, Timothy Sherwood	Execution leases: a hardware-supported mechanism for enforcing strong non-interference.	MICRO	2009	DBLP DOI BibTeX RDF	gate level information flow tracking, covert channels, high assurance systems, timing channels
1	Dyer Rolán, Basilio B. Fraguela, Ramon Doallo	Adaptive line placement with the set balancing cache.	MICRO	2009	DBLP DOI BibTeX RDF	performance, adaptivity, cache, balancing
1	Alejandro Valero, Julio Sahuquillo, Salvador Petit, Vicente Lorente, Ramon Canal, Pedro López 0001, José Duato	An hybrid eDRAM/SRAM macrocell to implement first-level data caches.	MICRO	2009	DBLP DOI BibTeX RDF	retention time, static and dynamic memory cells, leakage current
1	Brandon Lucia, Luis Ceze	Finding concurrency bugs with context-aware communication graphs.	MICRO	2009	DBLP DOI BibTeX RDF
1	Bo Zhao 0007, Yu Du, Youtao Zhang, Jun Yang 0002	Variation-tolerant non-uniform 3D cache management in die stacked multicore processor.	MICRO	2009	DBLP DOI BibTeX RDF	3D die stacking, NUCA, process variation, DRAM
1	Sheng Li 0007, Jung Ho Ahn, Richard D. Strong, Jay B. Brockman, Dean M. Tullsen, Norman P. Jouppi	McPAT: an integrated power, area, and timing modeling framework for multicore and manycore architectures.	MICRO	2009	DBLP DOI BibTeX RDF
1	Chi-Keung Luk, Sunpyo Hong, Hyesoon Kim	Qilin: exploiting parallelism on heterogeneous multiprocessors with adaptive mapping.	MICRO	2009	DBLP DOI BibTeX RDF	adaptive, GPU, mapping, heterogeneous, multicore, dynamic compilation
1	Balaram Sinharoy	POWER7 multi-core processor design.	MICRO	2009	DBLP DOI BibTeX RDF
1	Meeta Sharma Gupta, Jude A. Rivers, Pradip Bose, Gu-Yeon Wei, David M. Brooks	Tribeca: design for PVT variations with local recovery and fine-grained adaptation.	MICRO	2009	DBLP DOI BibTeX RDF
1	Mark Woh, Yuan Lin 0002, Sangwon Seo, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Richard Bruce, Danny Kershaw, Alastair Reid 0001, Mladen Wilder, Krisztián Flautner	From SODA to scotch: The evolution of a wireless baseband processor.	MICRO	2008	DBLP DOI BibTeX RDF
1	Livio Soares, David K. Tam, Michael Stumm	Reducing the harmful effects of last-level cache polluters with an OS-level, software-only pollute buffer.	MICRO	2008	DBLP DOI BibTeX RDF
1	Aqeel Mahesri, Daniel R. Johnson, Neal Clayton Crago, Sanjay J. Patel	Tradeoffs in designing accelerator architectures for visual computing.	MICRO	2008	DBLP DOI BibTeX RDF
1	Haiming Liu 0001, Michael Ferdman, Jaehyuk Huh 0001, Doug Burger	Cache bursts: A new approach for eliminating dead blocks and increasing cache efficiency.	MICRO	2008	DBLP DOI BibTeX RDF
1	Arun Raghavan, Colin Blundell, Milo M. K. Martin	Token tenure: PATCHing token counting using directory-based cache coherence.	MICRO	2008	DBLP DOI BibTeX RDF
1	Isidro Gonzalez, Marco Galluzzi, Alexander V. Veidenbaum, Marco Antonio Ramírez, Adrián Cristal, Mateo Valero	A distributed processor state management architecture for large-window processors.	MICRO	2008	DBLP DOI BibTeX RDF
1	Chen Tian 0002, Min Feng 0001, Vijay Nagarajan, Rajiv Gupta 0001	Copy or Discard execution model for speculative parallelization on multicores.	MICRO	2008	DBLP DOI BibTeX RDF
1	Xin Fu, Tao Li 0006, José A. B. Fortes	NBTI tolerant microarchitecture design in the presence of process variation.	MICRO	2008	DBLP DOI BibTeX RDF
1	Abhishek Das, Berkin Özisikyilmaz, Serkan Ozdemir, Gokhan Memik, Joseph Zambreno, Alok N. Choudhary	Evaluating the effects of cache redundancy on profit.	MICRO	2008	DBLP DOI BibTeX RDF
1	M.-C. Frank Chang, Jason Cong, Adam Kaplan, Chunyue Liu, Mishali Naik, Jagannath Premkumar, Glenn Reinman, Eran Socher, Sai-Wang Tam	Power reduction of CMP communication networks via RF-interconnects.	MICRO	2008	DBLP DOI BibTeX RDF
1	Mohit Tiwari, Banit Agrawal, Shashidhar Mysore, Jonathan Valamehr, Timothy Sherwood	A small cache of large ranges: Hardware methods for efficiently searching, storing, and updating big dataflow tags.	MICRO	2008	DBLP DOI BibTeX RDF
1	Xi E. Chen, Tor M. Aamodt	Hybrid analytical modeling of pending cache hits, data prefetching, and MSHRs.	MICRO	2008	DBLP DOI BibTeX RDF

Publications at "MICRO"( http://dblp.L3S.de/Venues/MICRO )