Search results for "SOI"

Hits ?▲	Authors	Title	Venue	Year	Link
13	Toke Meyer Andersen, Florian Krismer, Johann W. Kolar, Thomas Toifl, Christian Menolfi, Lukas Kull, Thomas Morf, Marcel A. Kossel, Matthias Braendli, Peter Buchmann, Pier Andrea Francese	4.7 A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm2 at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS.	ISSCC	2014	DBLP DOI BibTeX RDF
13	Vanessa Hung-Chu Chen, Lawrence T. Pileggi	22.2 A 69.5mW 20GS/s 6b time-interleaved ADC with embedded time-to-digital calibration in 32nm CMOS SOI.	ISSCC	2014	DBLP DOI BibTeX RDF
13	Eric J. Fluhr, Joshua Friedrich, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, Allen Hall, David Hogenmiller, Frank Malgioglio, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Ruchir Puri, Phillip J. Restle, David Shan, Kevin Stawiasz, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler	5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth.	ISSCC	2014	DBLP DOI BibTeX RDF
13	Lukas Kull, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici	22.1 A 90GS/s 8b 667mW 64× interleaved SAR ADC in 32nm digital SOI CMOS.	ISSCC	2014	DBLP DOI BibTeX RDF
13	Philippe Flatresse	Process and design solutions for exploiting FD-SOI technology towards energy efficient SOCs.	ISLPED	2014	DBLP DOI BibTeX RDF
13	Michael Georgas, Benjamin Moss, Chen Sun 0003, Jeffrey Shainline, Jason Orcutt, Mark T. Wade, Yu-Hsin Chen, Kareem Nammari, Jonathan C. Leu, Aravind Srinivasan, Rajeev J. Ram, Milos A. Popovic, Vladimir Stojanovic	A monolithically-integrated optical transmitter and receiver in a zero-change 45nm SOI process.	VLSIC	2014	DBLP DOI BibTeX RDF
13	Seungwoo Jung, Troy D. England, Ickhyun Song, Bryan Wier, John D. Cressler, Jeff A. Babcock	A complementary SiGe HBT on SOI low dropout voltage regulator utilizing a nulling resistor.	ISCAS	2014	DBLP DOI BibTeX RDF
13	Nicholas Axelos, Nikolaos Eftaxiopoulos-Sarris, Georgios Zervakis 0001, Kostas Tsoumanis, Kiamal Z. Pekmestzi	FF-DICE: An 8T soft-error tolerant cell using Independent Dual Gate SOI FinFETs.	IOLTS	2014	DBLP DOI BibTeX RDF
13	Jinghui Zou, Yu Yu, Weili Yang, Zhao Wu, Mengyuan Ye, Guanyu Chen, Xinliang Zhang	An SOI based polarization insensitive filter for all-optical clock recovery.	OFC	2014	DBLP DOI BibTeX RDF
13	Ying Huang, Xianshu Luo, Junfeng Song, Tsung-Yang Liow, Patrick Guo-Qiang Lo	Low loss (<0.2dB per transition) CMOS compatible multi-layer Si3N4-on-SOI platform with thermal-optics device integration for silicon photonics.	OFC	2014	DBLP DOI BibTeX RDF
13	Wesley D. Sacher, Ying Huang, Ding Liang, Tymon Barwicz, Jared C. Mikkelsen, Benjamin J. F. Taylor, Guo-Qiang Lo, Joyce K. S. Poon	Si3N4-on-SOI polarization rotator-splitter based on TM0-TE1 mode conversion.	OFC	2014	DBLP DOI BibTeX RDF
13	Bryce A. Dorin, Winnie N. Ye	A two-mode division multiplexing filter demonstrated Using a SOI ring resonator.	OFC	2014	DBLP DOI BibTeX RDF
13	Yu Geng, Shaoqi Feng, Andrew W. Poon, Kei May Lau	High-speed InGaAs photodetectors with low dark current selectively grown on SOI substrate.	OFC	2014	DBLP DOI BibTeX RDF
13	Vladimir Verstov, Vadim A. Shakhnov, Lyudmila Zinchenko	Parallel Algorithm of SOI Layout Decomposition for Double Patterning Lithography on High-Performance Computer Platforms.	DoCEIS	2014	DBLP DOI BibTeX RDF
13	Jean-Pierre Raskin	SOI technology: An opportunity for RF designers?	VLSI-DAT	2014	DBLP DOI BibTeX RDF
13	Yejin Chen, Goh Wang Ling, Jun Yu, Muthukumaraswamy Annamalai Arasu	An SOI-CMOS low noise chopper amplifier for high temperature applications.	ISIC	2014	DBLP DOI BibTeX RDF
13	D. H. Lung, S. K. Hu, James B. Kuo, D. Chen, Y. J. Chen	Parasitic BJT versus DIBL: Floating-body-related subthreshold characteristics of SOI NMOS device.	ISIC	2014	DBLP DOI BibTeX RDF
13	Hans Reyserhove, Nele Reynders, Wim Dehaene	Ultra-low voltage datapath blocks in 28nm UTBB FD-SOI.	A-SSCC	2014	DBLP DOI BibTeX RDF
13	Lukas Kull, Jan Plíva, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici	A 110 mW 6 bit 36 GS/s interleaved SAR ADC for 100 GBE occupying 0.048 mm2 in 32 nm SOI CMOS.	A-SSCC	2014	DBLP DOI BibTeX RDF
13	Fei Song, Sam Chun-Geik Tan, Osama Shana'a	An ultra-low-cost ESD-protected 0.65dB NF +10dBm OP1dB GNSS LNA in 0.18-μm SOI CMOS.	A-SSCC	2014	DBLP DOI BibTeX RDF
13	Aravind Tharayil Narayanan, Wei Deng 0001, Dongsheng Yang 0002, Rui Wu 0001, Kenichi Okada, Akira Matsuzawa	A 0.011 mm2 PVT-robust fully-synthesizable CDR with a data rate of 10.05 Gb/s in 28nm FD SOI.	A-SSCC	2014	DBLP DOI BibTeX RDF
13	Jean-Max Dutertre, Stephan De Castro, Alexandre Sarafianos, Noemie Boher, Bruno Rouzeyre, Mathieu Lisart, Joel Damiens, Philippe Candelier, Marie-Lise Flottes, Giorgio Di Natale	Laser attacks on integrated circuits: From CMOS to FD-SOI.	DTIS	2014	DBLP DOI BibTeX RDF
13	Roma Dasgupta, Szymon Bugiel, Sebastian Glab, Marek Idzik, Jakub Moron, Piotr Kapusta	Design and simulations of the 10-bit SAR ADC in novel sub-micron technology 200 nm SOI CMOS.	MIXDES	2014	DBLP DOI BibTeX RDF
13	Szymon Bugiel, Roma Dasgupta, Sebastian Glab, Marek Idzik, Piotr Kapusta	Development of pixel detector in Novel sub-micron technology SOI CMOS 200 nm.	MIXDES	2014	DBLP DOI BibTeX RDF
13	Saman Kiamehr, Thomas H. Osiecki, Mehdi Baradaran Tahoori, Sani R. Nassif	Radiation-Induced Soft Error Analysis of SRAMs in SOI FinFET Technology: A Device to Circuit Approach.	DAC	2014	DBLP DOI BibTeX RDF
13	Yeter Akgul, Diego Puschini, Suzanne Lesecq, Edith Beigné, Ivan Miro Panades, Pascal Benoit, Lionel Torres	Power management through DVFS and dynamic body biasing in FD-SOI circuits.	DAC	2014	DBLP DOI BibTeX RDF
13	David E. Bellasi, Luca Bettini, Thomas Burger, Christian Benkeser, Qiuting Huang, Christoph Studer	Compressive sensing spectrum recovery from quantized measurements in 28nm SOI CMOS.	EUSIPCO	2014	DBLP BibTeX RDF
13	Benjamin Wohlfeil, Christos Stamatiadis, M. Jager, Lars Zimmermann, Sven Burger, Klaus Petermann	Integrated optical fiber grating coupler on SOI for the excitation of several higher order fiber modes.	ECOC	2014	DBLP DOI BibTeX RDF
13	Yunhong Ding, Haiyan Ou, Christophe Peucheret, Kresten Yvind	Fully-etched apodized fiber-to-chip grating coupler on the SOI platform with -0.78 dB coupling efficiency using photonic crystals and bonded Al mirror.	ECOC	2014	DBLP DOI BibTeX RDF
13	Sotirios Papaioannou 0001, George Dabos, Kostantinos Vyrsokinos, Giannis Giannoulis, A. Prinzen, C. Porschatis, M. Waldow, Dimitris Apostolopoulos, Hercules Avramopoulos, Nikos Pleros	Eight-channel second-order ring resonator based SOI multiplexers/demultiplexers for optical interconnects.	ECOC	2014	DBLP DOI BibTeX RDF
13	Yunhong Ding, Feihong Ye, Christophe Peucheret, Haiyan Ou, Yutaka Miyamoto, Toshio Morioka	On-chip grating coupler array on the SOI platform for fan-in/fan-out of multi-core fibers with low insertion loss and crosstalk.	ECOC	2014	DBLP DOI BibTeX RDF
13	Lukas Kull, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici	A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
13	Andreea Balteanu, Ioannis Sarkas, Eric Dacquay, Alexander Tomkins, Gabriel M. Rebeiz, Peter M. Asbeck, Sorin P. Voinigescu	A 2-Bit, 24 dBm, Millimeter-Wave SOI CMOS Power-DAC Cell for Watt-Level High-Efficiency, Fully Digital m-ary QAM Transmitters.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
13	Jing-Hwa Chen, S. R. Helmi, R. Azadegan, F. Aryanfar, S. Mohammadi	A Broadband Stacked Power Amplifier in 45-nm CMOS SOI Technology.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
13	Amir Agah, Hayg-Taniel Dabag, Bassel Hanafi, Peter M. Asbeck, James F. Buckwalter, Lawrence E. Larson	Active Millimeter-Wave Phase-Shift Doherty Power Amplifier in 45-nm SOI CMOS.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
13	Sami Rosenblatt, Daniel Fainstein, Alberto Cestero, John Safran, Norman Robson, Toshiaki Kirihata, Subramanian S. Iyer	Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
13	Marcel A. Kossel, Thomas Toifl, Pier Andrea Francese, Matthias Braendli, Christian Menolfi, Peter Buchmann, Lukas Kull, Toke Meyer Andersen, Thomas Morf	A 10 Gb/s 8-Tap 6b 2-PAM/4-PAM Tomlinson-Harashima Precoding Transmitter for Future Memory-Link Applications in 22-nm SOI CMOS.	IEEE J. Solid State Circuits	2013	DBLP DOI BibTeX RDF
13	John S. Liberty, Adrian Barrera, David W. Boerstler, Thomas B. Chadwick, Scott R. Cottier, H. Peter Hofstee, Julie A. Rosser, Marty L. Tsai	True hardware random number generation implemented in the 32-nm SOI POWER7+ processor.	IBM J. Res. Dev.	2013	DBLP DOI BibTeX RDF
13	Bingxu Ning, Dawei Bi, Huixiang Huang, Zhengxuan Zhang, Ming Chen 0007, Shichang Zou	Comprehensive study on the TID effects of 0.13 μm partially depleted SOI NMOSFETs.	Microelectron. J.	2013	DBLP DOI BibTeX RDF
13	Simona A. Cozzi, Lorenzo Labate, Roberto Stella	Extraction of scalable electrical model for a SOI JFET using BSIM3 model.	Microelectron. J.	2013	DBLP DOI BibTeX RDF
13	Lingli Jiang, Hang Fan, Ming Qiao, Bo Zhang 0027, Zhaoji Li	ESD characterization of a 190V LIGBT SOI ESD power clamp structure for plasma display panel applications.	Microelectron. Reliab.	2013	DBLP DOI BibTeX RDF
13	Xiaowu Cai, Junxiu Wei, Chao Liang, Zhe Gao, Chuan Lv	Investigation of high voltage SCR-LDMOS ESD device for 150 V SOI BCD process.	Microelectron. Reliab.	2013	DBLP DOI BibTeX RDF
13	Michelly de Souza, Bruna Cardoso Paz, Denis Flandre, Marcelo Antonio Pavanello	Asymmetric channel doping profile and temperature reduction influence on the performance of current mirrors implemented with FD SOI nMOSFETs.	Microelectron. Reliab.	2013	DBLP DOI BibTeX RDF
13	Masayuki Yoshimura, Atsushi Uchida, Satoshi Matsumoto	Design issues of a thin-film p-channel SOI power MOSFET for high-temperature applications.	Microelectron. Reliab.	2013	DBLP DOI BibTeX RDF
13	Bingxu Ning, Dawei Bi, Huixiang Huang, Zhengxuan Zhang, Zhiyuan Hu, Ming Chen 0007, Shichang Zou	Bias dependence of TID radiation responses of 0.13 μm partially depleted SOI NMOSFETs.	Microelectron. Reliab.	2013	DBLP DOI BibTeX RDF
13	Ganesh C. Patil, Shafi Qureshi	Engineering buried oxide in dopant-segregated Schottky barrier SOI MOSFET for nanoscale CMOS circuits.	Microelectron. Reliab.	2013	DBLP DOI BibTeX RDF
13	Xingsheng Wang, Binjie Cheng, Jente B. Kuang, Andrew R. Brown, Campbell Millar, Asen Asenov	Statistical Variability and Reliability and the Impact on Corresponding 6T-SRAM Cell Design for a 14-nm Node SOI FinFET Technology.	IEEE Des. Test	2013	DBLP DOI BibTeX RDF
13	El Hafed Boufouss, Laurent A. Francis, Valeria Kilchytska, Pierre Gérard, Pascal Simon, Denis Flandre	Ultra-Low Power High Temperature and Radiation Hard Complementary Metal-Oxide-Semiconductor (CMOS) Silicon-on-Insulator (SOI) Voltage Reference.	Sensors	2013	DBLP DOI BibTeX RDF
13	Huiquan Wang, Junyi Yang, Sheping Yan, Zhonghe Jin	Thin Layer SOI-FETs Used for Stress-Sensing and Its Application in Accelerometers.	IEEE Trans Autom. Sci. Eng.	2013	DBLP DOI BibTeX RDF
13	Timothy D. Gathman, James F. Buckwalter	A 45-nm SOI CMOS Integrate-and-Dump Optical Sampling Receiver.	IEEE Trans. Circuits Syst. I Regul. Pap.	2013	DBLP DOI BibTeX RDF
13	Jean-Olivier Plouchart, Mark A. Ferriss, A. S. Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Larry T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman	A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS.	IEEE Trans. Circuits Syst. I Regul. Pap.	2013	DBLP DOI BibTeX RDF
13	Satoshi Shiraki, Shigeki Takahashi, Youichi Ashida, Atsuyuki Hiruma, Tsuyoshi Funaki	Loss reduction of lateral power diode on SOI substrate with trenched buried oxide layer.	IEICE Electron. Express	2013	DBLP DOI BibTeX RDF
13	Xiaoming Yang, Tianqian Li, Yu Cai, Jun Wang, Changjiang Chen	High voltage (>1100V) SOI LDMOS with an accumulated charges layer for double enhanced dielectric electric field.	IEICE Electron. Express	2013	DBLP DOI BibTeX RDF
13	Jun-Ku Kim, Chang-Wook Baek	Capacitive pressure sensor with wafer-through silicon vias using SOI-Si direct wafer bonding and glass reflow technique.	IEICE Electron. Express	2013	DBLP DOI BibTeX RDF
13	Sawsan Abdul-Majid, Imad Hasan, Qi Zheng, Ramón Maldonado-Basilio, Serge Bidnyk, Trevor J. Hall	90° SOI optical hybrid for Radio-over-fibre links.	Ann. des Télécommunications	2013	DBLP DOI BibTeX RDF
13	Remi Coquand, Sylvain Barraud, Mikaël Cassé, Masahiro Koyama, Virginie Maffini-Alvaro, Marie-Pierre Samson, Lucie Tosti, Xavier Mescot, Gérard Ghibaudo, Stéphane Monfray, Frédéric Boeuf, Olivier Faynot, Barbara De Salvo	Low-temperature transport characteristics in SOI and sSOI nanowires down to 8nm width: Evidence of IDS and mobility oscillations.	ESSDERC	2013	DBLP DOI BibTeX RDF
13	Carlos Navarro, Maryline Bawedin, François Andrieu, Bruno Sagnes, Sorin Cristoloveanu	Why are SCE overestimated in FD-SOI MOSFETs?	ESSDERC	2013	DBLP DOI BibTeX RDF
13	Xingsheng Wang, Binjie Cheng, Andrew R. Brown, Campbell Millar, Jente B. Kuang, Sani R. Nassif, Asen Asenov	Impact of statistical variability and charge trapping on 14 nm SOI FinFET SRAM cell stability.	ESSDERC	2013	DBLP DOI BibTeX RDF
13	Masahiro Koyama, Mikaël Cassé, Remi Coquand, Sylvain Barraud, Gérard Ghibaudo, Hiroshi Iwai, Gilles Reimbold	Influence of device scaling on low-frequency noise in SOI tri-gate N- and p-type Si nanowire MOSFETs.	ESSDERC	2013	DBLP DOI BibTeX RDF
13	Yeter Akgul, Diego Puschini, Suzanne Lesecq, Edith Beigné, Pascal Benoit, Lionel Torres	Methodology for Power Mode selection in FD-SOI circuits with DVFS and Dynamic Body Biasing.	PATMOS	2013	DBLP DOI BibTeX RDF
13	Bertrand Pelloux-Prayer, Alexandre Valentian, Bastien Giraud, Yvain Thonnart, Jean-Philippe Noel, Philippe Flatresse, Edith Beigné	Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
13	Konstantin O. Petrosyants, Igor A. Kharitonov, D. A. Popov	Coupled TCAD-SPICE simulation of parasitic BJT effect on SOI CMOS SRAM SEU.	EWDTS	2013	DBLP DOI BibTeX RDF
13	Konstantin O. Petrosyants, Igor A. Kharitonov, Lev M. Sambursky, V. N. Bogatyrev, Z. M. Povarnitcyna, E. S. Drozdenko	Simulation of total dose influence on analog-digital SOI/SOS CMOS circuits with EKV-RAD macromodel.	EWDTS	2013	DBLP DOI BibTeX RDF
13	Ivan Lovshenko, Vladislav Nelayev, Sergey Shvedov, Vitaly Solodukha, Arkady Turtsevich	IGBT on SOI. Technology and construction investigation.	EWDTS	2013	DBLP DOI BibTeX RDF
13	Sunghyun Park 0002, Masood Qazi, Li-Shiuan Peh, Anantha P. Chandrakasan	40.4fJ/bit/mm low-swing on-chip signaling with self-resetting logic repeaters embedded within a mesh NoC in 45nm SOI CMOS.	DATE	2013	DBLP DOI BibTeX RDF
13	Philippe Magarshack, Philippe Flatresse, Giorgio Cesana	UTBB FD-SOI: a process/design symbiosis for breakthrough energy-efficiency.	DATE	2013	DBLP DOI BibTeX RDF
13	Jérémie Hamon, Edith Beigné	Automatic Leakage Control for Wide Range Performance QDI Asynchronous Circuits in FD-SOI Technology.	ASYNC	2013	DBLP DOI BibTeX RDF
13	Jonathan Hernandez, Tugrul Zure, Sazzadur Chowdhury	Capacitance measurements of an SOI based CMUT.	LASCAS	2013	DBLP DOI BibTeX RDF
13	Andres Amaya, Francisco Villota, Guillermo Espinosa	A robust to PVT fully-differential amplifier in 45nm SOI-CMOS technology.	LASCAS	2013	DBLP DOI BibTeX RDF
13	Azzedin D. Es-Sakhi, Masud H. Chowdhury	Analytical model to estimate the subthreshold swing of SOI FinFET.	ICECS	2013	DBLP DOI BibTeX RDF
13	Alessandro da Silveira Dias, Leandro Krug Wives, Isabela Gasparini	SOI Based Video Recommender Systems - Interaction Design Issues and Collective Intelligence.	WAIHCWS	2013	DBLP BibTeX RDF
13	Alexander Schmidt, Holger Kappert, Rainer Kokozinski	High temperature analog circuit design in PD-SOI CMOS technology using reverse body biasing.	ESSCIRC	2013	DBLP DOI BibTeX RDF
13	Vivek Asthana, Malathi Kar, Jean Jimenez, Jean-Philippe Noel, Sébastien Haendler, Philippe Galy	Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control.	ESSCIRC	2013	DBLP DOI BibTeX RDF
13	Stefan Shopov, Andreea Balteanu, Sorin P. Voinigescu	A 19-dBm, 15-Gbaud, 9-bit SOI CMOS power-DAC cell for high-order QAM W-band transmitters.	ESSCIRC	2013	DBLP DOI BibTeX RDF
13	Haifeng Ma, Ronan A. R. van der Zee, Bram Nauta	An integrated 80-V class-D power output stage with 94% efficiency in a 0.14µm SOI BCD process.	ESSCIRC	2013	DBLP DOI BibTeX RDF
13	Gauthier Tant, Alexandre Giry, Pierre Vincent, Jean-Daniel Arnould, Jean-Michel Fournier	A 2.14GHz watt-level power amplifier with passive load modulation in a SOI CMOS technology.	ESSCIRC	2013	DBLP DOI BibTeX RDF
13	Liping Wei, Chenyang Xue, Junbin Zang, Danfeng Cui, Yonghua Wang 0002, Wendong Zhang 0001	Analysis of second-order radial mode dips in racetrack optical ring resonator based on SOI rib waveguide.	NEMS	2013	DBLP DOI BibTeX RDF
13	Jianbing Xie, Meng Song, Weizheng Yuan	A high sensitivity micromachined accelerometer with an enhanced inertial mass SOI MEMS process.	NEMS	2013	DBLP DOI BibTeX RDF
13	William Lepkowski, Seth J. Wilk, J. Kam, Trevor J. Thornton	40V MESFETs fabricated on 32nm SOI CMOS.	CICC	2013	DBLP DOI BibTeX RDF
13	Mihai A. T. Sanduleanu, Alberto Valdes-Garcia, Y. Liu, Benjamin D. Parker, Shlomo Shlafman, Benny Sheinman, Danny Elad, Scott K. Reynolds, Daniel J. Friedman	A 60GHz, linear, direct down-conversion mixer with mm-Wave tunability in 32nm CMOS SOI.	CICC	2013	DBLP DOI BibTeX RDF
13	Yousr Ismail, Chang-Jin Kim 0001, Chih-Kong Ken Yang	A bipolar >40-V driver in 45-nm SOI CMOS technology.	CICC	2013	DBLP DOI BibTeX RDF
13	X. Shawn Wang, Xin Wang 0031, Fei Lu 0004, Li Wang 0058, Rui Ma 0003, Zongyu Dong, Li Sun, Albert Z. Wang, C. Patrick Yue, Dawn Wang, Alvin J. Joseph	A smartphone SP10T T/R switch in 180-nm SOI CMOS with 8kV+ ESD protection by co-design.	CICC	2013	DBLP DOI BibTeX RDF
13	Volker Blaschke, Aharon Unikovski, Paul Hurwitz, Samir Chaudhry	A SP9T cellular antenna switch in 2.5 V CMOS thin-film SOI.	RWS	2013	DBLP DOI BibTeX RDF
13	Florence Sonnerat, Romain Pilard, Frederic Gianesello, Sebastien Jan, François Le Pennec, Christian Person, Cedric Durand, Daniel Gloria	30 dBm P1dB and 4 dB insertion losses optimized 4G antenna tuner fully integrated in a 130 nm CMOS SOI technology.	RWS	2013	DBLP DOI BibTeX RDF
13	Jefy Alex Jayamon, Amir Agah, Bassel Hanafi, Hayg Dabag, James F. Buckwalter, Peter M. Asbeck	A W-band stacked FET power amplifier with 17 dBm Psat in 45-nm SOI MOS.	RWS	2013	DBLP DOI BibTeX RDF
13	Lukas Kull, Thomas Toifl, Martin L. Schmatz, Pier Andrea Francese, Christian Menolfi, Matthias Braendli, Marcel A. Kossel, Thomas Morf, Toke Meyer Andersen, Yusuf Leblebici	A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS.	ISSCC	2013	DBLP DOI BibTeX RDF
13	Zheng Wang 0014, Pei-Yuan Chiang, Peyman Nazari, Chun-Cheng Wang, Zhiming Chen 0001, Payam Heydari	A 210GHz fully integrated differential transceiver with fundamental-frequency VCO in 32nm SOI CMOS.	ISSCC	2013	DBLP DOI BibTeX RDF
13	Seongjong Kim, Inyong Kwon, David Fick, Myungbo Kim, Yen-Po Chen, Dennis Sylvester	Razor-lite: A side-channel error-detection register for timing-margin recovery in 45nm SOI CMOS.	ISSCC	2013	DBLP DOI BibTeX RDF
13	Harold Pilo, Chad A. Adams, Igor Arsovski, Robert M. Houle, Steve Lamphier, Michael M. Lee, Frank Pavlik, Sushma N. Sambatur, Adnan Seferagic, Richard Wu, Mohammad Imran Younus	A 64Mb SRAM in 22nm SOI technology featuring fine-granularity power gating and low-energy power-supply-partition techniques for 37% leakage reduction.	ISSCC	2013	DBLP DOI BibTeX RDF
13	Yong Liu 0023, Ping-Hsuan Hsieh, Seongwon Kim, Jae-sun Seo, Robert K. Montoye, Leland Chang, José A. Tierno, Daniel J. Friedman	A 0.1pJ/b 5-to-10Gb/s charge-recycling stacked low-power I/O for on-chip signaling in 45nm CMOS SOI.	ISSCC	2013	DBLP DOI BibTeX RDF
13	Benjamin Moss, Chen Sun 0003, Michael Georgas, Jeffrey Shainline, Jason Orcutt, Jonathan C. Leu, Mark T. Wade, Yu-Hsin Chen, Kareem Nammari, Xiaoxi Wang, Hanqing Li, Rajeev J. Ram, Milos A. Popovic, Vladimir Stojanovic	A 1.23pJ/b 2.5Gb/s monolithically integrated optical carrier-injection ring modulator and all-digital driver circuit in commercial 45nm SOI.	ISSCC	2013	DBLP DOI BibTeX RDF
13	Binjie Cheng, Xingsheng Wang, Andrew R. Brown, Jente B. Kuang, Dave Reid, Campbell Millar, Sani R. Nassif, Asen Asenov	SRAM device and cell co-design considerations in a 14nm SOI FinFET technology.	ISCAS	2013	DBLP DOI BibTeX RDF
13	Benjamin Wohlfeil, Christos Stamatiadis, Lars Zimmermann, Klaus Petermann	Compact fiber grating coupler on SOI for coupling of higher order fiber modes.	OFC/NFOEC	2013	DBLP BibTeX RDF
13	Jonathan E. Proesel, Benjamin G. Lee, Christian W. Baks, Clint L. Schow	35-Gb/s VCSEL-Based optical link using 32-nm SOI CMOS circuits.	OFC/NFOEC	2013	DBLP BibTeX RDF
13	Xuebei Yang, Aydin Babakhani	Optical waveguides and photodiodes in 0.18µm CMOS SOI with no post-processing.	OFC/NFOEC	2013	DBLP BibTeX RDF
13	Guillaume Moritz, Bastien Giraud, Jean-Philippe Noel, David Turgis, Anuj Grover	Optimization of a voltage sense amplifier operating in ultra wide voltage range with back bias design techniques in 28nm UTBB FD-SOI technology.	ICICDT	2013	DBLP DOI BibTeX RDF
13	Vita Pi-Ho Hu, Ming-Long Fan, Pin Su, Ching-Te Chuang	Device design and analysis of logic circuits and SRAMs for Germanium FinFETs on SOI and bulk substrates.	ISQED	2013	DBLP DOI BibTeX RDF
13	Xinliang Zhang, Jianji Dong, Sisi Tan, Dexiu Huang	All-optical analog signal processing technologies with SOI-based microring resonators.	ICAIT	2013	DBLP DOI BibTeX RDF
13	Guoli Li, Yun Zeng, Wei Hu, Yu Xia, Wei Peng	Modeling and Electrical Simulations of Thin-Film Gated SOI Lateral PIN Photodetectors for High Sensitivity and Speed Performances.	NCCET	2013	DBLP DOI BibTeX RDF
13	Mariusz Jankowski, Andrzej Napieralski	High input- and output-impedance functionality implementation in HV soi voltage buffers.	MIXDES	2013	DBLP BibTeX RDF