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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 908 occurrences of 401 keywords
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Results
Found 1076 publication records. Showing 1076 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
9 | Lars Gesellensetter, Sabine Glesner, Elke Salecker |
Formal Verification with Isabelle/HOL in Practice: Finding a Bug in the GCC Scheduler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMICS ![In: Formal Methods for Industrial Critical Systems, 12th International Workshop, FMICS 2007, Berlin, Germany, July 1-2, 2007, Revised Selected Papers, pp. 85-100, 2007, Springer, 978-3-540-79706-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Yong Li 0006, Zhiying Wang 0003, Xue-mi Zhao, Jian Ruan, Kui Dai |
Design of a Low-Power Embedded Processor Architecture Using Asynchronous Function Units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 12th Asia-Pacific Conference, ACSAC 2007, Seoul, Korea, August 23-25, 2007, Proceedings, pp. 354-363, 2007, Springer, 978-3-540-74308-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Kingshuk Karuri, Anupam Chattopadhyay, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr |
Increasing data-bandwidth to instruction-set extensions through register clustering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 166-171, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Tobias Nopper, Christoph Scholl 0001, Bernd Becker 0001 |
Computation of minimal counterexamples by using black box techniques and symbolic methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 273-280, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Nelson Yen-Chung Chang, Ting-Min Lin, Tsung-Hsien Tsai, Yu-Cheng Tseng, Tian-Sheuan Chang |
Real-Time DSP Implementation on Local Stereo Matching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICME ![In: Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, ICME 2007, July 2-5, 2007, Beijing, China, pp. 2090-2093, 2007, IEEE Computer Society, 1-4244-1017-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Klaus Gaedke, Malte Borsum, Marco Georgi, Andreas Kluger, Jean-Pierre Le Glanic, Pascal Bernard |
Architecture and VLSI Implementation of a programmable HD Real-Time Motion Estimator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1609-1612, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Paul Morgan, Richard Taylor |
ASIP Instruction Encoding for Energy and Area Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 797-800, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Paul Feautrier |
Scalable and Structured Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 34(5), pp. 459-487, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Structured scheduling, scalability, automatic parallelization |
9 | Mehrdad Reshadi, Nikil D. Dutt, Prabhat Mishra 0001 |
A retargetable framework for instruction-set architecture simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 5(2), pp. 431-452, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Retargetable instruction-set simulation, generic instruction model, instruction binary encoding, architecture description language, decode algorithm |
9 | Konstantinos Sarrigeorgidis, Jan M. Rabaey |
A Scalable Configurable Architecture for Advanced Wireless Communication Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 45(3), pp. 127-151, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
wireless communication algorithms, low power DSP architectures, SVD, QR, MIMO-OFDM |
9 | Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti |
An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSAMOS ![In: Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2006), Samos, Greece, July 17-20, 2006, pp. 115-122, 2006, IEEE, 1-4244-0155-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
9 | David Atienza, Praveen Raghavan, José L. Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo |
Compiler-Driven Leakage Energy Reduction in Banked Register Files. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006, Proceedings, pp. 107-116, 2006, Springer, 3-540-39094-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
9 | Ying Yi, Ioannis Nousias, Mark Milward, Sami Khawam, Tughrul Arslan, Iain Lindsay |
System-level scheduling on instruction cell based reconfigurable systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 381-386, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
9 | Christopher K. Lennard, Victor Berman, Saverio Fazzari, Mark A. Indovina, Cary Ussery, Marino Strik, John Wilson, Olivier Florent, François Rémond, Pierre Bricaud |
Industrially proving the SPIRIT consortium specifications for design chain integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE Designers' Forum ![In: Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 142-147, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-0-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
9 | Aaron Smith, Ramadass Nagarajan, Karthikeyan Sankaralingam, Robert G. McDonald, Doug Burger, Stephen W. Keckler, Kathryn S. McKinley |
Dataflow Predication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 9-13 December 2006, Orlando, Florida, USA, pp. 89-102, 2006, IEEE Computer Society, 0-7695-2732-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
9 | Tom Vander Aa, Murali Jayapala, Henk Corporaal, Francky Catthoor, Geert Deconinck |
Instruction Transfer And Storage Exploration for Low Energy VLIWs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada, pp. 292-297, 2006, IEEE, 1-4244-0382-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
9 | Hoseok Chang, Junho Cho, Wonyong Sung |
Performance Evaluation of an SIMD Architecture with a Multi-bank Vector Memory Unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada, pp. 71-76, 2006, IEEE, 1-4244-0382-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
9 | Koen Van Renterghem, Dieter Verhulst, S. Verschuere, Pieter Demuytere, Jan Vandewege, Xing-Zhi Qiu |
A Scalable Network ASIP Enabling Flow Awareness in Ethernet Access. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-4, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
9 | Jianying Peng, Xing Qin, Jian Yang 0015, Xiaolang Yan, Xiexiong Chen |
A Programmable Bitstream Parser for Multiple Video Coding Standards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICIC (3) ![In: First International Conference on Innovative Computing, Information and Control (ICICIC 2006), 30 August - 1 September 2006, Beijing, China, pp. 609-612, 2006, IEEE Computer Society, 0-7695-2616-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
9 | Jie Guo 0007, Torsten Limberg, Emil Matús, Björn Mennenga, Reimund Klemm, Gerhard P. Fettweis |
Code Generation for STA Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28 - September 1, 2006, Proceedings, pp. 299-310, 2006, Springer, 3-540-37783-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
9 | Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania |
Fuzzy decision making in embedded system design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 223-228, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
pareto-set reduction, clustering, decision making, multi-objective optimization |
9 | Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Yutaka Ota, Nobu Matsumoto, Masaki Nakagawa |
Pack instruction generation for media pUsing multi-valued decision diagram. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 154-159, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
multi-valued decision diagram, SIMD instructions |
9 | Jie Guo 0007, Gleb Belov, Gerhard P. Fettweis |
A Basic Data Routing Model for a Coarse-Grain Reconfigurable Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures and Applications, Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006, Revised Selected Papers, pp. 419-424, 2006, Springer. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
9 | Samuel Williams 0001, John Shalf, Leonid Oliker, Shoaib Kamil 0001, Parry Husbands, Katherine A. Yelick |
The potential of the cell processor for scientific computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the Third Conference on Computing Frontiers, 2006, Ischia, Italy, May 3-5, 2006, pp. 9-20, 2006, ACM, 1-59593-302-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
GEMM, SpMV, three level memory, FFT, sparse matrix, cell processor, stencil |
9 | Soumyajit Dey, Susmit Biswas, Arijit Mukhopadhyay, Anupam Basu |
An Approach to Architectural Enhancement for Embedded Speech Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 19th International Conference on VLSI Design (VLSI Design 2006), 3-7 January 2006, Hyderabad, India, pp. 371-376, 2006, IEEE Computer Society, 0-7695-2502-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
9 | Iyad Al Khatib, Francesco Poletti, Davide Bertozzi, Luca Benini, Mohamed Bechara, Hasan Khalifeh, Axel Jantsch, Rustam Nabiev |
A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: architectural design space exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 125-130, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
hardware space exploration, embedded system design, multiprocessor system-on-chip, real-time analysis, electrocardiogram algorithms |
9 | Yu-Kuen Lai, Gregory T. Byrd |
Stream-Based Implementation of Hash Functions for Multi-Gigabit Message Authentication Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDCAT ![In: Seventh International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2006), 4-7 December 2006, Taipei, Taiwan, pp. 150-155, 2006, IEEE Computer Society, 0-7695-2736-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
9 | H. C. Wang, C. K. Yuen |
A general framework to build new CPUs by mapping abstract machine code to instruction level parallel execution hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 33(4), pp. 113-120, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | Sid Ahmed Ali Touati |
Register Saturation in Instruction Level Parallelism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 33(4), pp. 393-449, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Register requirement, instruction level parallelism, integer linear programming, optimizing compilation, register pressure |
9 | Harm Peters, Ramanathan Sethuraman, Aleksandar Beric, Patrick Meuwissen, Srinivasan Balakrishnan, Carlos A. Alba Pinto, W. M. Kruijtzer, Fabian Ernst, Ghiath Alkadi, Jef L. van Meerbergen, Gerard de Haan |
Application Specific Instruction-Set Processor Template for Motion Estimation in Video Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. Video Technol. ![In: IEEE Trans. Circuits Syst. Video Technol. 15(4), pp. 508-527, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | Hans-Joachim Stolberg, Mladen Berekovic, Peter Pirsch |
A Platform-Independent Methodology for Performance Estimation of Multimedia Signal Processing Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 41(2), pp. 139-151, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
multimedia signal processing, bitstream analysis, complexity, MPEG-4, performance estimation, digital signal processor |
9 | Ruby B. Lee, A. Murat Fiskiran |
PLX: An Instruction Set Architecture and Testbed for Multimedia Information Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 40(1), pp. 85-108, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
multimedia, processor architecture, instruction set architecture, media processing, ISA |
9 | Tohru Ishihara, Farzan Fallah |
A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 358-363, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | Jie S. Hu, Feihui Li, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin |
Compiler-Directed Instruction Duplication for Soft Error Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 1056-1057, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | Mark G. Arnold |
Approximating Trigonometric Functions with the Laws of Sines and Cosines using the Logarithmic Number System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August - 3 September 2005, Porto, Portugal, pp. 48-55, 2005, IEEE Computer Society, 0-7695-2433-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | Jan-Willem van de Waerdt, Stamatis Vassiliadis, Sanjeev Das, Sebastian Mirolo, Chris Yen, Bill Zhong, Carlos Basto, Jean-Paul van Itegem, Dinesh Amirtharaj, Kulbhushan Kalra, Pedro Rodriguez, Hans Van Antwerpen |
The TM3270 Media-Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 12-16 November 2005, Barcelona, Spain, pp. 331-342, 2005, IEEE Computer Society, 0-7695-2440-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | Masatoshi Shima 0001 |
The Birth, Evolution and Future of the Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIT ![In: Fifth International Conference on Computer and Information Technology (CIT 2005), 21-23 September 2005, Shanghai, China, pp. 2, 2005, IEEE Computer Society, 0-7695-2432-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | Mario Schölzel, Peter Bachmann |
DESCOMP: A New Design Space Exploration Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Systems Aspects in Organic and Pervasive Computing - ARCS 2005, 18th International Conference on Architecture of Computing Systems, Innsbruck, Austria, March 14-17, 2005, Proceedings, pp. 178-192, 2005, Springer, 3-540-25273-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | Antonio Carlos Schneider Beck, Luigi Carro |
Application of Binary Translation to Java Reconfigurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, 2005, IEEE Computer Society, 0-7695-2312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | Claudio Mucci, Fabio Campi, Antonio Deledda, Alberto Fazzi, Mirco Ferri, Massimo Bocchi |
A Cycle-Accurate ISS for a Dynamically Reconfigurable Processor Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, 2005, IEEE Computer Society, 0-7695-2312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | Xiushan Feng, Alan J. Hu |
Cutpoints for formal equivalence verification of embedded software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMSOFT ![In: EMSOFT 2005, September 18-22, 2005, Jersey City, NJ, USA, 5th ACM International Conference On Embedded Software, Proceedings, pp. 307-316, 2005, ACM, 1-59593-091-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
formal verification, embedded software, equivalence checking |
9 | Yu Hu 0016, Qing Li 0001, C.-C. Jay Kuo |
Run-Time Power Consumption Modeling for Embedded Multimedia Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2005), 17-19 August 2005, Hong Kong, China, pp. 353-356, 2005, IEEE Computer Society, 0-7695-2346-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | Chih-wen Hsueh, Tien-Fu Chen, Rong-Guey Chang, Shi-Wu Lo |
Development of Architecture and Software Technologies in High-Performance Low-Power SoC Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2005), 17-19 August 2005, Hong Kong, China, pp. 475-480, 2005, IEEE Computer Society, 0-7695-2346-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Tool Chain, Architecture, Compiler, System-on-Chip, Real-Time Operating System |
9 | Hong Yue, Ming-che Lai, Kui Dai, Zhiying Wang 0003 |
Design of a Configurable Embedded Processor Architecture for DSP Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS (2) ![In: 11th International Conference on Parallel and Distributed Systems, ICPADS 2005, Fuduoka, Japan, July 20-22, 2005, pp. 27-31, 2005, IEEE Computer Society, 0-7695-2281-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | Naohiro Ishii, Hiroaki Ogi, Tsubasa Mochizuki, Kazunori Iwata 0001 |
Parallelism Improvements of Software Pipelining by Combining Spilling with Rematerialization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KES (1) ![In: Knowledge-Based Intelligent Information and Engineering Systems, 9th International Conference, KES 2005, Melbourne, Australia, September 14-16, 2005, Proceedings, Part I, pp. 820-826, 2005, Springer, 3-540-28894-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | Oliver Schliebusch, Anupam Chattopadhyay, Ernst Martin Witte, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr |
Optimization Techniques for ADL-Driven RTL Processor Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 8-10 June 2005, Montreal, Canada, pp. 165-171, 2005, IEEE Computer Society, 0-7695-2361-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | Mehrdad Reshadi, Bita Gorjiara, Daniel D. Gajski |
Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 69-76, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | Ernst Martin Witte, Anupam Chattopadhyay, Oliver Schliebusch, David Kammler |
Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 193-199, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | Jan-Willem van de Waerdt, Stamatis Vassiliadis |
Instruction Set Architecture Enhancements for Video Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2005), 23-25 July 2005, Samos, Greece, pp. 146-153, 2005, IEEE Computer Society, 0-7695-2407-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | Mohammad Mostafizur Rahman Mozumdar, Kingshuk Karuri, Anupam Chattopadhyay, Stefan Kraemer, Hanno Scharwächter, Heinrich Meyr, Gerd Ascheid, Rainer Leupers |
Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2005), 23-25 July 2005, Samos, Greece, pp. 154-160, 2005, IEEE Computer Society, 0-7695-2407-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | A. Murat Fiskiran, Ruby B. Lee |
On-Chip Lookup Tables for Fast Symmetric-Key Encryption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 16th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2005), 23-25 July 2005, Samos, Greece, pp. 356-363, 2005, IEEE Computer Society, 0-7695-2407-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | A. Murat Fiskiran, Ruby B. Lee |
Fast Parallel Table Lookups to Accelerate Symmetric-Key Cryptography. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITCC (1) ![In: International Symposium on Information Technology: Coding and Computing (ITCC 2005), Volume 1, 4-6 April 2005, Las Vegas, Nevada, USA, pp. 526-531, 2005, IEEE Computer Society, 0-7695-2315-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | Aleksandar Beric, Ramanathan Sethuraman, Jef L. van Meerbergen, Gerard de Haan |
Memory-Centric Motion Estimator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 816-819, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | Nerina Bermudo, Andreas Krall, R. Nigel Horspool |
Control Flow Graph Reconstruction for Assembly Language Programs with Delayed Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCAM ![In: 5th IEEE International Workshop on Source Code Analysis and Manipulation (SCAM 2005), 30 September - 1 October 2005, Budapest, Hungary, pp. 107-118, 2005, IEEE Computer Society, 0-7695-2290-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | Shorin Kyo, Shin'ichiro Okazaki, Tamio Arai |
An Integrated Memory Array Processor Architecture for Embedded Image Recognition Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 32st International Symposium on Computer Architecture (ISCA 2005), 4-8 June 2005, Madison, Wisconsin, USA, pp. 134-145, 2005, IEEE Computer Society, 978-0-7695-2270-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | Antonio Carlos Schneider Beck, Luigi Carro |
Dynamic reconfiguration with binary translation: breaking the ILP barrier with software compatibility. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 732-737, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
java, power consumption, binary translation, reconfigurable processors |
9 | Bruce R. Childers, Jack W. Davidson |
Custom Wide Counterflow Pipelines for High-Performance Embedded Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 53(2), pp. 141-158, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Counterflow pipelines, automatic architectural synthesis, application-specific processors |
9 | Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar |
An efficient technique for exploring register file size in ASIP design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(12), pp. 1693-1699, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
9 | Stéphane Chevobbe, Nicolas Ventroux, Frédéric Blanc 0001, Thierry Collette |
RAMPASS: Reconfigurable and Advanced Multi-processing Architecture for Future Silicon Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Computer Systems: Architectures, Modeling, and Simulation, Third and Fourth International Workshops, SAMOS 2003 and SAMOS 2004, Samos, Greece, July 21-23, 2003 and July 19-21, 2004, Proceedings, pp. 20-29, 2004, Springer, 3-540-22377-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
9 | Paul Feautrier |
Scalable and Modular Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Computer Systems: Architectures, Modeling, and Simulation, Third and Fourth International Workshops, SAMOS 2003 and SAMOS 2004, Samos, Greece, July 21-23, 2003 and July 19-21, 2004, Proceedings, pp. 433-442, 2004, Springer, 3-540-22377-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
9 | Prabhat Mishra 0001, Nikil D. Dutt, Yaron Kashai |
Functional Verification of Pipelined Processors: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), Common Challenges and Solutions, 08-10 September 2004, Austin, Texas, USA, pp. 79-84, 2004, IEEE Computer Society, 0-7695-2320-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
9 | Eric Senn, Johann Laurent, Nathalie Julien, Eric Martin 0001 |
SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 342-351, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
9 | Zhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vissers |
A quantitative analysis of the speedup factors of FPGAs over processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 162-170, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
performance, FPGA, analysis, VHDL, reconfigurable computing |
9 | Murali Jayapala, Tom Vander Aa, Francisco Barat, Geert Deconinck, Francky Catthoor, Henk Corporaal |
L0 buffer energy optimization through scheduling and exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2004 ACM Symposium on Applied Computing (SAC), Nicosia, Cyprus, March 14-17, 2004, pp. 905-906, 2004, ACM, 1-58113-812-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
9 | Mikhail Smelyanskiy, Scott A. Mahlke, Edward S. Davidson |
Probabilistic Predicate-Aware Modulo Scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: 2nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2004), 20-24 March 2004, San Jose, CA, USA, pp. 151-162, 2004, IEEE Computer Society, 0-7695-2102-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
9 | Jens Braunes, Steffen Köhler, Rainer G. Spallek |
RECAST: An Evaluation Framework for Coarse-Grain Reconfigurable Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Organic and Pervasive Computing - ARCS 2004, International Conference on Architecture of Computing Systems, Augsburg, Germany, March 23-26, 2004, Proceedings, pp. 156-166, 2004, Springer, 3-540-21238-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
9 | Miroslav N. Velev |
Using positive equality to prove liveness for pipelined microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 316-321, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
9 | Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Francky Catthoor, Henk Corporaal |
Instruction buffering exploration for low energy VLIWs with instruction clusters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 824-829, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
9 | Gerardo Bandera, Mario A. González, Julio Villalba, Javier Hormigo, Emilio L. Zapata |
Evaluation of Elementary Functions Using Multimedia Features. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM / Abstracts Proceedings, 26-30 April 2004, Santa Fe, New Mexico, USA, 2004, IEEE Computer Society, 0-7695-2132-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
9 | Andy Lambrechts, Tom Vander Aa, Murali Jayapala, Guillermo Talavera, Anthony Leroy, Adelina Shickova, Francisco Barat, Bingfeng Mei, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Corporaal, Frédéric Robert, Jordi Carrabina Bordoll |
Design Style Case Study for Embedded Multi Media Compute Nodes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTSS ![In: Proceedings of the 25th IEEE Real-Time Systems Symposium (RTSS 2004), 5-8 December 2004, Lisbon, Portugal, pp. 104-113, 2004, IEEE Computer Society, 0-7695-2247-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
9 | Steve Carr 0001, Philip H. Sweany |
Automatic data partitioning for the agere payload plus network processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2004 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2004, Washington DC, USA, September 22 - 25, 2004, pp. 238-247, 2004, ACM, 1-58113-890-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
scheduling, partitioning, network processors |
9 | Zili Shao, Qingfeng Zhuge, Meilin Liu, Bin Xiao 0001, Edwin Hsing-Mean Sha |
Switching-Activity Minimization on Instruction-Level Loop Scheduling for VLIWDSP Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 15th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2004), 27-29 September 2004, Galveston, TX, USA, pp. 224-234, 2004, IEEE Computer Society, 0-7695-2226-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
9 | Ganesh Yadav, R. K. Singh, Vipin Chaudhary |
On Implementation of MPEG-2 Like Real-Time Parallel Media Applications on MDSP SoC Cradle Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC ![In: Embedded and Ubiquitous Computing, International Conference EUC 2004, Aizu-Wakamatsu City, Japan, August 25-27, 2004, Proceedings, pp. 281-290, 2004, Springer, 3-540-22906-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
9 | Miroslav N. Velev |
Efficient formal verification of pipelined processors with instruction queues. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 92-95, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
logic of equality, positive equality, decomposition, SAT |
9 | Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen |
A compact DSP core with static floating-point unit & its microcode generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 57-60, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
DSP core, digital signal processor, floating-point units |
9 | Aleksandar Beric, Ramanathan Sethuraman, Harm Peters, Jef L. van Meerbergen, Gerard de Haan, Carlos A. Alba Pinto |
A 27 mW 1.1 mm2 Motion Estimator for Picture-Rate Up-converter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 17th International Conference on VLSI Design (VLSI Design 2004), with the 3rd International Conference on Embedded Systems Design, 5-9 January 2004, Mumbai, India, pp. 1083-, 2004, IEEE Computer Society, 0-7695-2072-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
9 | Philip Brisk, Adam Kaplan, Majid Sarrafzadeh |
Area-efficient instruction set synthesis for reconfigurable system-on-chip designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 395-400, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
field-programmable gate array (FPGA), compiler, resource sharing, integer linear programming (ILP) |
9 | Christoforos E. Kozyrakis, David A. Patterson 0001 |
Scalable Vector Processors for Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 23(6), pp. 36-45, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
9 | Kazuaki Ishizaki, Mikio Takeuchi, Kiyokuni Kawachiya, Toshio Suganuma, Osamu Gohda, Tatsushi Inagaki, Akira Koseki, Kazunori Ogata, Motohiro Kawahito, Toshiaki Yasue, Takeshi Ogasawara, Tamiya Onodera, Hideaki Komatsu, Toshio Nakatani |
Effectiveness of cross-platform optimizations for a java just-in-time compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OOPSLA ![In: Proceedings of the 2003 ACM SIGPLAN Conference on Object-Oriented Programming Systems, Languages and Applications, OOPSLA 2003, October 26-30, 2003, Anaheim, CA, USA, pp. 187-204, 2003, ACM, 1-58113-712-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Java, optimization, just-in-time compiler |
9 | Andrea Lodi 0002, Mario Toma, Fabio Campi |
A pipelined configurable gate array for embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 21-30, 2003, ACM, 1-58113-651-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
FPGA, pipeline, energy, reconfigurable processor |
9 | James C. Dehnert, Brian Grant, John P. Banning, Richard Johnson, Thomas Kistler, Alexander Klaiber, Jim Mattson |
The Transmeta Code Morphing - Software: Using Speculation, Recovery, and Adaptive Retranslation to Address Real-Life Challenges. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CGO ![In: 1st IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2003), 23-26 March 2003, San Francisco, CA, USA, pp. 15-24, 2003, IEEE Computer Society, 0-7695-1913-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
9 | Oliver Wahlen, Manuel Hohenauer, Gunnar Braun, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Xiaoning Nie |
Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SCOPES ![In: Software and Compilers for Embedded Systems, 7th International Workshop, SCOPES 2003, Vienna, Austria, September 24-26, 2003, Proceedings, pp. 167-181, 2003, Springer, 3-540-20145-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
9 | Fabio Campi, Andrea Cappelli, Roberto Guerrieri, Andrea Lodi 0002, Mario Toma, Alberto La Rosa, Luciano Lavagno, Claudio Passerone, Roberto Canegallo |
A Reconfigurable Processor Architecture and Software Development Environment for Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings, pp. 171, 2003, IEEE Computer Society, 0-7695-1926-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
9 | Mehrdad Reshadi, Nikhil Bansal 0003, Prabhat Mishra 0001, Nikil D. Dutt |
An efficient retargetable framework for instruction-set simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003, Newport Beach, CA, USA, October 1-3, 2003, pp. 13-18, 2003, ACM, 1-58113-742-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
generic instruction model, instruction binary encoding, retargetable instruction-set simulation, architecture description language, decode algorithm |
9 | Michael L. Chu, Kevin Fan, Scott A. Mahlke |
Region-based hierarchical operation partitioning for multicluster processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the ACM SIGPLAN 2003 Conference on Programming Language Design and Implementation 2003, San Diego, California, USA, June 9-11, 2003, pp. 300-311, 2003, ACM, 1-58113-662-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
multicluster processor, operation partitioning, clustering, instruction-level parallelism, instruction scheduling, region-based compilation |
9 | Miroslav N. Velev |
Automatic Abstraction of Equations in a Logic of Equality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TABLEAUX ![In: Automated Reasoning with Analytic Tableaux and Related Methods, International Conference, TABLEAUX 2003, Rome, Italy, September 9-12, 2003. Proceedings, pp. 196-213, 2003, Springer, 3-540-40787-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
9 | Afshin Abdollahi, Massoud Pedram, Farzan Fallah, Indradeep Ghosh |
Precomputation-based Guarding for Dynamic and Leakage Power Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 90-97, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
9 | Guido Bertoni, A. Bircan, Luca Breveglieri, Pasqualina Fragneto, Marco Macchetti, Vittorio Zaccaria |
About the performances of the Advanced Encryption Standard in embedded systems with cache memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 145-148, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
9 | Christian Panis, Raimund Leitner, Herbert Grünbacher, Jari Nurmi |
xLIW - a scaleable long instruction word. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 69-72, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
9 | Kevin Fan, Nathan Clark, Michael L. Chu, K. V. Manjunath, Rajiv A. Ravindran, Mikhail Smelyanskiy, Scott A. Mahlke |
Systematic Register Bypass Customization for Application-Specific Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 14th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2003), 24-26 June 2003, The Hague, The Netherlands, pp. 64-74, 2003, IEEE Computer Society, 0-7695-1992-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
9 | Vinod Kathail, Shail Aditya, Robert Schreiber, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman |
PICO: Automatically Designing Custom Computers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Computer ![In: Computer 35(9), pp. 39-47, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Sebastian Unger, Frank Mueller 0001 |
Handling irreducible loops: optimized node splitting versus DJ-graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 24(4), pp. 299-333, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
irreducible flowgraphs, reducible flowgraphs, compilation, instruction-level parallelism, Code optimization, loops, control flow graphs, node splitting |
9 | Oliver Wahlen, Tilman Glökler, Achim Nohl, Andreas Hoffmann 0002, Rainer Leupers, Heinrich Meyr |
Application specific compiler/architecture codesign: a case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES-SCOPES ![In: Proceedings of the 2002 Joint Conference on Languages, Compilers, and Tools for Embedded Systems & Software and Compilers for Embedded Systems (LCTES'02-SCOPES'02), Berlin, Germany, 19-21 June 2002, pp. 185-193, 2002, ACM, 1-58113-527-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
ASIP, architecture exploration, retargetable compiler |
9 | Alex Aletà, Josep M. Codina, F. Jesús Sánchez, Antonio González 0001, David R. Kaeli |
Exploiting Pseudo-Schedules to Guide Data Dependence Graph Partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 22-25 September 2002, Charlottesville, VA, USA, pp. 281-290, 2002, IEEE Computer Society, 0-7695-1620-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Chunhong Chen, Majid Sarrafzadeh |
Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 1016-1020, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Mohamed M. Zahran, Manoj Franklin |
A Feasibility Study of Hierarchical Multithreading. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 15-19 April 2002, Fort Lauderdale, FL, USA, CD-ROM/Abstracts Proceedings, 2002, IEEE Computer Society, 0-7695-1573-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Satoshi Matsushita |
Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan, pp. 103-108, 2002, ACM / IEEE Computer Society, 1-58113-576-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
deign experience, CMP, chip multiprocessor, functional verification, speculative multithreading |
9 | Giuseppe Desoli, Nikolay Mateev, Evelyn Duesterwald, Paolo Faraboschi, Josh Fisher |
A New Facility for Dynamic Control of Program Execution: DELI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMSOFT ![In: Embedded Software, Second International Conference, EMSOFT 2002, Grenoble, France, October 7-9, 2002, Proceedings, pp. 305-318, 2002, Springer, 3-540-44307-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Lori Carter, Brad Calder |
Using predicate path information in hardware to determine true dependences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 16th international conference on Supercomputing, ICS 2002, New York City, NY, USA, June 22-26, 2002, pp. 230-240, 2002, ACM, 1-58113-483-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
dependence analysis, predicated execution, path analysis |
9 | Julio Villalba, Gerardo Bandera, Mario A. González, Javier Hormigo, Emilio L. Zapata |
Polynomial Evaluation on Multimedia Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 13th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2002), 17-19 July 2002, San Jose, CA, USA, pp. 265-, 2002, IEEE Computer Society, 0-7695-1712-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
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