Search results for "VLIW"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
9	Lars Gesellensetter, Sabine Glesner, Elke Salecker	Formal Verification with Isabelle/HOL in Practice: Finding a Bug in the GCC Scheduler.	FMICS	2007	DBLP DOI BibTeX RDF
9	Yong Li 0006, Zhiying Wang 0003, Xue-mi Zhao, Jian Ruan, Kui Dai	Design of a Low-Power Embedded Processor Architecture Using Asynchronous Function Units.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF
9	Kingshuk Karuri, Anupam Chattopadhyay, Manuel Hohenauer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr	Increasing data-bandwidth to instruction-set extensions through register clustering.	ICCAD	2007	DBLP DOI BibTeX RDF
9	Tobias Nopper, Christoph Scholl 0001, Bernd Becker 0001	Computation of minimal counterexamples by using black box techniques and symbolic methods.	ICCAD	2007	DBLP DOI BibTeX RDF
9	Nelson Yen-Chung Chang, Ting-Min Lin, Tsung-Hsien Tsai, Yu-Cheng Tseng, Tian-Sheuan Chang	Real-Time DSP Implementation on Local Stereo Matching.	ICME	2007	DBLP DOI BibTeX RDF
9	Klaus Gaedke, Malte Borsum, Marco Georgi, Andreas Kluger, Jean-Pierre Le Glanic, Pascal Bernard	Architecture and VLSI Implementation of a programmable HD Real-Time Motion Estimator.	ISCAS	2007	DBLP DOI BibTeX RDF
9	Paul Morgan, Richard Taylor	ASIP Instruction Encoding for Energy and Area Reduction.	DAC	2007	DBLP DOI BibTeX RDF
9	Paul Feautrier	Scalable and Structured Scheduling.	Int. J. Parallel Program.	2006	DBLP DOI BibTeX RDF	Structured scheduling, scalability, automatic parallelization
9	Mehrdad Reshadi, Nikil D. Dutt, Prabhat Mishra 0001	A retargetable framework for instruction-set architecture simulation.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	Retargetable instruction-set simulation, generic instruction model, instruction binary encoding, architecture description language, decode algorithm
9	Konstantinos Sarrigeorgidis, Jan M. Rabaey	A Scalable Configurable Architecture for Advanced Wireless Communication Algorithms.	J. VLSI Signal Process.	2006	DBLP DOI BibTeX RDF	wireless communication algorithms, low power DSP architectures, SVD, QR, MIMO-OFDM
9	Giuseppe Ascia, Vincenzo Catania, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti	An Efficent Hierachical Fuzzy Approach for System Level System-on-a-Chip Design.	ICSAMOS	2006	DBLP DOI BibTeX RDF
9	David Atienza, Praveen Raghavan, José L. Ayala, Giovanni De Micheli, Francky Catthoor, Diederik Verkest, Marisa López-Vallejo	Compiler-Driven Leakage Energy Reduction in Banked Register Files.	PATMOS	2006	DBLP DOI BibTeX RDF
9	Ying Yi, Ioannis Nousias, Mark Milward, Sami Khawam, Tughrul Arslan, Iain Lindsay	System-level scheduling on instruction cell based reconfigurable systems.	DATE	2006	DBLP DOI BibTeX RDF
9	Christopher K. Lennard, Victor Berman, Saverio Fazzari, Mark A. Indovina, Cary Ussery, Marino Strik, John Wilson, Olivier Florent, François Rémond, Pierre Bricaud	Industrially proving the SPIRIT consortium specifications for design chain integration.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
9	Aaron Smith, Ramadass Nagarajan, Karthikeyan Sankaralingam, Robert G. McDonald, Doug Burger, Stephen W. Keckler, Kathryn S. McKinley	Dataflow Predication.	MICRO	2006	DBLP DOI BibTeX RDF
9	Tom Vander Aa, Murali Jayapala, Henk Corporaal, Francky Catthoor, Geert Deconinck	Instruction Transfer And Storage Exploration for Low Energy VLIWs.	SiPS	2006	DBLP DOI BibTeX RDF
9	Hoseok Chang, Junho Cho, Wonyong Sung	Performance Evaluation of an SIMD Architecture with a Multi-bank Vector Memory Unit.	SiPS	2006	DBLP DOI BibTeX RDF
9	Koen Van Renterghem, Dieter Verhulst, S. Verschuere, Pieter Demuytere, Jan Vandewege, Xing-Zhi Qiu	A Scalable Network ASIP Enabling Flow Awareness in Ethernet Access.	FPL	2006	DBLP DOI BibTeX RDF
9	Jianying Peng, Xing Qin, Jian Yang 0015, Xiaolang Yan, Xiexiong Chen	A Programmable Bitstream Parser for Multiple Video Coding Standards.	ICICIC (3)	2006	DBLP DOI BibTeX RDF
9	Jie Guo 0007, Torsten Limberg, Emil Matús, Björn Mennenga, Reimund Klemm, Gerhard P. Fettweis	Code Generation for STA Architecture.	Euro-Par	2006	DBLP DOI BibTeX RDF
9	Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti, Giuseppe Ascia, Vincenzo Catania	Fuzzy decision making in embedded system design.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	pareto-set reduction, clustering, decision making, multi-objective optimization
9	Hiroaki Tanaka, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai, Yutaka Ota, Nobu Matsumoto, Masaki Nakagawa	Pack instruction generation for media pUsing multi-valued decision diagram.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	multi-valued decision diagram, SIMD instructions
9	Jie Guo 0007, Gleb Belov, Gerhard P. Fettweis	A Basic Data Routing Model for a Coarse-Grain Reconfigurable Hardware.	ARC	2006	DBLP DOI BibTeX RDF
9	Samuel Williams 0001, John Shalf, Leonid Oliker, Shoaib Kamil 0001, Parry Husbands, Katherine A. Yelick	The potential of the cell processor for scientific computing.	Conf. Computing Frontiers	2006	DBLP DOI BibTeX RDF	GEMM, SpMV, three level memory, FFT, sparse matrix, cell processor, stencil
9	Soumyajit Dey, Susmit Biswas, Arijit Mukhopadhyay, Anupam Basu	An Approach to Architectural Enhancement for Embedded Speech Applications.	VLSI Design	2006	DBLP DOI BibTeX RDF
9	Iyad Al Khatib, Francesco Poletti, Davide Bertozzi, Luca Benini, Mohamed Bechara, Hasan Khalifeh, Axel Jantsch, Rustam Nabiev	A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: architectural design space exploration.	DAC	2006	DBLP DOI BibTeX RDF	hardware space exploration, embedded system design, multiprocessor system-on-chip, real-time analysis, electrocardiogram algorithms
9	Yu-Kuen Lai, Gregory T. Byrd	Stream-Based Implementation of Hash Functions for Multi-Gigabit Message Authentication Codes.	PDCAT	2006	DBLP DOI BibTeX RDF
9	H. C. Wang, C. K. Yuen	A general framework to build new CPUs by mapping abstract machine code to instruction level parallel execution hardware.	SIGARCH Comput. Archit. News	2005	DBLP DOI BibTeX RDF
9	Sid Ahmed Ali Touati	Register Saturation in Instruction Level Parallelism.	Int. J. Parallel Program.	2005	DBLP DOI BibTeX RDF	Register requirement, instruction level parallelism, integer linear programming, optimizing compilation, register pressure
9	Harm Peters, Ramanathan Sethuraman, Aleksandar Beric, Patrick Meuwissen, Srinivasan Balakrishnan, Carlos A. Alba Pinto, W. M. Kruijtzer, Fabian Ernst, Ghiath Alkadi, Jef L. van Meerbergen, Gerard de Haan	Application Specific Instruction-Set Processor Template for Motion Estimation in Video Applications.	IEEE Trans. Circuits Syst. Video Technol.	2005	DBLP DOI BibTeX RDF
9	Hans-Joachim Stolberg, Mladen Berekovic, Peter Pirsch	A Platform-Independent Methodology for Performance Estimation of Multimedia Signal Processing Applications.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	multimedia signal processing, bitstream analysis, complexity, MPEG-4, performance estimation, digital signal processor
9	Ruby B. Lee, A. Murat Fiskiran	PLX: An Instruction Set Architecture and Testbed for Multimedia Information Processing.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	multimedia, processor architecture, instruction set architecture, media processing, ISA
9	Tohru Ishihara, Farzan Fallah	A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors.	DATE	2005	DBLP DOI BibTeX RDF
9	Jie S. Hu, Feihui Li, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin	Compiler-Directed Instruction Duplication for Soft Error Detection.	DATE	2005	DBLP DOI BibTeX RDF
9	Mark G. Arnold	Approximating Trigonometric Functions with the Laws of Sines and Cosines using the Logarithmic Number System.	DSD	2005	DBLP DOI BibTeX RDF
9	Jan-Willem van de Waerdt, Stamatis Vassiliadis, Sanjeev Das, Sebastian Mirolo, Chris Yen, Bill Zhong, Carlos Basto, Jean-Paul van Itegem, Dinesh Amirtharaj, Kulbhushan Kalra, Pedro Rodriguez, Hans Van Antwerpen	The TM3270 Media-Processor.	MICRO	2005	DBLP DOI BibTeX RDF
9	Masatoshi Shima 0001	The Birth, Evolution and Future of the Microprocessor.	CIT	2005	DBLP DOI BibTeX RDF
9	Mario Schölzel, Peter Bachmann	DESCOMP: A New Design Space Exploration Approach.	ARCS	2005	DBLP DOI BibTeX RDF
9	Antonio Carlos Schneider Beck, Luigi Carro	Application of Binary Translation to Java Reconfigurable Architectures.	IPDPS	2005	DBLP DOI BibTeX RDF
9	Claudio Mucci, Fabio Campi, Antonio Deledda, Alberto Fazzi, Mirco Ferri, Massimo Bocchi	A Cycle-Accurate ISS for a Dynamically Reconfigurable Processor Architecture.	IPDPS	2005	DBLP DOI BibTeX RDF
9	Xiushan Feng, Alan J. Hu	Cutpoints for formal equivalence verification of embedded software.	EMSOFT	2005	DBLP DOI BibTeX RDF	formal verification, embedded software, equivalence checking
9	Yu Hu 0016, Qing Li 0001, C.-C. Jay Kuo	Run-Time Power Consumption Modeling for Embedded Multimedia Systems.	RTCSA	2005	DBLP DOI BibTeX RDF
9	Chih-wen Hsueh, Tien-Fu Chen, Rong-Guey Chang, Shi-Wu Lo	Development of Architecture and Software Technologies in High-Performance Low-Power SoC Design.	RTCSA	2005	DBLP DOI BibTeX RDF	Tool Chain, Architecture, Compiler, System-on-Chip, Real-Time Operating System
9	Hong Yue, Ming-che Lai, Kui Dai, Zhiying Wang 0003	Design of a Configurable Embedded Processor Architecture for DSP Functions.	ICPADS (2)	2005	DBLP DOI BibTeX RDF
9	Naohiro Ishii, Hiroaki Ogi, Tsubasa Mochizuki, Kazunori Iwata 0001	Parallelism Improvements of Software Pipelining by Combining Spilling with Rematerialization.	KES (1)	2005	DBLP DOI BibTeX RDF
9	Oliver Schliebusch, Anupam Chattopadhyay, Ernst Martin Witte, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr	Optimization Techniques for ADL-Driven RTL Processor Synthesis.	IEEE International Workshop on Rapid System Prototyping	2005	DBLP DOI BibTeX RDF
9	Mehrdad Reshadi, Bita Gorjiara, Daniel D. Gajski	Utilizing Horizontal and Vertical Parallelism with a No-Instruction-Set Compiler for Custom Datapaths.	ICCD	2005	DBLP DOI BibTeX RDF
9	Ernst Martin Witte, Anupam Chattopadhyay, Oliver Schliebusch, David Kammler	Applying Resource Sharing Algorithms to ADL-driven Automatic ASIP Implementation.	ICCD	2005	DBLP DOI BibTeX RDF
9	Jan-Willem van de Waerdt, Stamatis Vassiliadis	Instruction Set Architecture Enhancements for Video Processing.	ASAP	2005	DBLP DOI BibTeX RDF
9	Mohammad Mostafizur Rahman Mozumdar, Kingshuk Karuri, Anupam Chattopadhyay, Stefan Kraemer, Hanno Scharwächter, Heinrich Meyr, Gerd Ascheid, Rainer Leupers	Instruction Set Customization of Application Specific Processors for Network Processing: A Case Study.	ASAP	2005	DBLP DOI BibTeX RDF
9	A. Murat Fiskiran, Ruby B. Lee	On-Chip Lookup Tables for Fast Symmetric-Key Encryption.	ASAP	2005	DBLP DOI BibTeX RDF
9	A. Murat Fiskiran, Ruby B. Lee	Fast Parallel Table Lookups to Accelerate Symmetric-Key Cryptography.	ITCC (1)	2005	DBLP DOI BibTeX RDF
9	Aleksandar Beric, Ramanathan Sethuraman, Jef L. van Meerbergen, Gerard de Haan	Memory-Centric Motion Estimator.	VLSI Design	2005	DBLP DOI BibTeX RDF
9	Nerina Bermudo, Andreas Krall, R. Nigel Horspool	Control Flow Graph Reconstruction for Assembly Language Programs with Delayed Instructions.	SCAM	2005	DBLP DOI BibTeX RDF
9	Shorin Kyo, Shin'ichiro Okazaki, Tamio Arai	An Integrated Memory Array Processor Architecture for Embedded Image Recognition Systems.	ISCA	2005	DBLP DOI BibTeX RDF
9	Antonio Carlos Schneider Beck, Luigi Carro	Dynamic reconfiguration with binary translation: breaking the ILP barrier with software compatibility.	DAC	2005	DBLP DOI BibTeX RDF	java, power consumption, binary translation, reconfigurable processors
9	Bruce R. Childers, Jack W. Davidson	Custom Wide Counterflow Pipelines for High-Performance Embedded Applications.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Counterflow pipelines, automatic architectural synthesis, application-specific processors
9	Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar	An efficient technique for exploring register file size in ASIP design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
9	Stéphane Chevobbe, Nicolas Ventroux, Frédéric Blanc 0001, Thierry Collette	RAMPASS: Reconfigurable and Advanced Multi-processing Architecture for Future Silicon Systems.	SAMOS	2004	DBLP DOI BibTeX RDF
9	Paul Feautrier	Scalable and Modular Scheduling.	SAMOS	2004	DBLP DOI BibTeX RDF
9	Prabhat Mishra 0001, Nikil D. Dutt, Yaron Kashai	Functional Verification of Pipelined Processors: A Case Study.	MTV	2004	DBLP DOI BibTeX RDF
9	Eric Senn, Johann Laurent, Nathalie Julien, Eric Martin 0001	SoftExplorer: Estimation, Characterization, and Optimization of the Power and Energy Consumption at the Algorithmic Level.	PATMOS	2004	DBLP DOI BibTeX RDF
9	Zhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vissers	A quantitative analysis of the speedup factors of FPGAs over processors.	FPGA	2004	DBLP DOI BibTeX RDF	performance, FPGA, analysis, VHDL, reconfigurable computing
9	Murali Jayapala, Tom Vander Aa, Francisco Barat, Geert Deconinck, Francky Catthoor, Henk Corporaal	L0 buffer energy optimization through scheduling and exploration.	SAC	2004	DBLP DOI BibTeX RDF
9	Mikhail Smelyanskiy, Scott A. Mahlke, Edward S. Davidson	Probabilistic Predicate-Aware Modulo Scheduling.	CGO	2004	DBLP DOI BibTeX RDF
9	Jens Braunes, Steffen Köhler, Rainer G. Spallek	RECAST: An Evaluation Framework for Coarse-Grain Reconfigurable Architectures.	ARCS	2004	DBLP DOI BibTeX RDF
9	Miroslav N. Velev	Using positive equality to prove liveness for pipelined microprocessors.	ASP-DAC	2004	DBLP DOI BibTeX RDF
9	Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Francky Catthoor, Henk Corporaal	Instruction buffering exploration for low energy VLIWs with instruction clusters.	ASP-DAC	2004	DBLP DOI BibTeX RDF
9	Gerardo Bandera, Mario A. González, Julio Villalba, Javier Hormigo, Emilio L. Zapata	Evaluation of Elementary Functions Using Multimedia Features.	IPDPS	2004	DBLP DOI BibTeX RDF
9	Andy Lambrechts, Tom Vander Aa, Murali Jayapala, Guillermo Talavera, Anthony Leroy, Adelina Shickova, Francisco Barat, Bingfeng Mei, Francky Catthoor, Diederik Verkest, Geert Deconinck, Henk Corporaal, Frédéric Robert, Jordi Carrabina Bordoll	Design Style Case Study for Embedded Multi Media Compute Nodes.	RTSS	2004	DBLP DOI BibTeX RDF
9	Steve Carr 0001, Philip H. Sweany	Automatic data partitioning for the agere payload plus network processor.	CASES	2004	DBLP DOI BibTeX RDF	scheduling, partitioning, network processors
9	Zili Shao, Qingfeng Zhuge, Meilin Liu, Bin Xiao 0001, Edwin Hsing-Mean Sha	Switching-Activity Minimization on Instruction-Level Loop Scheduling for VLIWDSP Applications.	ASAP	2004	DBLP DOI BibTeX RDF
9	Ganesh Yadav, R. K. Singh, Vipin Chaudhary	On Implementation of MPEG-2 Like Real-Time Parallel Media Applications on MDSP SoC Cradle Architecture.	EUC	2004	DBLP DOI BibTeX RDF
9	Miroslav N. Velev	Efficient formal verification of pipelined processors with instruction queues.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	logic of equality, positive equality, decomposition, SAT
9	Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen	A compact DSP core with static floating-point unit & its microcode generation.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	DSP core, digital signal processor, floating-point units
9	Aleksandar Beric, Ramanathan Sethuraman, Harm Peters, Jef L. van Meerbergen, Gerard de Haan, Carlos A. Alba Pinto	A 27 mW 1.1 mm2 Motion Estimator for Picture-Rate Up-converter.	VLSI Design	2004	DBLP DOI BibTeX RDF
9	Philip Brisk, Adam Kaplan, Majid Sarrafzadeh	Area-efficient instruction set synthesis for reconfigurable system-on-chip designs.	DAC	2004	DBLP DOI BibTeX RDF	field-programmable gate array (FPGA), compiler, resource sharing, integer linear programming (ILP)
9	Christoforos E. Kozyrakis, David A. Patterson 0001	Scalable Vector Processors for Embedded Systems.	IEEE Micro	2003	DBLP DOI BibTeX RDF
9	Kazuaki Ishizaki, Mikio Takeuchi, Kiyokuni Kawachiya, Toshio Suganuma, Osamu Gohda, Tatsushi Inagaki, Akira Koseki, Kazunori Ogata, Motohiro Kawahito, Toshiaki Yasue, Takeshi Ogasawara, Tamiya Onodera, Hideaki Komatsu, Toshio Nakatani	Effectiveness of cross-platform optimizations for a java just-in-time compiler.	OOPSLA	2003	DBLP DOI BibTeX RDF	Java, optimization, just-in-time compiler
9	Andrea Lodi 0002, Mario Toma, Fabio Campi	A pipelined configurable gate array for embedded processors.	FPGA	2003	DBLP DOI BibTeX RDF	FPGA, pipeline, energy, reconfigurable processor
9	James C. Dehnert, Brian Grant, John P. Banning, Richard Johnson, Thomas Kistler, Alexander Klaiber, Jim Mattson	The Transmeta Code Morphing - Software: Using Speculation, Recovery, and Adaptive Retranslation to Address Real-Life Challenges.	CGO	2003	DBLP DOI BibTeX RDF
9	Oliver Wahlen, Manuel Hohenauer, Gunnar Braun, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Xiaoning Nie	Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models.	SCOPES	2003	DBLP DOI BibTeX RDF
9	Fabio Campi, Andrea Cappelli, Roberto Guerrieri, Andrea Lodi 0002, Mario Toma, Alberto La Rosa, Luciano Lavagno, Claudio Passerone, Roberto Canegallo	A Reconfigurable Processor Architecture and Software Development Environment for Embedded Systems.	IPDPS	2003	DBLP DOI BibTeX RDF
9	Mehrdad Reshadi, Nikhil Bansal 0003, Prabhat Mishra 0001, Nikil D. Dutt	An efficient retargetable framework for instruction-set simulation.	CODES+ISSS	2003	DBLP DOI BibTeX RDF	generic instruction model, instruction binary encoding, retargetable instruction-set simulation, architecture description language, decode algorithm
9	Michael L. Chu, Kevin Fan, Scott A. Mahlke	Region-based hierarchical operation partitioning for multicluster processors.	PLDI	2003	DBLP DOI BibTeX RDF	multicluster processor, operation partitioning, clustering, instruction-level parallelism, instruction scheduling, region-based compilation
9	Miroslav N. Velev	Automatic Abstraction of Equations in a Logic of Equality.	TABLEAUX	2003	DBLP DOI BibTeX RDF
9	Afshin Abdollahi, Massoud Pedram, Farzan Fallah, Indradeep Ghosh	Precomputation-based Guarding for Dynamic and Leakage Power Reduction.	ICCD	2003	DBLP DOI BibTeX RDF
9	Guido Bertoni, A. Bircan, Luca Breveglieri, Pasqualina Fragneto, Marco Macchetti, Vittorio Zaccaria	About the performances of the Advanced Encryption Standard in embedded systems with cache memory.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
9	Christian Panis, Raimund Leitner, Herbert Grünbacher, Jari Nurmi	xLIW - a scaleable long instruction word.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
9	Kevin Fan, Nathan Clark, Michael L. Chu, K. V. Manjunath, Rajiv A. Ravindran, Mikhail Smelyanskiy, Scott A. Mahlke	Systematic Register Bypass Customization for Application-Specific Processors.	ASAP	2003	DBLP DOI BibTeX RDF
9	Vinod Kathail, Shail Aditya, Robert Schreiber, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman	PICO: Automatically Designing Custom Computers.	Computer	2002	DBLP DOI BibTeX RDF
9	Sebastian Unger, Frank Mueller 0001	Handling irreducible loops: optimized node splitting versus DJ-graphs.	ACM Trans. Program. Lang. Syst.	2002	DBLP DOI BibTeX RDF	irreducible flowgraphs, reducible flowgraphs, compilation, instruction-level parallelism, Code optimization, loops, control flow graphs, node splitting
9	Oliver Wahlen, Tilman Glökler, Achim Nohl, Andreas Hoffmann 0002, Rainer Leupers, Heinrich Meyr	Application specific compiler/architecture codesign: a case study.	LCTES-SCOPES	2002	DBLP DOI BibTeX RDF	ASIP, architecture exploration, retargetable compiler
9	Alex Aletà, Josep M. Codina, F. Jesús Sánchez, Antonio González 0001, David R. Kaeli	Exploiting Pseudo-Schedules to Guide Data Dependence Graph Partitioning.	IEEE PACT	2002	DBLP DOI BibTeX RDF
9	Chunhong Chen, Majid Sarrafzadeh	Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis.	DATE	2002	DBLP DOI BibTeX RDF
9	Mohamed M. Zahran, Manoj Franklin	A Feasibility Study of Hierarchical Multithreading.	IPDPS	2002	DBLP DOI BibTeX RDF
9	Satoshi Matsushita	Design Experience of a Chip Multiprocessor Merlot and Expectation to Functional Verification.	ISSS	2002	DBLP DOI BibTeX RDF	deign experience, CMP, chip multiprocessor, functional verification, speculative multithreading
9	Giuseppe Desoli, Nikolay Mateev, Evelyn Duesterwald, Paolo Faraboschi, Josh Fisher	A New Facility for Dynamic Control of Program Execution: DELI.	EMSOFT	2002	DBLP DOI BibTeX RDF
9	Lori Carter, Brad Calder	Using predicate path information in hardware to determine true dependences.	ICS	2002	DBLP DOI BibTeX RDF	dependence analysis, predicated execution, path analysis
9	Julio Villalba, Gerardo Bandera, Mario A. González, Javier Hormigo, Emilio L. Zapata	Polynomial Evaluation on Multimedia Processors.	ASAP	2002	DBLP DOI BibTeX RDF