|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 26884 occurrences of 7514 keywords
|
|
|
Results
Found 51597 publication records. Showing 51597 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
20 | Vijaykumar Ramamurthi, Jason McCollum, Christopher Ostler, Karam S. Chatha |
System Level Methodology for Programming CMP Based Multi-Threaded Network Processor Architectures. |
ISVLSI |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Guilherme Dal Pizzol, Philippe Olivier Alexandre Navaux |
Branch Prediction Topologies for SMT Architectures. |
SBAC-PAD |
2005 |
DBLP DOI BibTeX RDF |
|
20 | Daniel Bauer 0001, Ilias Iliadis, Sean Rooney, Paolo Scotton |
Communication Architectures for Massive Multi-Player Games. |
Multim. Tools Appl. |
2004 |
DBLP DOI BibTeX RDF |
massive multi-player games, scalability assessment, federated peer-to-peer systems, client-server systems |
20 | Aviral Shrivastava, Nikil D. Dutt |
Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA). |
ASP-DAC |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Klaus Waldschmidt |
Adaptive System Architectures. |
IPDPS |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Christopher D. Rickett, Sung-Eun Choi, Bradford L. Chamberlain |
Compiling High-Level Languages for Vector Architectures. |
LCPC |
2004 |
DBLP DOI BibTeX RDF |
|
20 | Vincenzo Eramo, Marco Listanti |
Dimensioning Models of Shared Resources in Optical Packet Switching Architectures. |
QoS-IP |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Guido Bertoni, Jorge Guajardo, Gerardo Orlando |
Systolic and Scalable Architectures for Digit-Serial Multiplication in Fields GF(pm). |
INDOCRYPT |
2003 |
DBLP DOI BibTeX RDF |
|
20 | Karl-Erwin Großpietsch |
Guest Editor's Edtroduction: Unorthodox Computer Architectures. |
IEEE Micro |
2002 |
DBLP DOI BibTeX RDF |
|
20 | Istabrak Abdul-Fatah, Shikharesh Majumdar |
Performance of CORBA-Based Client-Server Architectures. |
IEEE Trans. Parallel Distributed Syst. |
2002 |
DBLP DOI BibTeX RDF |
Middleware performance, CORBA performance, client-server performance, software performance, experimental performance evaluation |
20 | Pietro Abate, Marco Bernardo 0001 |
A scalable approach to the design of SW architectures with dynamically create/destroyed components. |
SEKE |
2002 |
DBLP DOI BibTeX RDF |
|
20 | Chao-Tsung Huang, Po-Chih Tseng, Liang-Gee Chen |
Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method. |
ISCAS (5) |
2002 |
DBLP DOI BibTeX RDF |
|
20 | Sundar Iyer, Rui Zhang, Nick McKeown |
Routers with a single stage of buffering. |
SIGCOMM |
2002 |
DBLP DOI BibTeX RDF |
constraint sets, routers, buffers, switching |
20 | Dilip V. Sarwate, Naresh R. Shanbhag |
High-speed architectures for Reed-Solomon decoders. |
IEEE Trans. Very Large Scale Integr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
20 | Ilka Philippow, Matthias Riebisch |
Systematic Definition of Reusable Architectures. |
ECBS |
2001 |
DBLP DOI BibTeX RDF |
Frame-works, Architecture, Components, Software product lines, Reusability, Domain Analysis, Object technology, Evolutionary development |
20 | Ramadass Nagarajan, Karthikeyan Sankaralingam, Doug Burger, Stephen W. Keckler |
A design space evaluation of grid processor architectures. |
MICRO |
2001 |
DBLP DOI BibTeX RDF |
|
20 | Alexander Marquardt, Vaughn Betz, Jonathan Rose |
Speed and area tradeoffs in cluster-based FPGA architectures. |
IEEE Trans. Very Large Scale Integr. Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
20 | Bharat P. Dave, Niraj K. Jha |
COHRA: Hardware-Software Co-Synthesis of Hierarchical Distributed Embedded System Architectures. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
scheduling, distributed systems, embedded systems, hierarchy, allocation, system synthesis, hardware-software co-synthesis |
20 | José L. Fernández, Bárbara Álvarez, Francisco J. García Izquierdo, Ángel Pérez, Juan Antonio de la Puente |
A Case Study in Quantitative Evaluation of Real-Time Software Architectures. |
Ada-Europe |
1998 |
DBLP DOI BibTeX RDF |
|
19 | Damián A. Mallón, Guillermo L. Taboada, Carlos Teijeiro, Juan Touriño, Basilio B. Fraguela, Andrés Gómez 0002, Ramon Doallo, José Carlos Mouriño |
Performance Evaluation of MPI, UPC and OpenMP on Multicore Architectures. |
PVM/MPI |
2009 |
DBLP DOI BibTeX RDF |
NAS Parallel Benchmarks (NPB), Performance Evaluation, MPI, OpenMP, Multicore Architectures, UPC |
19 | Youssouf Zatout, Eric Campo, Jean-François Llibre |
Toward hybrid WSN architectures for monitoring people at home. |
MEDES |
2009 |
DBLP DOI BibTeX RDF |
wireless body area network (WBAN), wireless sensor networks (WSNs), evaluation metrics, hybrid architectures, design framework, home monitoring |
19 | Niranjan Suri |
Dynamic service-oriented architectures for tactical edge networks. |
WEWST |
2009 |
DBLP DOI BibTeX RDF |
dynamic service-oriented architectures, tactical edge networks, load balancing, service discovery, green computing, service migration |
19 | Ian Gray, Neil C. Audsley |
Exposing non-standard architectures to embedded software using compile-time virtualisation. |
CASES |
2009 |
DBLP DOI BibTeX RDF |
architectures, virtualization, embedded, application-specific, compile-time |
19 | Bertil Schmidt, Douglas L. Maskell |
Workshop on Using Emerging Parallel Architectures for Computational Science. |
ICCS (1) |
2009 |
DBLP DOI BibTeX RDF |
High Performance Computing, Reconfigurable Computing, Computational Science, GPGPU, Parallel Computer Architectures, Heterogeneous Multi-cores |
19 | Matteo Monchiero, Ramon Canal, Antonio González 0001 |
Power/Performance/Thermal Design-Space Exploration for Multicore Architectures. |
IEEE Trans. Parallel Distributed Syst. |
2008 |
DBLP DOI BibTeX RDF |
simulation of, Modeling, evaluation, Measurement, Parallel Architectures, Shared memory, Energy-aware systems, multiple-processor systems |
19 | Marjan Karkooti, Predrag Radosavljevic, Joseph R. Cavallaro |
Configurable LDPC Decoder Architectures for Regular and Irregular Codes. |
J. Signal Process. Syst. |
2008 |
DBLP DOI BibTeX RDF |
Error correcting codes, Reconfigurable architectures, Low density parity check codes |
19 | Carolyn McGregor, J. Mikael Eklund |
Real-Time Service-Oriented Architectures to Support Remote Critical Care: Trends and Challenges. |
COMPSAC |
2008 |
DBLP DOI BibTeX RDF |
Neonatal Care, Intensive Care Unit, Critical Care, Service Oriented Architectures, Health Informatics, Event Stream Processing |
19 | Hsin-Chou Chi, Chia-Ming Wu, Jun-Hui Lee |
Integrated Mapping and Scheduling for Circuit-Switched Network-on-Chip Architectures. |
DELTA |
2008 |
DBLP DOI BibTeX RDF |
network-on-chip architectures, scheduling, mapping, circuit-switched networks |
19 | Christopher Ostler, Karam S. Chatha, Goran Konjevod |
Approximation Algorithm for Process Mapping on Network Processor Architectures. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
Intel IXP2400 architecture, programmable network processor architectures, symmetric multiprocessing, automated system-level design, NP-complete problem, process mapping, polynomial time approximation algorithm, block multithreading |
19 | Cristóbal Costa Soria, Nour Ali, Jennifer Pérez, José A. Carsí, Isidro Ramos |
Dynamic Reconfiguration of Software Architectures Through Aspects. |
ECSA |
2007 |
DBLP DOI BibTeX RDF |
software architectures, Dynamic reconfiguration, AOSD |
19 | Jih-Fu Tu |
Cache Management for Discrete Processor Architectures. |
ISPA |
2005 |
DBLP DOI BibTeX RDF |
Discrete processor architectures, write-invalidate (WI) and cache block, multithreading, cache coherency, shared cache, memory latency |
19 | Srinivasan Ramasubramanian, Arun K. Somani |
Analysis of optical networks with heterogeneous grooming architectures. |
IEEE/ACM Trans. Netw. |
2004 |
DBLP DOI BibTeX RDF |
WDM/TDM switching, heterogeneous grooming architectures, performance modeling, optical networks, blocking probability |
19 | Flávio Oquendo |
pi-ARL: an architecture refinement language for formally modelling the stepwise refinement of software architectures. |
ACM SIGSOFT Softw. Eng. Notes |
2004 |
DBLP DOI BibTeX RDF |
architecture refinement languages, formal development techniques, software architectures, stepwise refinement |
19 | Rafik Amir Salama, Amir Zeid |
A UML profile for service oriented architectures. |
OOPSLA Companion |
2004 |
DBLP DOI BibTeX RDF |
software engineering, service oriented architectures, UML profiles |
19 | Fredy Rivera, Marcos Sánchez-Élez, Milagros Fernández, Román Hermida, Nader Bagherzadeh |
Efficient mapping of hierarchical trees on coarse-grain reconfigurable architectures. |
CODES+ISSS |
2004 |
DBLP DOI BibTeX RDF |
multimedia, computer graphics, reconfigurable architectures, SIMD, hierarchical trees |
19 | Ming Huo, Shikharesh Majumdar |
Performance of parallel architectures for CORBA-based systems. |
WOSP |
2004 |
DBLP DOI BibTeX RDF |
CORBA performance, high performance middleware, interaction architectures |
19 | Laurence E. LaForge, Kirk F. Korver, M. Sami Fadali |
What Designers of Bus and Network Architectures Should Know about Hypercubes. |
IEEE Trans. Computers |
2003 |
DBLP DOI BibTeX RDF |
Hypercube fault tolerance, hypercube latency, Hamming graphs, K-cubes, Moore graphs, Moore Bound, C-cubes, performability, quorums, configuration architectures, Lee distance |
19 | Fahri Yetim, Elaine M. Raybourn |
Supporting intercultural computer-mediated discourse: methods, models, and architectures. |
CHI Extended Abstracts |
2003 |
DBLP DOI BibTeX RDF |
intercultural computer-mediated discourse, models, architectures, methods, intercultural communication |
19 | Alice Wang, Anantha P. Chandrakasan |
Energy-aware architectures for a real-valued FFT implementation. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
energy-quality scalability, microsensors, source tracking and localization, wireless sensor networks, energy efficient, fast fourier transform (FFT), energy-awareness, digital signal processors (DSP), scalable architectures |
19 | Chidamber Kulkarni, Matthias Gries, Christian Sauer 0001, Kurt Keutzer |
Programming challenges in network processor deployment. |
CASES |
2003 |
DBLP DOI BibTeX RDF |
IPv4 forwarding, programming heterogeneous architectures, mapping, programming model, multi-threading, resource sharing |
19 | Nicolas Sklavos 0001, Odysseas G. Koufopavlou |
Architectures and VLSI Implementations of the AES-Proposal Rijndael. |
IEEE Trans. Computers |
2002 |
DBLP DOI BibTeX RDF |
secret key ciphers, security, AES, Rijndael, pipelining architectures |
19 | William L. Freking, Keshab K. Parhi |
Performance-Scalable Array Architectures for Modular Multiplication. |
J. VLSI Signal Process. |
2002 |
DBLP DOI BibTeX RDF |
modular multipliers, systolic computation, high-radix arithmetic implementation, pipelined architectures |
19 | Vangalur S. Alagar, Ralf Lämmel |
Three-Tiered Specification of Micro-architectures. |
ICFEM |
2002 |
DBLP DOI BibTeX RDF |
UML, interaction, formal methods, frameworks, design patterns, reuse, evolution, object-oriented design, micro-architectures |
19 | Juanjo Noguera, Rosa M. Badia |
Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures. |
CODES |
2002 |
DBLP DOI BibTeX RDF |
dynamic run-time scheduling, reconfigurable architectures |
19 | William Fornaciari, Vito Trianni, Carlo Brandolese, Donatella Sciuto, Fabio Salice, Giovanni Beltrame |
Modeling Assembly Instruction Timing in Superscalar Architectures. |
ISSS |
2002 |
DBLP DOI BibTeX RDF |
assembly-level analysis, performance estimation, superscalar architectures |
19 | Shyh-Kwei Chen, W. Kent Fuchs |
Compiler-Assisted Multiple Instruction Word Retry for VLIW Architectures. |
IEEE Trans. Parallel Distributed Syst. |
2001 |
DBLP DOI BibTeX RDF |
compilers, Fault-tolerant computing, instruction level parallelism, VLIW architectures, instruction retry |
19 | Alencar de Melo Jr., Juan Manuel Adán Coello |
Packet Scheduling Based on Learning in the Next Generation Internet Architectures. |
ISCC |
2000 |
DBLP DOI BibTeX RDF |
new Internet architectures, quality of service, machine learning, fuzzy control, packet scheduling |
19 | Nimish Doshi |
Object Databases and Multi-Tier Architectures. |
TOOLS (26) |
1998 |
DBLP DOI BibTeX RDF |
Multi-tier Arcitiectures, Object Databases and Multi-Tier Architectures, Object Databases |
19 | Edward D. Moreno, Sergio Takeo Kofuji |
Efficiency of remote access caches in future SMP-based CC-NUMA multiprocessors: initial results. |
ISPAN |
1997 |
DBLP DOI BibTeX RDF |
shared remote access cache, future SMP based CC-NUMA multiprocessors, symmetric multiprocessor nodes, future architectures, realistic hardware parameters, state of the art systems components, SPLASH-2 benchmark suite, performance application, baseline architecture, approach-1, slow network, approach-2, fast network, 32-processor system, four-processor SMP nodes, two-processor SMP nodes, multiprocessing systems, execution time, cost effectiveness |
19 | T. C. Nicholas Graham, Tore Urnes |
Linguistic Support for the Evolutionary Design of Software Architectures. |
ICSE |
1996 |
DBLP BibTeX RDF |
Clock-Works programming environment, architecture language, automatic message routing, constraint-based communication, multiuser applications, restricted scoping, visual syntax, software engineering, interactive, software architectures, programming environments, interactive systems, Clock, high level languages |
19 | Leilei Song, Keshab K. Parhi |
Efficient Finite Field Serial/Parallel Multiplication. |
ASAP |
1996 |
DBLP DOI BibTeX RDF |
finite field serial/parallel multiplication, finite field arithmetic architectures, bit-serial/parallel finite field multiplier, standard basis representation, optimal primitive polynomials, minimum hardware complexity, semi-systolic architecture, computational complexity, cryptography, cryptography, encoding, digital arithmetic, polynomials, multiplying circuits, VLSI implementation, coding theory |
19 | Guido Araujo, Sharad Malik |
Optimal code generation for embedded memory non-homogeneous register architectures. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
TMS320C25 processor, [1, /spl infin/] model, embedded memory nonhomogeneous register architectures, expression trees, optimal code generation, register transfer graph, scheduling, computational complexity, graph theory, optimisation, computer architecture, register allocation, processor scheduling, storage allocation, microprocessor chips, instruction sets, instruction set architecture, sufficient conditions, instruction selection, structural representation |
19 | Catherine H. Gebotys, Robert J. Gebotys |
Optimized mapping of video applications to hardware-software for VLSI architectures. |
HICSS (1) |
1995 |
DBLP DOI BibTeX RDF |
integer optimization, video computations, video systems, optimized mapping, scheduling, VLSI, optimisation, VLSI architectures, video signal processing, VLIW processor |
19 | Hermann Kopetz |
Why time-triggered architectures will succeed in large hard real-time systems. |
FTDCS |
1995 |
DBLP DOI BibTeX RDF |
large hard real-time systems, encapsulated subsystems, temporal firewalls, sparse time base, replica determinism, time-triggered communication protocol, real-time systems, computational complexity, computer architecture, design principles, time-triggered architectures |
19 | Philip S. Yu, Asit Dan |
Performance Evaluation of Transaction Processing Coupling Architectures for Handling System Dynamics. |
IEEE Trans. Parallel Distributed Syst. |
1994 |
DBLP DOI BibTeX RDF |
shared memorysystems, transaction processing coupling architectures, systemdynamics, shared disk architecture, shared intermediatememory architecture, performance evaluation, performance evaluation, fault tolerant computing, transaction processing, shared nothing architecture |
19 | Alex Delis, Nick Roussopoulos |
Performance Comparison of Three Modern DBMS Architectures. |
IEEE Trans. Software Eng. |
1993 |
DBLP DOI BibTeX RDF |
DBMS architectures, software architecture configurations, RAD-UNIFY type, functional components, performance evaluation, software engineering, database management systems, local area networks, simulation results, simulation models, design rationales, workstations, client-server |
19 | Branislav Meandzija |
Archetype: A Unified Method for the Design and Implementation of Protocol Architectures. |
IEEE Trans. Software Eng. |
1988 |
DBLP DOI BibTeX RDF |
data-driven concurrent execution model, abstract protocol architecture specifications, performance constraints, X.25-level 3-like protocol, protocols, data structures, data structures, natural languages, automatic programming, automatic programming, protocol design, automated design, multiprocessing programs, simulation languages, protocol architectures, specification technique, Archetype |
19 | Nadathur Satish, Changkyu Kim, Jatin Chhugani, Anthony D. Nguyen, Victor W. Lee, Daehyun Kim 0001, Pradeep Dubey |
Fast sort on CPUs and GPUs: a case for bandwidth oblivious SIMD sort. |
SIGMOD Conference |
2010 |
DBLP DOI BibTeX RDF |
merge network, tlp, performance, databases, sorting, buffer, merge, many-core, simd, radix |
19 | Jan Hoogerbrugge, Henk Corporaal |
Comparing Software Pipelining for an Operation-Triggered and a Tarnsport-Triggered Architecture. |
CC |
1992 |
DBLP DOI BibTeX RDF |
|
18 | Matthias Galster |
Describing variability in service-oriented software product lines. |
ECSA Companion Volume |
2010 |
DBLP DOI BibTeX RDF |
modeling, service-oriented architectures, variability |
18 | Bita Gorjiara, Daniel Gajski |
Automatic architecture refinement techniques for customizing processing elements. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
GNR, nanocoded architectures, no-instruction-set computer (NISC), refinement, high-level synthesis, power, ASIP, datapath, netlist |
18 | Carl Ebeling, Chris Fisher, Guanbin Xing, Manyuan Shen, Hui Liu 0011 |
Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture. |
IEEE Trans. Computers |
2004 |
DBLP DOI BibTeX RDF |
Data communications devices, application studies resulting in better multiple-processor systems, reconfigurable hardware, wireless systems, special-purpose and application-based systems, adaptable architectures, heterogeneous (hybrid) systems, design studies, signal processing systems |
18 | Jun Han |
TRAM: A Tool for Requirements and Architecture Management. |
ACSC |
2001 |
DBLP DOI BibTeX RDF |
system architectures, Requirements management, software engineering tools |
18 | Kemal Efe, Antonio Fernández 0001 |
Mesh-Connected Trees: A Bridge Between Grids and Meshes of Trees. |
IEEE Trans. Parallel Distributed Syst. |
1996 |
DBLP DOI BibTeX RDF |
parallel algorithms, grids, interconnection networks, Parallel architectures, hypercubes, binary tree, graph embedding, product networks, mesh of trees |
18 | José Monteiro 0001, John Rinderknecht, Srinivas Devadas, Abhijit Ghosh |
Optimization of combinational and sequential logic circuits for low power using precomputation. |
ARVLSI |
1995 |
DBLP DOI BibTeX RDF |
sequential logic circuits, low power optimisation, logic optimization technique, precomputation architectures, logic synthesis methods, transmission gates, transparent latches, switching activity reduction, power dissipation reduction, VLSI, logic design, sequential circuits, combinational circuits, integrated circuit design, CMOS logic circuits, circuit optimisation, precomputation, combinational logic circuits, clock cycle |
18 | Sébastien Bilavarn |
Modélisation, Conception Système d'Architectures Hétérogènes pour les Applications Embarquées : Eléments d'amélioration de l'efficacité énergétique des systèmes sur puce de silicium. (Modelling, Design of Heterogenous architectures for embedded Applications / Modelling, Design of Heterogenous architectures for embedded Applications : Refinement parts about power efficiency of silicon chips systems). |
|
2018 |
RDF |
|
18 | Eleni Kanellou |
Data Structures for Current Multi-core and Future Many-core Architectures. (Structures de données pour des architectures multi-cœur actuelles et de futures architectures many-cœur). |
|
2015 |
RDF |
|
18 | Steffen Becker 0001, Frantisek Plásil, Ralf H. Reussner (eds.) |
Quality of Software Architectures. Models and Architectures, 4th International Conference on the Quality of Software-Architectures, QoSA 2008, Karlsruhe, Germany, October 14-17, 2008. Proceedings |
QoSA |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Ales Plsek, Jirí Adámek |
Carmen: Software Component Model Checker. |
QoSA |
2008 |
DBLP DOI BibTeX RDF |
|
18 | J. Andrés Díaz Pace, Hyunwoo Kim, Len Bass, Philip Bianco, Felix Bachmann |
Integrating Quality-Attribute Reasoning Frameworks in the ArchE Design Assistant. |
QoSA |
2008 |
DBLP DOI BibTeX RDF |
Architecture-based analysis & design, ArchE, quality attributes, design assistance |
18 | Bas van der Raadt, Hans van Vliet |
Designing the Enterprise Architecture Function. |
QoSA |
2008 |
DBLP DOI BibTeX RDF |
Organizational, Management, Enterprise Architecture, Governance, Function, Reference Model, Conformance |
18 | Julien Mallet, Siegfried Rouvrais |
Style-Based Model Transformation for Early Extrafunctional Analysis of Distributed Systems. |
QoSA |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Vittorio Cortellessa, Pierluigi Pierini, Romina Spalazzese, Alessio Vianale |
MOSES: MOdeling Software and platform architEcture in UML 2 for Simulation-based performance analysis. |
QoSA |
2008 |
DBLP DOI BibTeX RDF |
Simulation, UML, Software Performance, Resource Modeling |
18 | Guillaume Waignier, Anne-Françoise Le Meur, Laurence Duchien |
Architectural Specification and Static Analyses of Contractual Application Properties. |
QoSA |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Antony Tang, Minh H. Tran, Jun Han 0004, Hans van Vliet |
Design Reasoning Improves Software Design Quality. |
QoSA |
2008 |
DBLP DOI BibTeX RDF |
Design Reasoning, Usability, Software Architecture Design |
18 | Danilo Ardagna, Carlo Ghezzi, Raffaela Mirandola |
Rethinking the Use of Models in Software Architecture. |
QoSA |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Larix Lee, Philippe Kruchten |
A Tool to Visualize Architectural Design Decisions. |
QoSA |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Gabriel A. Moreno, Paulo Merson |
Model-Driven Performance Analysis. |
QoSA |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Anton Jansen, Tjaard de Vries, Paris Avgeriou, Martijn van Veelen |
Sharing the Architectural Knowledge of Quantitative Analysis. |
QoSA |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Frank Salger, Marcel Bennicke, Gregor Engels, Claus Lewerentz |
Comprehensive Architecture Evaluation and Management in Large Software-Systems. |
QoSA |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Stefano Gallotti, Carlo Ghezzi, Raffaela Mirandola, Giordano Tamburrelli |
Quality Prediction of Service Compositions through Probabilistic Model Checking. |
QoSA |
2008 |
DBLP DOI BibTeX RDF |
|
18 | Samy Meftali |
Exploration d'architectures et allocation/affectation mémoire dans les systèmes multiprocesseurs mono puce = Architectures exploration and memory allocation/assignment in multiprocessor SoC. (Architectures exploration and memory allocation/assignment in multiprocessor SoC). |
|
2002 |
RDF |
|
18 | Alireza Amirshahi, Giovanni Ansaloni, David Atienza |
Accelerator-Driven Data Arrangement to Minimize Transformers Run-Time on Multi-Core Architectures. |
PARMA-DITAM |
2024 |
DBLP DOI BibTeX RDF |
|
18 | Mohammed Bey Ahmed Khernache, Jalil Boukhobza, Yahia Benmoussa, Daniel Ménard |
Energy-Aware HEVC Software Decoding On Mobile Heterogeneous Multi-Cores Architectures. |
PARMA-DITAM@HiPEAC |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Antonino Tumeo, Nicolas Bohm Agostini, Serena Curzel, Ankur Limaye, Cheng Tan 0002, Vinay Amatya, Marco Minutoli, Vito Giovanni Castellana, Ang Li 0006, Joseph B. Manzano |
SO(DA)2: End-to-end Generation of Specialized Reconfigurable Architectures (Invited Talk). |
PARMA-DITAM@HiPEAC |
2022 |
DBLP DOI BibTeX RDF |
|
18 | Hugo Miomandre, Julien Hascoët, Karol Desnos, Kevin J. M. Martin, Benoît Dupont de Dinechin, Jean-François Nezan |
Embedded Runtime for Reconfigurable Dataflow Graphs on Manycore Architectures. |
PARMA-DITAM@HiPEAC |
2018 |
DBLP DOI BibTeX RDF |
|
18 | Carsten Lucke, Markus May, Nane Kratzke, Ulrike Lechner |
How Do System and Enterprise Architectures Influence Knowledge Management in Software Projects? - An Explorative Study of Six Software Projects. |
EMISA |
2009 |
DBLP BibTeX RDF |
|
18 | Sabine Buckl, Alexander M. Ernst, Josef Lankes, Christian M. Schweda, André Wittenburg |
Generating Visualizations of Enterprise Architectures using Model Transformations. |
EMISA |
2007 |
DBLP BibTeX RDF |
|
18 | Antonia Bertolino, Paola Inverardi, Henry Muccini |
Formal Methods in Testing Software Architectures. |
SFM |
2003 |
DBLP DOI BibTeX RDF |
|
18 | David F. Snelling, Gregory K. Egan |
A Comparative Study of Data-Flow Architectures. |
IFIP PACT |
1994 |
DBLP BibTeX RDF |
|
18 | Rainer Leupers, Wolfgang Schenk, Peter Marwedel |
Microcode Generation for Flexible Parallel Target Architectures. |
IFIP PACT |
1994 |
DBLP BibTeX RDF |
|
18 | Hiecheol Kim, Jean-Luc Gaudiot |
Exploitation of Fine-grain Parallelism in Logic Languages on Massively Parallel Architectures. |
IFIP PACT |
1994 |
DBLP BibTeX RDF |
|
18 | Andrea Capitanio, Nikil D. Dutt, Alexandru Nicolau |
Partitioning of Variables for Multiple-Register-File Architectures via Hypergraph Coloring. |
IFIP PACT |
1994 |
DBLP BibTeX RDF |
|
18 | Michel Weinfeld |
Integrated artificial neural networks: components for higher level architectures with new properties. |
NATO Neurocomputing |
1989 |
DBLP DOI BibTeX RDF |
|
18 | Pierre Peretto, Robert Van Zurk, André Mougin, Christian Gamrat |
The Semi-Parallel Architectures of Neuro-Computers. |
NATO Neurocomputing |
1989 |
DBLP DOI BibTeX RDF |
|
18 | Jan Müller 0001, Dirk Fimmel, Renate Merker |
Exploitation of Instruction-Level Parallelism for Optimal Loop Scheduling. |
Interaction between Compilers and Computer Architectures |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Motonobu Fujita, Masaaki Kondo, Hiroshi Nakamura |
Data Movement Optimization for Software-Controlled On-Chip Memory. |
Interaction between Compilers and Computer Architectures |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Osman S. Unsal, Israel Koren, C. Mani Krishna 0001, Csaba Andras Moritz |
Cool-Fetch: A Compiler-Enabled IPC Estimation Based Framework for Energy Reduction. |
Interaction between Compilers and Computer Architectures |
2004 |
DBLP DOI BibTeX RDF |
|
18 | Pramod Ramarao, Akhilesh Tyagi |
An Adiabatic Framework for a Low Energy µ-Architecture & Compiler. |
Interaction between Compilers and Computer Architectures |
2003 |
DBLP DOI BibTeX RDF |
|
18 | Romain Rouvoy, Paolo Barone, Yun Ding, Frank Eliassen, Svein O. Hallsteinsen, Jorge Lorenzo, Alessandro Mamelli, Ulrich Scholz |
MUSIC: Middleware Support for Self-Adaptation in Ubiquitous and Service-Oriented Environments. |
Software Engineering for Self-Adaptive Systems |
2009 |
DBLP DOI BibTeX RDF |
Adaptation planning, service-oriented architectures, self-adaptation, component-based architectures |
|
|