Search results for "datapath"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
9	Dmitry Ponomarev 0001, Gurhan Kucuk, Kanad Ghose	AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors.	DATE	2002	DBLP DOI BibTeX RDF
9	Marcos Ferretti, Peter A. Beerel	Single-Track Asynchronous Pipeline Templates Using 1-of-N Encoding.	DATE	2002	DBLP DOI BibTeX RDF
9	José M. Mendías, Román Hermida, María C. Molina, Olga Peñalba	Efficient Verification of Scheduling, Allocation and Binding in High-Level Synthesis.	DSD	2002	DBLP DOI BibTeX RDF
9	Oswaldo Cadenas, Graham M. Megson	A Clocking Technique with Power Savings in Virtex-Based Pipelined Designs.	FPL	2002	DBLP DOI BibTeX RDF
9	Dmitry Cheresiz, Ben H. H. Juurlink, Stamatis Vassiliadis, Harry A. G. Wijshoff	Performance Scalability of Multimedia Instruction Set Extensions.	Euro-Par	2002	DBLP DOI BibTeX RDF
9	Aristidis Sotiropoulos, Georgios Tsoukalas, Nectarios Koziris	Enhancing the Performance of Tiled Loop Execution onto Clusters Using Memory Mapped Network Interfaces and Pipelined Schedules.	IPDPS	2002	DBLP DOI BibTeX RDF	Memory Mapped Interfaces, Zero-Copy Protocols, DMA transfers, Loop Tiling, Communication Overlapping
9	Carles Rodoreda Sala, Natalino G. Busá	A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW Processor.	ISSS	2002	DBLP DOI BibTeX RDF	VLIW processors, reconfigurable logic, architectural synthesis
9	Juan Carlos López 0001, Fernando Rincón, Francisco Moya, José Manuel Moya	Improving Embedded System Design by Means of HW-SW Compilation on Reconfigurable Coprocessors.	ISSS	2002	DBLP DOI BibTeX RDF	reconfigurable datapaths, hardware-software codesign
9	Chao Huang, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	High-level synthesis of distributed logic-memory architectures.	ICCAD	2002	DBLP DOI BibTeX RDF
9	Weiping Liao, Joseph M. Basile, Lei He 0001	Leakage power modeling and reduction with data retention.	ICCAD	2002	DBLP DOI BibTeX RDF
9	Maria Athanasaki, Aristidis Sotiropoulos, Georgios Tsoukalas, Nectarios Koziris	A Pipelined Execution of Tiled Nested Loops on SMPs with Computation and Communication Overlapping.	ICPP Workshops	2002	DBLP DOI BibTeX RDF
9	Karim Ben Chehida, Michel Auguin	HW / SW partitioning approach for reconfigurable system design.	CASES	2002	DBLP DOI BibTeX RDF	genetic algorithm, clustering, dynamic reconfiguration, codesign, HW/SW partitioning
9	Oguz Ergin, Kanad Ghose, Gurhan Kucuk, Dmitry Ponomarev 0001	A Circuit-Level Implementation of Fast, Energy-Efficient CMOS Comparators for High-Performance Microprocessors.	ICCD	2002	DBLP DOI BibTeX RDF
9	Hyun-Gyu Kim, Hyeong-Cheol Oh	Efficient Hardware Multiplicative Inverters.	ICISC	2002	DBLP DOI BibTeX RDF
9	Koji Ohashi, Mineo Kaneko	Heuristic assignment-driven scheduling for data-path synthesis.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
9	Chang Yong Kang, Earl E. Swartzlander Jr.	An Analysis of the CORDIC Algorithm for Direct Digital Frequency Synthesis.	ASAP	2002	DBLP DOI BibTeX RDF
9	Anna Antola, Mariagiovanna Sami, Vincenzo Piuri	On-line Diagnosis and Reconfiguration of FPGA Systems.	DELTA	2002	DBLP DOI BibTeX RDF	on-line detection, fault tolerance, FPGA, reconfiguration, diagnosis
9	Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten Schwan, Richard West	Architecture and Hardware for Scheduling Gigabit Packet Streams.	Hot Interconnects	2002	DBLP DOI BibTeX RDF
9	Tomás Bautista, Antonio Núñez	Quantitative study of the impact of design and synthesis options on processor core performance.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
9	Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Wu Ye	Influence of compiler optimizations on system power.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
9	Oliver Chiu-sing Choy, Jan Butas, Juraj Povazanec, Cheong-Fat Chan	A New Control Circuit for Asynchronous Micropipelines.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	zero-overhead, dual-rail coding, Asynchronous design, micropipeline
9	HyungWon Kim 0001, John P. Hayes	Realization-independent ATPG for designs with unimplemented blocks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
9	Sanghun Park, Kiyoung Choi	Performance-driven high-level synthesis with bit-level chaining andclock selection.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
9	Ben H. H. Juurlink, Stamatis Vassiliadis, Dmitri Tcheressiz, Harry A. G. Wijshoff	Implementation and Evaluation of the Complex Streamed Instruction Set.	IEEE PACT	2001	DBLP DOI BibTeX RDF
9	Reiner W. Hartenstein	Reconfigurable Computing: A New Business Model and its Impact on SoC Design.	DSD	2001	DBLP DOI BibTeX RDF
9	W. J. Bainbridge, Stephen B. Furber	Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding.	ASYNC	2001	DBLP DOI BibTeX RDF
9	Mei-Yun Hsu, Hao-Chieh Chang, Yi-Chu Wang, Liang-Gee Chen	Scalable module-based architecture for MPEG-4 BMA motion estimation.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
9	Seongmoo Heo, Ronny Krashinsky, Krste Asanovic	Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy.	ARVLSI	2001	DBLP DOI BibTeX RDF
9	Sheng Sun, Larry McMurchie, Carl Sechen	A High-Performance 64-bit Adder Implemented in Output Prediction Logic.	ARVLSI	2001	DBLP DOI BibTeX RDF
9	Azeez J. Bhavnagarwala, Blanca Austin, Keith A. Bowman, James D. Meindl	A minimum total power methodology for projecting limits on CMOS GSI.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
9	Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Sequential fault modeling, test pattern generation, robust testing, iterative logic arrays
9	Tomás Lang, Elisardo Antelo	CORDIC-Based Computation of ArcCos.	J. VLSI Signal Process.	2000	DBLP DOI BibTeX RDF
9	Shiro Kobayashi, Gerhard P. Fettweis	A Hierarchical Block-Floating-Point Arithmetic.	J. VLSI Signal Process.	2000	DBLP DOI BibTeX RDF
9	Michael Münch, Norbert Wehn, Bernd Wurth, Renu Mehra, Jim Sproch	Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths.	DATE	2000	DBLP DOI BibTeX RDF
9	Jens Schönherr, Bernd Straube	Automatic Equivalence Check of Circuit Descriptions at Clocked Algorithmic and Register Transfer Level.	DATE	2000	DBLP DOI BibTeX RDF
9	Xianfeng Zhou, Margaret Martonosi	Augmenting Modern Superscalar Architectures with Configurable Extended Instructions.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF
9	R. Anand, Margarida F. Jacome, Gustavo de Veciana	Heuristic tradeoffs between latency and energy consumption in register assignment.	CODES	2000	DBLP DOI BibTeX RDF
9	Henry Styles, Wayne Luk	Customizing Graphics Applications: Techniques and Programming Interface.	FCCM	2000	DBLP DOI BibTeX RDF
9	Cameron Patterson	High Performance DES Encryption in Virtex(tm) FPGAs Using Jbits(tm).	FCCM	2000	DBLP DOI BibTeX RDF
9	Pedro C. Diniz, Joonseok Park	Automatic Synthesis of Data Storage and Control Structures for FPGA-Based Computing Engines.	FCCM	2000	DBLP DOI BibTeX RDF	FPGA-based reconfigurable computing architectures, data queues, compilation, program analysis
9	Michael J. Wirthlin, Steve Morrison, Paul S. Graham, Brian Bray	Improving the Performance and Efficiency of an Adaptive Amplification Operation Using Configurable Hardware.	FCCM	2000	DBLP DOI BibTeX RDF
9	Natalino G. Busá, Albert van der Werf, Marco Bekooij	Scheduling Coarse-Grain Operations for VLIW Processors.	ISSS	2000	DBLP DOI BibTeX RDF
9	Kamal S. Khouri, Niraj K. Jha	Leakage Power Analysis and Reduction during Behavioral Synthesis.	ICCD	2000	DBLP DOI BibTeX RDF
9	Larry McMurchie, Su Kio, Gin Yee, Tyler Thorp, Carl Sechen	Output Prediction Logic: A High-Performance CMOS Design Technique.	ICCD	2000	DBLP DOI BibTeX RDF
9	Gin Yee, Tyler Thorp, Ron Christopherson, Ban P. Wang, Carl Sechen	An Automated Shielding Algorithm and Tool For Dynamic Circuits.	ISQED	2000	DBLP DOI BibTeX RDF
9	Mark D. Aagaard, Robert B. Jones, Thomas F. Melham, John W. O'Leary, Carl-Johan H. Seger	A Methodology for Large-Scale Hardware Verification.	FMCAD	2000	DBLP DOI BibTeX RDF
9	Russell E. Henning, Chaitali Chakrabarti	Relating Data Characteristics to Transition Activity in High-Level Static CMOS Design.	VLSI Design	2000	DBLP DOI BibTeX RDF	statistical parameters, high-level synthesis, Low power design, data models, transition activity
9	Cameron Patterson	A Dynamic FPGA Implementation of the Serpent Block Cipher.	CHES	2000	DBLP DOI BibTeX RDF
9	Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Hyun Suk Kim, Wu Ye	Energy-driven integrated hardware-software optimizations using SimplePower.	ISCA	2000	DBLP DOI BibTeX RDF	energy optimization and estimation, energy simulator, hardware-software interaction, system energy, compiler optimizations, low-power architectures
9	Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Wu Ye	Influence of compiler optimizations on system power.	DAC	2000	DBLP DOI BibTeX RDF
9	William J. Dally, Andrew Chang 0001	The role of custom design in ASIC Chips.	DAC	2000	DBLP DOI BibTeX RDF
9	Laurence Goodby, Alex Orailoglu	Redundancy and testability in digital filter datapaths.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
9	Supratik Chakraborty, Kenneth Y. Yun, David L. Dill	Timing analysis of asynchronous systems using time separation of events.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
9	Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantin Halatsis	An Accumulator-Based BIST Approach for Two-Pattern Testing.	J. Electron. Test.	1999	DBLP DOI BibTeX RDF	stuck-open fault testing, built-in self test, delay fault testing, two-pattern testing
9	Antonis M. Paschalis, Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Yervant Zorian	An Effective BIST Architecture for Fast Multiplier Cores.	DATE	1999	DBLP DOI BibTeX RDF
9	Jaan Raik, Raimund Ubar	Sequential Circuit Test Generation Using Decision Diagram Models.	DATE	1999	DBLP DOI BibTeX RDF
9	Stefan Höreth, Rolf Drechsler	Formal Verification of Word-Level Specifications.	DATE	1999	DBLP DOI BibTeX RDF
9	Mike J. G. Lewis, Jim D. Garside, L. E. M. Brackenbury	Reconfigurable Latch Controllers for Low Power Asynchronous Circuits.	ASYNC	1999	DBLP DOI BibTeX RDF
9	Jon Tyler, Jeff Lent, Anh Mather, Huy Nguyen	AltiVecTM: bringing vector technology to the PowerPCTM processor family.	IPCCC	1999	DBLP DOI BibTeX RDF
9	François Pêcheux, Yannick Hervé	DIPS for MIPS: An Instrumented VHDL/Corba Kernel for Distributed Learning in EECS.	MSE	1999	DBLP DOI BibTeX RDF
9	Andrew A. Chien, Jay H. Byun	Safe and Protected Execution for the Morph/AMRM Reconfigurable Processor.	FCCM	1999	DBLP DOI BibTeX RDF	Multiprocess Protection, Process isolation, Machine Virtualization, Adaptive Computing, Reconfigurable Processor
9	Kei-Yong Khoo, Zhan Yu, Alan N. Willson Jr.	Bit-level arithmetic optimization for carry-save additions.	ICCAD	1999	DBLP DOI BibTeX RDF
9	Bulent Basaran, Kiran Ganesh, Raymond Y. K. Lau, Artour Levin, Miles McCoo, Srinivasan Rangarajan, Naresh Sehgal	GeneSys: A Leaf-Cell Layout Synthesis System for GHz VLSI Designs.	VLSI Design	1999	DBLP DOI BibTeX RDF
9	Avinash K. Gautam, Jagdish C. Rao, Rohit Rathi, H. Udayakumar	A Design-in Methodology to Ensure First Time Success of Complex Digital Signal Processors.	VLSI Design	1999	DBLP DOI BibTeX RDF
9	Ingrid Verbauwhede, Mihran Touriguian	A Low Power DSP Engine for Wireless Communications.	J. VLSI Signal Process.	1998	DBLP DOI BibTeX RDF
9	Thomas Müller-Wipperfürth, Richard Hagelauer	Graphical Entry of FSMDs Revisited: Putting Graphical Models on a Solid Base.	DATE	1998	DBLP DOI BibTeX RDF	FSMD, VHDL, Statecharts, Graphical Modelling
9	Wei Zhao, Christos A. Papachristou	Testing DSP Cores Based on Self-Test Programs.	DATE	1998	DBLP DOI BibTeX RDF
9	Isidoro Urriza, José Ignacio Artigas, José I. García-Nicolás, Luis Angel Barragan, Denis Navarro	VLSI Architecture for Lossless Compression of Medical Images Using the Discrete Wavelet Transform.	DATE	1998	DBLP DOI BibTeX RDF	DWT, VLSI architectures, Medical Image compression
9	José Carlos Alves, José Silva Matos	RVC - A Reconfigurable Coprocessor for Vector Processing Applications.	FCCM	1998	DBLP DOI BibTeX RDF
9	Apostolos Dollas, Euripides Sotiriades, Apostolos Emmanouelides	Architecture and Design of GE1, a FCCM for Golomb Ruler Derivation.	FCCM	1998	DBLP DOI BibTeX RDF	FPGA, Architecture, Custom, Golomb Ruler
9	Philip Heng Wai Leong, P. K. Tsang, T. K. Lee	A FPGA Based Forth Microprocessor.	FCCM	1998	DBLP DOI BibTeX RDF
9	Azeez J. Bhavnagarwala, Blanca Austin, James D. Meindl	Minimum supply voltage for bulk Si CMOS GSI.	ISLPED	1998	DBLP DOI BibTeX RDF
9	Miroslav N. Velev, Randal E. Bryant	Efficient Modeling of Memory Arrays in Symbolic Ternary Simulation.	TACAS	1998	DBLP DOI BibTeX RDF
9	Farzan Fallah, Srinivas Devadas, Kurt Keutzer	Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability.	DAC	1998	DBLP DOI BibTeX RDF	low power, synthesis, placement, flip-flops, voltage scaling, codec, MPEG4, level converters, design automatian
9	Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey	A Methodology for Guided Behavioral-Level Optimization.	DAC	1998	DBLP DOI BibTeX RDF	congestion, global routing, quadratic placement, routing models, supply-demand, relaxed pins
9	Patrick Schaumont, Bart Vanthournout, Ivo Bolsens, Hugo De Man	Synthesis of pipelined DSP accelerators with dynamic scheduling.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
9	Johannes Kneip, Mladen Berekovic, Jens Peter Wittenburg, Willm Hinrichs, Peter Pirsch	An Algorithm Adapted Autonomous Controlling Concept for a Parallel Single-Chip Digital Signal Processor.	J. VLSI Signal Process.	1997	DBLP DOI BibTeX RDF
9	Corinna G. Lee, Derek J. DeVries	Initial Results on the Performance and Cost of Vector Microprocessors.	MICRO	1997	DBLP DOI BibTeX RDF
9	Carl Ebeling, Darren C. Cronquist, Paul Franklin, Jason Secosky, Stefan G. Berg	Mapping applications to the RaPiD configurable architecture.	FCCM	1997	DBLP DOI BibTeX RDF
9	Hans M. Jacobson, Ganesh Gopalakrishnan	Asynchronous Microengines for Efficient High-level Control.	ARVLSI	1997	DBLP DOI BibTeX RDF	asynchronous circuits, microprogramming, self-timing
9	Tomás Lang, Elisardo Antelo	CORDIC-based computation of arccos and arcsin.	ASAP	1997	DBLP DOI BibTeX RDF
9	Debashis Bhattacharya, Smith Freeman, Bill Lin 0002	Optimizing Test Hardware for At-Speed Testing of Datapaths in an Integrated Circuit.	VLSI Design	1997	DBLP DOI BibTeX RDF
9	Pradip K. Jha, Nikil D. Dutt	High-level library mapping for arithmetic components.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
9	Ravichandran Ramachandran, Shih-Lien Lu	Efficient arithmetic using self-timing.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
9	En-Shou Chang, Daniel Gajski, Sanjiv Narayan	An optimal clock period selection method based on slack minimization criteria.	ACM Trans. Design Autom. Electr. Syst.	1996	DBLP DOI BibTeX RDF	clock slack, scheduling, performance estimation, clock period
9	Saman Adham, Sanjay Gupta	DP-BIST: A Built-In Self Test For DSP DataPaths A Low Overhead and High Fault Coverage Technique.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
9	Tommy King-Yin Cheung, Graham R. Hellestrand, Prasert Kanthamanon	A Multi-Level Transformation Approach to HW/SW Codesign: A Case Study.	CODES	1996	DBLP DOI BibTeX RDF	Design Transformations, Functional Languages
9	Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh 0001	Low power realization of FIR filters using multirate architectures.	VLSI Design	1996	DBLP DOI BibTeX RDF	low power realization, multirate architectures, computationally efficient implementations, power dissipation reduction, dedicated ASIC implementation, TMS320C2x/C5x programmable DSP, computational complexity, computational complexity, application specific integrated circuits, power analysis, digital filters, FIR filters, FIR filters, digital signal processing chips
9	Tom Lovett, Russell M. Clapp	STiNG: A CC-NUMA Computer System for the Commercial Marketplace.	ISCA	1996	DBLP DOI BibTeX RDF
9	Paul E. Landman, Jan M. Rabaey	Architectural power analysis: The dual bit type method.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
9	Anantha P. Chandrakasan, Miodrag Potkonjak, Renu Mehra, Jan M. Rabaey, Robert W. Brodersen	Optimizing power using transformations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
9	D. K. Arvind 0001, Robert D. Mullins, Vinod E. F. Rebello	Micronets: a model for decentralising control in asynchronous processor architectures.	ASYNC	1995	DBLP DOI BibTeX RDF	decentralising control, asynchronous processor architectures, micronets, communicating resources, four-phase protocol, hazard avoidance mechanisms, SPICE-level simulations, computer architecture, computer architecture, pipeline processing, processor architectures, fine-grain concurrency
9	J. Arjun Prabhu, Gregory B. Zyner	167 MHz Radix-8 Divide and Square Root Using Overlapped Radix-2 Stages.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF
9	Robert B. Jones, David L. Dill, Jerry R. Burch	Efficient validity checking for processor verification.	ICCAD	1995	DBLP DOI BibTeX RDF	formal verification, validation, decision procedure, uninterpreted functions, microprocessor architecture
9	Rahul Razdan, Michael D. Smith 0001	A high-performance microarchitecture with hardware-programmable functional units.	MICRO	1994	DBLP DOI BibTeX RDF	automatic instruction set design, compile-time optimization, general-purpose microarchitectures, logic synthesis, programmable logic
9	R. Milikowski, Willem G. Vree	Non-homogeneous Parallel Memory Operations in a VLIW Machine.	CONPAR	1994	DBLP DOI BibTeX RDF
9	Heinz-Josef Eikerling, Ralf Hunstock, Raul Camposano	Optimization of hierarchical designs using partitioning and resynthesis.	ICCAD	1994	DBLP DOI BibTeX RDF
9	Sanjay Gupta, Janusz Rajski, Jerzy Tyszer	Test pattern generation based on arithmetic operations.	ICCAD	1994	DBLP DOI BibTeX RDF
9	Joseph Varghese, Michael Butts, Jon Batcheller	An efficient logic emulation system.	IEEE Trans. Very Large Scale Integr. Syst.	1993	DBLP DOI BibTeX RDF
9	Abhijit Ghosh, Srinivas Devadas, A. Richard Newton	Sequential test generation and synthesis for testability at the register-transfer and logic levels.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF