Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
9 | Dmitry Ponomarev 0001, Gurhan Kucuk, Kanad Ghose |
AccuPower: An Accurate Power Estimation Tool for Superscalar Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 124-129, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Marcos Ferretti, Peter A. Beerel |
Single-Track Asynchronous Pipeline Templates Using 1-of-N Encoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 1008-1015, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | José M. Mendías, Román Hermida, María C. Molina, Olga Peñalba |
Efficient Verification of Scheduling, Allocation and Binding in High-Level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), Systems-on-Chip, 4-6 September 2002, Dortmund, Germany, pp. 308-315, 2002, IEEE Computer Society, 0-7695-1790-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Oswaldo Cadenas, Graham M. Megson |
A Clocking Technique with Power Savings in Virtex-Based Pipelined Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 322-331, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Dmitry Cheresiz, Ben H. H. Juurlink, Stamatis Vassiliadis, Harry A. G. Wijshoff |
Performance Scalability of Multimedia Instruction Set Extensions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2002, Parallel Processing, 8th International Euro-Par Conference Paderborn, Germany, August 27-30, 2002, Proceedings, pp. 849-860, 2002, Springer, 3-540-44049-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Aristidis Sotiropoulos, Georgios Tsoukalas, Nectarios Koziris |
Enhancing the Performance of Tiled Loop Execution onto Clusters Using Memory Mapped Network Interfaces and Pipelined Schedules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 15-19 April 2002, Fort Lauderdale, FL, USA, CD-ROM/Abstracts Proceedings, 2002, IEEE Computer Society, 0-7695-1573-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Memory Mapped Interfaces, Zero-Copy Protocols, DMA transfers, Loop Tiling, Communication Overlapping |
9 | Carles Rodoreda Sala, Natalino G. Busá |
A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan, pp. 44-49, 2002, ACM / IEEE Computer Society, 1-58113-576-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
VLIW processors, reconfigurable logic, architectural synthesis |
9 | Juan Carlos López 0001, Fernando Rincón, Francisco Moya, José Manuel Moya |
Improving Embedded System Design by Means of HW-SW Compilation on Reconfigurable Coprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan, pp. 255-260, 2002, ACM / IEEE Computer Society, 1-58113-576-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
reconfigurable datapaths, hardware-software codesign |
9 | Chao Huang, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha |
High-level synthesis of distributed logic-memory architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 564-571, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Weiping Liao, Joseph M. Basile, Lei He 0001 |
Leakage power modeling and reduction with data retention. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 714-719, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Maria Athanasaki, Aristidis Sotiropoulos, Georgios Tsoukalas, Nectarios Koziris |
A Pipelined Execution of Tiled Nested Loops on SMPs with Computation and Communication Overlapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP Workshops ![In: 31st International Conference on Parallel Processing Workshops (ICPP 2002 Workshops), 20-23 August 2002, Vancouver, BC, Canada, pp. 559-567, 2002, IEEE Computer Society, 0-7695-1680-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Karim Ben Chehida, Michel Auguin |
HW / SW partitioning approach for reconfigurable system design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2002, Greenoble, France, October 8-11, 2002, pp. 247-251, 2002, ACM, 1-58113-575-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
genetic algorithm, clustering, dynamic reconfiguration, codesign, HW/SW partitioning |
9 | Oguz Ergin, Kanad Ghose, Gurhan Kucuk, Dmitry Ponomarev 0001 |
A Circuit-Level Implementation of Fast, Energy-Efficient CMOS Comparators for High-Performance Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings, pp. 118-121, 2002, IEEE Computer Society, 0-7695-1700-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Hyun-Gyu Kim, Hyeong-Cheol Oh |
Efficient Hardware Multiplicative Inverters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICISC ![In: Information Security and Cryptology - ICISC 2002, 5th International Conference Seoul, Korea, November 28-29, 2002, Revised Papers, pp. 313-326, 2002, Springer, 3-540-00716-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Koji Ohashi, Mineo Kaneko |
Heuristic assignment-driven scheduling for data-path synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 703-706, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Chang Yong Kang, Earl E. Swartzlander Jr. |
An Analysis of the CORDIC Algorithm for Direct Digital Frequency Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 13th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2002), 17-19 July 2002, San Jose, CA, USA, pp. 111-119, 2002, IEEE Computer Society, 0-7695-1712-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Anna Antola, Mariagiovanna Sami, Vincenzo Piuri |
On-line Diagnosis and Reconfiguration of FPGA Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 1st IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002), 29-31 January 2002, Christchurch, New Zealand, pp. 291-296, 2002, IEEE Computer Society, 0-7695-1453-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
on-line detection, fault tolerance, FPGA, reconfiguration, diagnosis |
9 | Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten Schwan, Richard West |
Architecture and Hardware for Scheduling Gigabit Packet Streams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hot Interconnects ![In: 10th Annual IEEE Symposium on High Performance Interconnects (HOTIC 2002), August 21 - 23, 2002, Stanford, CA, USA, pp. 52-64, 2002, IEEE Computer Society, 0-7695-1650-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
9 | Tomás Bautista, Antonio Núñez |
Quantitative study of the impact of design and synthesis options on processor core performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(3), pp. 461-473, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
9 | Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Wu Ye |
Influence of compiler optimizations on system power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(6), pp. 801-804, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
9 | Oliver Chiu-sing Choy, Jan Butas, Juraj Povazanec, Cheong-Fat Chan |
A New Control Circuit for Asynchronous Micropipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(9), pp. 992-997, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
zero-overhead, dual-rail coding, Asynchronous design, micropipeline |
9 | HyungWon Kim 0001, John P. Hayes |
Realization-independent ATPG for designs with unimplemented blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(2), pp. 290-306, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
9 | Sanghun Park, Kiyoung Choi |
Performance-driven high-level synthesis with bit-level chaining andclock selection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(2), pp. 199-212, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
9 | Ben H. H. Juurlink, Stamatis Vassiliadis, Dmitri Tcheressiz, Harry A. G. Wijshoff |
Implementation and Evaluation of the Complex Streamed Instruction Set. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001), 8-12 September 2001, Barcelona, Spain, pp. 73-82, 2001, IEEE Computer Society, 0-7695-1363-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
9 | Reiner W. Hartenstein |
Reconfigurable Computing: A New Business Model and its Impact on SoC Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 4-6 September 2001, Warsaw, Poland, pp. 103-111, 2001, IEEE Computer Society, 0-7695-1239-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
9 | W. J. Bainbridge, Stephen B. Furber |
Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 11-14 March 2001, Salt Lake City, UT, USA, pp. 118-126, 2001, IEEE Computer Society, 0-7695-1034-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
9 | Mei-Yun Hsu, Hao-Chieh Chang, Yi-Chu Wang, Liang-Gee Chen |
Scalable module-based architecture for MPEG-4 BMA motion estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 245-248, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
9 | Seongmoo Heo, Ronny Krashinsky, Krste Asanovic |
Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 19th Conference on Advanced Research in VLSI (ARVLSI 2001), 14-16 March 2001, Salt Lake City, UT, USA, pp. 59-74, 2001, IEEE Computer Society, 0-7695-1037-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
9 | Sheng Sun, Larry McMurchie, Carl Sechen |
A High-Performance 64-bit Adder Implemented in Output Prediction Logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 19th Conference on Advanced Research in VLSI (ARVLSI 2001), 14-16 March 2001, Salt Lake City, UT, USA, pp. 213-223, 2001, IEEE Computer Society, 0-7695-1037-X. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
9 | Azeez J. Bhavnagarwala, Blanca Austin, Keith A. Bowman, James D. Meindl |
A minimum total power methodology for projecting limits on CMOS GSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(3), pp. 235-251, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
9 | Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian |
Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(10), pp. 1083-1099, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Sequential fault modeling, test pattern generation, robust testing, iterative logic arrays |
9 | Tomás Lang, Elisardo Antelo |
CORDIC-Based Computation of ArcCos. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 25(1), pp. 19-38, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
9 | Shiro Kobayashi, Gerhard P. Fettweis |
A Hierarchical Block-Floating-Point Arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 24(1), pp. 19-30, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
9 | Michael Münch, Norbert Wehn, Bernd Wurth, Renu Mehra, Jim Sproch |
Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 624-631, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
9 | Jens Schönherr, Bernd Straube |
Automatic Equivalence Check of Circuit Descriptions at Clocked Algorithmic and Register Transfer Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 759, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
9 | Xianfeng Zhou, Margaret Martonosi |
Augmenting Modern Superscalar Architectures with Configurable Extended Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS Workshops ![In: Parallel and Distributed Processing, 15 IPDPS 2000 Workshops, Cancun, Mexico, May 1-5, 2000, Proceedings, pp. 941-950, 2000, Springer, 3-540-67442-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
9 | R. Anand, Margarida F. Jacome, Gustavo de Veciana |
Heuristic tradeoffs between latency and energy consumption in register assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Eighth International Workshop on Hardware/Software Codesign, CODES 2000, San Diego, California, USA, 2000, pp. 115-119, 2000, ACM, 1-58113-268-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
9 | Henry Styles, Wayne Luk |
Customizing Graphics Applications: Techniques and Programming Interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 17-19 April 2000, Napa Valley, CA, USA, Proceedings, pp. 77-90, 2000, IEEE Computer Society, 0-7695-0871-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
9 | Cameron Patterson |
High Performance DES Encryption in Virtex(tm) FPGAs Using Jbits(tm). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 17-19 April 2000, Napa Valley, CA, USA, Proceedings, pp. 113-121, 2000, IEEE Computer Society, 0-7695-0871-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
9 | Pedro C. Diniz, Joonseok Park |
Automatic Synthesis of Data Storage and Control Structures for FPGA-Based Computing Engines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 17-19 April 2000, Napa Valley, CA, USA, Proceedings, pp. 91-100, 2000, IEEE Computer Society, 0-7695-0871-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
FPGA-based reconfigurable computing architectures, data queues, compilation, program analysis |
9 | Michael J. Wirthlin, Steve Morrison, Paul S. Graham, Brian Bray |
Improving the Performance and Efficiency of an Adaptive Amplification Operation Using Configurable Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 17-19 April 2000, Napa Valley, CA, USA, Proceedings, pp. 267-278, 2000, IEEE Computer Society, 0-7695-0871-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
9 | Natalino G. Busá, Albert van der Werf, Marco Bekooij |
Scheduling Coarse-Grain Operations for VLIW Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 13th International Symposium on System Synthesis, ISSS'00, Madrid, Spain, September 20-22, 2000., pp. 47-54, 2000, ACM / IEEE Computer Society, 0-7695-0765-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
9 | Kamal S. Khouri, Niraj K. Jha |
Leakage Power Analysis and Reduction during Behavioral Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 561-564, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
9 | Larry McMurchie, Su Kio, Gin Yee, Tyler Thorp, Carl Sechen |
Output Prediction Logic: A High-Performance CMOS Design Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 247-254, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
9 | Gin Yee, Tyler Thorp, Ron Christopherson, Ban P. Wang, Carl Sechen |
An Automated Shielding Algorithm and Tool For Dynamic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 1st International Symposium on Quality of Electronic Design (ISQED 2000), 20-22 March 2000, San Jose, CA, USA, pp. 369-374, 2000, IEEE Computer Society, 0-7695-0525-2. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
9 | Mark D. Aagaard, Robert B. Jones, Thomas F. Melham, John W. O'Leary, Carl-Johan H. Seger |
A Methodology for Large-Scale Hardware Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FMCAD ![In: Formal Methods in Computer-Aided Design, Third International Conference, FMCAD 2000, Austin, Texas, USA, November 1-3, 2000, Proceedings, pp. 263-282, 2000, Springer, 3-540-41219-0. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
9 | Russell E. Henning, Chaitali Chakrabarti |
Relating Data Characteristics to Transition Activity in High-Level Static CMOS Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 13th International Conference on VLSI Design (VLSI Design 2000), 4-7 January 2000, Calcutta, India, pp. 38-43, 2000, IEEE Computer Society, 0-7695-0487-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
statistical parameters, high-level synthesis, Low power design, data models, transition activity |
9 | Cameron Patterson |
A Dynamic FPGA Implementation of the Serpent Block Cipher. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHES ![In: Cryptographic Hardware and Embedded Systems - CHES 2000, Second International Workshop, Worcester, MA, USA, August 17-18, 2000, Proceedings, pp. 141-155, 2000, Springer, 3-540-41455-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
9 | Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Hyun Suk Kim, Wu Ye |
Energy-driven integrated hardware-software optimizations using SimplePower. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 27th International Symposium on Computer Architecture (ISCA 2000), June 10-14, 2000, Vancouver, BC, Canada, pp. 95-106, 2000, IEEE Computer Society, 978-1-58113-232-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
energy optimization and estimation, energy simulator, hardware-software interaction, system energy, compiler optimizations, low-power architectures |
9 | Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Wu Ye |
Influence of compiler optimizations on system power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 304-307, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
9 | William J. Dally, Andrew Chang 0001 |
The role of custom design in ASIC Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 643-647, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
9 | Laurence Goodby, Alex Orailoglu |
Redundancy and testability in digital filter datapaths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(5), pp. 631-644, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | Supratik Chakraborty, Kenneth Y. Yun, David L. Dill |
Timing analysis of asynchronous systems using time separation of events. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(8), pp. 1061-1076, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Nikolos, Constantin Halatsis |
An Accumulator-Based BIST Approach for Two-Pattern Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 15(3), pp. 267-278, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
stuck-open fault testing, built-in self test, delay fault testing, two-pattern testing |
9 | Antonis M. Paschalis, Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Yervant Zorian |
An Effective BIST Architecture for Fast Multiplier Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 117-121, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | Jaan Raik, Raimund Ubar |
Sequential Circuit Test Generation Using Decision Diagram Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 736-740, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | Stefan Höreth, Rolf Drechsler |
Formal Verification of Word-Level Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 52-57, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | Mike J. G. Lewis, Jim D. Garside, L. E. M. Brackenbury |
Reconfigurable Latch Controllers for Low Power Asynchronous Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 19-22 April 1999, Barcelona, Spain, pp. 27-35, 1999, IEEE Computer Society, 0-7695-0031-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | Jon Tyler, Jeff Lent, Anh Mather, Huy Nguyen |
AltiVecTM: bringing vector technology to the PowerPCTM processor family. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPCCC ![In: Proceedings of the IEEE International Performance Computing and Communications Conference, IPCCC 1999, Phoenix/Scottsdale, Arizona, USA, 10-12 February 1999, pp. 437-444, 1999, IEEE, 0-7803-5258-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | François Pêcheux, Yannick Hervé |
DIPS for MIPS: An Instrumented VHDL/Corba Kernel for Distributed Learning in EECS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: IEEE International Conference on Microelectronic Systems Education, MSE 1999, Arlington, Virginia, USA, July 19-21, 1999, pp. 30-31, 1999, IEEE Computer Society, 0-7695-0312-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | Andrew A. Chien, Jay H. Byun |
Safe and Protected Execution for the Morph/AMRM Reconfigurable Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 21-23 April 1999, Napa, CA, USA, pp. 209-221, 1999, IEEE Computer Society, 0-7695-0375-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Multiprocess Protection, Process isolation, Machine Virtualization, Adaptive Computing, Reconfigurable Processor |
9 | Kei-Yong Khoo, Zhan Yu, Alan N. Willson Jr. |
Bit-level arithmetic optimization for carry-save additions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999, San Jose, California, USA, November 7-11, 1999, pp. 14-19, 1999, IEEE Computer Society, 0-7803-5832-5. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | Bulent Basaran, Kiran Ganesh, Raymond Y. K. Lau, Artour Levin, Miles McCoo, Srinivasan Rangarajan, Naresh Sehgal |
GeneSys: A Leaf-Cell Layout Synthesis System for GHz VLSI Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India, pp. 448-452, 1999, IEEE Computer Society, 0-7695-0013-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | Avinash K. Gautam, Jagdish C. Rao, Rohit Rathi, H. Udayakumar |
A Design-in Methodology to Ensure First Time Success of Complex Digital Signal Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India, pp. 346-349, 1999, IEEE Computer Society, 0-7695-0013-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
9 | Ingrid Verbauwhede, Mihran Touriguian |
A Low Power DSP Engine for Wireless Communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 18(2), pp. 177-186, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
9 | Thomas Müller-Wipperfürth, Richard Hagelauer |
Graphical Entry of FSMDs Revisited: Putting Graphical Models on a Solid Base. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 931-932, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
FSMD, VHDL, Statecharts, Graphical Modelling |
9 | Wei Zhao, Christos A. Papachristou |
Testing DSP Cores Based on Self-Test Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 166-172, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
9 | Isidoro Urriza, José Ignacio Artigas, José I. García-Nicolás, Luis Angel Barragan, Denis Navarro |
VLSI Architecture for Lossless Compression of Medical Images Using the Discrete Wavelet Transform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 196-201, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
DWT, VLSI architectures, Medical Image compression |
9 | José Carlos Alves, José Silva Matos |
RVC - A Reconfigurable Coprocessor for Vector Processing Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 15-17 April 1998, Napa Valley, CA, USA, pp. 258-259, 1998, IEEE Computer Society, 0-8186-8900-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
9 | Apostolos Dollas, Euripides Sotiriades, Apostolos Emmanouelides |
Architecture and Design of GE1, a FCCM for Golomb Ruler Derivation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 15-17 April 1998, Napa Valley, CA, USA, pp. 48-56, 1998, IEEE Computer Society, 0-8186-8900-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
FPGA, Architecture, Custom, Golomb Ruler |
9 | Philip Heng Wai Leong, P. K. Tsang, T. K. Lee |
A FPGA Based Forth Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 15-17 April 1998, Napa Valley, CA, USA, pp. 254-255, 1998, IEEE Computer Society, 0-8186-8900-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
9 | Azeez J. Bhavnagarwala, Blanca Austin, James D. Meindl |
Minimum supply voltage for bulk Si CMOS GSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998, Monterey, California, USA, August 10-12, 1998, pp. 100-102, 1998, ACM, 1-58113-059-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
9 | Miroslav N. Velev, Randal E. Bryant |
Efficient Modeling of Memory Arrays in Symbolic Ternary Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TACAS ![In: Tools and Algorithms for Construction and Analysis of Systems, 4th International Conference, TACAS '98, Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS'98, Lisbon, Portugal, March 28 - April 4, 1998, Proceedings, pp. 136-150, 1998, Springer, 3-540-64356-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
9 | Farzan Fallah, Srinivas Devadas, Kurt Keutzer |
Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 528-533, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
low power, synthesis, placement, flip-flops, voltage scaling, codec, MPEG4, level converters, design automatian |
9 | Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey |
A Methodology for Guided Behavioral-Level Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 309-314, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
congestion, global routing, quadratic placement, routing models, supply-demand, relaxed pins |
9 | Patrick Schaumont, Bart Vanthournout, Ivo Bolsens, Hugo De Man |
Synthesis of pipelined DSP accelerators with dynamic scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 5(1), pp. 59-68, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
9 | Johannes Kneip, Mladen Berekovic, Jens Peter Wittenburg, Willm Hinrichs, Peter Pirsch |
An Algorithm Adapted Autonomous Controlling Concept for a Parallel Single-Chip Digital Signal Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 16(1), pp. 31-40, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
9 | Corinna G. Lee, Derek J. DeVries |
Initial Results on the Performance and Cost of Vector Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 171-182, 1997, ACM/IEEE Computer Society, 0-8186-7977-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
9 | Carl Ebeling, Darren C. Cronquist, Paul Franklin, Jason Secosky, Stefan G. Berg |
Mapping applications to the RaPiD configurable architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 5th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97), 16-18 April 1997, Napa Valley, CA, USA, pp. 106-115, 1997, IEEE Computer Society, 0-8186-8159-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
9 | Hans M. Jacobson, Ganesh Gopalakrishnan |
Asynchronous Microengines for Efficient High-level Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 17th Conference on Advanced Research in VLSI (ARVLSI '97), September 15-16, 1997, Ann Arbor, MI, USA, pp. 201-218, 1997, IEEE Computer Society, 0-8186-7913-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
asynchronous circuits, microprogramming, self-timing |
9 | Tomás Lang, Elisardo Antelo |
CORDIC-based computation of arccos and arcsin. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1997 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '97), 14-16 July 1997, Zurich, Switzerland, pp. 132-143, 1997, IEEE Computer Society, 0-8186-7958-1. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
9 | Debashis Bhattacharya, Smith Freeman, Bill Lin 0002 |
Optimizing Test Hardware for At-Speed Testing of Datapaths in an Integrated Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 289-296, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
9 | Pradip K. Jha, Nikil D. Dutt |
High-level library mapping for arithmetic components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 4(2), pp. 157-169, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
9 | Ravichandran Ramachandran, Shih-Lien Lu |
Efficient arithmetic using self-timing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 4(4), pp. 445-454, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
9 | En-Shou Chang, Daniel Gajski, Sanjiv Narayan |
An optimal clock period selection method based on slack minimization criteria. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 1(3), pp. 352-370, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
clock slack, scheduling, performance estimation, clock period |
9 | Saman Adham, Sanjay Gupta |
DP-BIST: A Built-In Self Test For DSP DataPaths A Low Overhead and High Fault Coverage Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 5th Asian Test Symposium (ATS '96), November 20-22, 1996, Hsinchu, Taiwan, pp. 205-212, 1996, IEEE Computer Society, 0-8186-7478-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
9 | Tommy King-Yin Cheung, Graham R. Hellestrand, Prasert Kanthamanon |
A Multi-Level Transformation Approach to HW/SW Codesign: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES ![In: Proceedings of the Forth International Workshop on Hardware/Software Codesign, CODES 1996, Pittsburgh, PA, USA, March 18-20, 1996, pp. 10-17, 1996, IEEE Computer Society, 0-8186-7243-9. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Design Transformations, Functional Languages |
9 | Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh 0001 |
Low power realization of FIR filters using multirate architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 9th International Conference on VLSI Design (VLSI Design 1996), 3-6 January 1996, Bangalore, India, pp. 370-375, 1996, IEEE Computer Society, 0-8186-7228-5. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
low power realization, multirate architectures, computationally efficient implementations, power dissipation reduction, dedicated ASIC implementation, TMS320C2x/C5x programmable DSP, computational complexity, computational complexity, application specific integrated circuits, power analysis, digital filters, FIR filters, FIR filters, digital signal processing chips |
9 | Tom Lovett, Russell M. Clapp |
STiNG: A CC-NUMA Computer System for the Commercial Marketplace. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 23rd Annual International Symposium on Computer Architecture, Philadelphia, PA, USA, May 22-24, 1996, pp. 308-317, 1996, ACM, 0-89791-786-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
9 | Paul E. Landman, Jan M. Rabaey |
Architectural power analysis: The dual bit type method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 3(2), pp. 173-187, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
9 | Anantha P. Chandrakasan, Miodrag Potkonjak, Renu Mehra, Jan M. Rabaey, Robert W. Brodersen |
Optimizing power using transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(1), pp. 12-31, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
9 | D. K. Arvind 0001, Robert D. Mullins, Vinod E. F. Rebello |
Micronets: a model for decentralising control in asynchronous processor architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: Second Working Conference on Asynchronous Design Methodologies, May 30-31, 1995, London, England, UK, pp. 190-199, 1995, IEEE Computer Society, 0-8186-7098-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
decentralising control, asynchronous processor architectures, micronets, communicating resources, four-phase protocol, hazard avoidance mechanisms, SPICE-level simulations, computer architecture, computer architecture, pipeline processing, processor architectures, fine-grain concurrency |
9 | J. Arjun Prabhu, Gregory B. Zyner |
167 MHz Radix-8 Divide and Square Root Using Overlapped Radix-2 Stages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 12th Symposium on Computer Arithmetic (ARITH-12 '95), July 19-21, 1995, Bath, England, UK, pp. 155-162, 1995, IEEE Computer Society, 0-8186-7089-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
9 | Robert B. Jones, David L. Dill, Jerry R. Burch |
Efficient validity checking for processor verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 2-6, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
formal verification, validation, decision procedure, uninterpreted functions, microprocessor architecture |
9 | Rahul Razdan, Michael D. Smith 0001 |
A high-performance microarchitecture with hardware-programmable functional units. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30 - December 2, 1994, pp. 172-180, 1994, ACM / IEEE Computer Society, 0-89791-707-3. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
automatic instruction set design, compile-time optimization, general-purpose microarchitectures, logic synthesis, programmable logic |
9 | R. Milikowski, Willem G. Vree |
Non-homogeneous Parallel Memory Operations in a VLIW Machine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONPAR ![In: Parallel Processing: CONPAR 94 - VAPP VI, Third Joint International Conference on Vector and Parallel Processing, Linz, Austria, September 6-8, 1994, Proceedings, pp. 485-496, 1994, Springer, 3-540-58430-7. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
9 | Heinz-Josef Eikerling, Ralf Hunstock, Raul Camposano |
Optimization of hierarchical designs using partitioning and resynthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 707-712, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
9 | Sanjay Gupta, Janusz Rajski, Jerzy Tyszer |
Test pattern generation based on arithmetic operations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 117-124, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
9 | Joseph Varghese, Michael Butts, Jon Batcheller |
An efficient logic emulation system. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 1(2), pp. 171-174, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
9 | Abhijit Ghosh, Srinivas Devadas, A. Richard Newton |
Sequential test generation and synthesis for testability at the register-transfer and logic levels. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(5), pp. 579-598, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|