Search results for "pipeline"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
11	Anh Tuan Hoang, Katsuhiro Yamazaki, Shigeru Oyanagi	Multi-stage Pipelining MD5 Implementations on FPGA with Data Forwarding.	FCCM	2008	DBLP DOI BibTeX RDF
11	Hua Bai, Lixin Gao	A Vague Sets Based Hierarchical Synthetic Evaluation Algorithm for Health Condition Assessment.	ICIC (1)	2008	DBLP DOI BibTeX RDF	hierarchical synthetic evaluation algorithm, health condition, multi-source information fusion, vague sets
11	Manjunath Kudlur, Scott A. Mahlke	Orchestrating the execution of stream programs on multicore platforms.	PLDI	2008	DBLP DOI BibTeX RDF	multicore, software pipelining, cell processor, stream programming, streamit
11	B. V. N. Silpa, Anjul Patney, Tushar Krishna, Preeti Ranjan Panda, G. S. Visweswaran	Texture filter memory: a power-efficient and scalable texture memory architecture for mobile graphics processors.	ICCAD	2008	DBLP DOI BibTeX RDF
11	Shengyuan Jiang, Xudong Jiang, Jie Lu, Jianyong Li, Xiangyan Lv	Research on a Tri-axial Differential-Drive In-Pipe Robot.	ICIRA (1)	2008	DBLP DOI BibTeX RDF	in-pipe robot, elbow, differential drive, tri-axial differential mechanism
11	Michal Plotkowiak, Blanca Rodríguez, Gernot Plank, Jürgen E. Schneider, David Gavaghan, Peter Kohl, Vicente Grau	High Performance Computer Simulations of Cardiac Electrical Function Based on High Resolution MRI Datasets.	ICCS (1)	2008	DBLP DOI BibTeX RDF
11	Takeshi Sugawara 0001, Naofumi Homma, Takafumi Aoki, Akashi Satoh	Compact ASIC Architectures for the 512-Bit Hash Function Whirlpool.	WISA	2008	DBLP DOI BibTeX RDF	Hash function, Hardware architecture, Whirlpool, Cryptographic hardware
11	Jeff Pool, Anselmo Lastra, Montek Singh	Energy-precision tradeoffs in mobile Graphics Processing Units.	ICCD	2008	DBLP DOI BibTeX RDF
11	Hai Bing Yin, Xi Zhong Lou, Zhe Lei Xia, Wen Gao 0001	An efficient VLSI architecture for rate disdortion optimization in AVS video encoder.	ISCAS	2008	DBLP DOI BibTeX RDF
11	Tai-Hua Lu, Chung-Ho Chen, Kuen-Jong Lee	A hybrid self-testing methodology of processor cores.	ISCAS	2008	DBLP DOI BibTeX RDF
11	Xunying Zhang, Xubang Shen	A Power-Efficient Floating-Point Co-processor Design.	CSSE (4)	2008	DBLP DOI BibTeX RDF
11	Daniel P. Lopresti	Optical character recognition errors and their effects on natural language processing.	AND	2008	DBLP DOI BibTeX RDF	performance evaluation, optical character recognition, tokenization, part-of-speech tagging, sentence boundary detection
11	HongKee Moon, Auguste Genovesio	IM.Grid, a Grid computing approach for Image Mining of High Throughput-High Content Screening.	GRID	2008	DBLP DOI BibTeX RDF
11	Eui-Young Chung, Cheol Hong Kim, Sung Woo Chung	An Accurate and Energy-Efficient Way Determination Technique for Instruction Caches by Early Tab Matching.	DELTA	2008	DBLP DOI BibTeX RDF	way predictioin, low power, Instruction cache
11	Chung-Ho Chen, Chih-Kai Wei, Tai-Hua Lu, Hsun-Wei Gao	Software-Based Self-Testing With Multiple-Level Abstractions for Soft Processor Cores.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
11	Montek Singh, Steven M. Nowick	The Design of High-Performance Dynamic Asynchronous Pipelines: Lookahead Style.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
11	Lydia Ng, Sayan D. Pathak, Chihchau Kuan, Christopher Lau, Hong-wei Dong, Andrew Sodt, Chinh Dang, Brian B. Avants, Paul A. Yushkevich, James C. Gee, David R. Haynor, Ed S. Lein, Allan Jones, Michael Hawrylycz	Neuroinformatics for Genome-Wide 3-D Gene Expression Mapping in the Mouse Brain.	IEEE ACM Trans. Comput. Biol. Bioinform.	2007	DBLP DOI BibTeX RDF	Data mining, Information Visualization, Segmentation, Registration, Bioinformatics (genome or protein) databases
11	Kuizhi Mei, Nanning Zheng 0001, Chang Huang, Yuehu Liu, Qiang Zeng	VLSI Design of a High-Speed and Area-Efficient JPEG2000 Encoder.	IEEE Trans. Circuits Syst. Video Technol.	2007	DBLP DOI BibTeX RDF
11	Xinyu Zhang 0002, Young J. Kim	Interactive Collision Detection for Deformable Models Using Streaming AABBs.	IEEE Trans. Vis. Comput. Graph.	2007	DBLP DOI BibTeX RDF	AABB, Collision detection, deformable models, programmable graphics hardware, streaming computations
11	Cheng-Yi Xiong, Jin-Wen Tian, Jian Liu 0011	Efficient Architectures for Two-Dimensional Discrete Wavelet Transform Using Lifting Scheme.	IEEE Trans. Image Process.	2007	DBLP DOI BibTeX RDF
11	Stephen Roderick Hines, Gary S. Tyson, David B. Whalley	Addressing instruction fetch bottlenecks by using an instruction register file.	LCTES	2007	DBLP DOI BibTeX RDF	L0/filter cache, instruction packing, instruction register file
11	Neil Vachharajani, Ram Rangan, Easwaran Raman, Matthew J. Bridges, Guilherme Ottoni, David I. August	Speculative Decoupled Software Pipelining.	PACT	2007	DBLP DOI BibTeX RDF
11	Biörn Biörnstad, Cesare Pautasso	Let It Flow: Building Mashups with Data Processing Pipelines.	ICSOC Workshops	2007	DBLP DOI BibTeX RDF
11	Massimo Rovini, Giuseppe Gentile, Francesco Rossi, Luca Fanucci	A minimum-latency block-serial architecture of a decoder for IEEE 802.11n LDPC codes.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
11	Swaroop Ghosh, Swarup Bhunia, Kaushik Roy 0001	Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling.	DATE	2007	DBLP DOI BibTeX RDF
11	Qiang Zhu 0008, Aviral Shrivastava, Nikil D. Dutt	Interactive presentation: Functional and timing validation of partially bypassed processor pipelines.	DATE	2007	DBLP DOI BibTeX RDF
11	Benjamin C. Lee, David M. Brooks	Illustrative Design Space Studies with Microarchitectural Regression Models.	HPCA	2007	DBLP DOI BibTeX RDF
11	Paul Racunas, Kypros Constantinides, Srilatha Manne, Shubhendu S. Mukherjee	Perturbation-based Fault Screening.	HPCA	2007	DBLP DOI BibTeX RDF
11	Gurkan Koldas, Veysi Isler, Rynson W. H. Lau	Six Degrees of Freedom Incremental Occlusion Horizon Culling Method for Urban Environments.	ISVC (1)	2007	DBLP DOI BibTeX RDF
11	Mark J. Prusten	Motion picture production facility with liquid cooled 512 processor mobile super computing vehicle and virtual reality environment.	VRST	2007	DBLP DOI BibTeX RDF
11	Son Dao Trong, Martin S. Schmookler, Eric M. Schwarz, Michael Kroener	P6 Binary Floating-Point Unit.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF	denormal result handling, aggressive data forwarding, high-frequency design, data processing without stalls, Floating-point unit
11	Philip Garcia, Henry F. Korth	Pipelined hash-join on multithreaded architectures.	DaMoN	2007	DBLP DOI BibTeX RDF
11	Sheldon Andrews, Jochen Lang 0001	Interactive Scanning of Haptic Textures and Surface Compliance.	3DIM	2007	DBLP DOI BibTeX RDF
11	Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai	A low power VLIW processor generation method by means of extracting non-redundant activation conditions.	CODES+ISSS	2007	DBLP DOI BibTeX RDF	low power, ASIP, clock gating, VLIW processor
11	Andrew Danner, Thomas Mølhave, Ke Yi 0001, Pankaj K. Agarwal, Lars Arge, Helena Mitásová	TerraStream: from elevation data to watershed hierarchies.	GIS	2007	DBLP DOI BibTeX RDF	terrain modeling
11	Carlos D. Correa, Deborah Silver	Programmable shaders for deformation rendering.	Graphics Hardware	2007	DBLP DOI BibTeX RDF
11	Magnus Strengert, Thomas Klein, Thomas Ertl	A hardware-aware debugger for the OpenGL shading language.	Graphics Hardware	2007	DBLP DOI BibTeX RDF
11	Yong Dou, Jinbo Xu	FPGA-Accelerated Active Shape Model for Real-Time People Tracking.	Asia-Pacific Computer Systems Architecture Conference	2007	DBLP DOI BibTeX RDF	FPGA, Active Shape Model, People Tracking
11	Taehyun Rhee, John P. Lewis, Ulrich Neumann, Krishna S. Nayak	Soft-Tissue Deformation for In Vivo Volume Animation.	PG	2007	DBLP DOI BibTeX RDF
11	Moriyoshi Ohara, Hangu Yeo, Frank Savino, Giridharan Iyengar, Leiguang Gong, Hiroshi Inoue, Hideaki Komatsu, Vadim Sheinin, Shahrokh Daijavad	Accelerating Mutual-Information-Based Linear Registration on the Cell Broadband Engine Processor.	ICME	2007	DBLP DOI BibTeX RDF
11	Mathys Walma	Pipelined Cyclic Redundancy Check (CRC) Calculation.	ICCCN	2007	DBLP DOI BibTeX RDF
11	Haider Ali, Bashir M. Al-Hashimi	Architecture Level Power-Performance Tradeoffs for Pipelined Designs.	ISCAS	2007	DBLP DOI BibTeX RDF
11	Ramin Zanbaghi, Seyed Mojtaba Atarodi, Armin Tajalli	A Power Optimized Base-Band Circuitry for the Low-IF Receivers.	ISCAS	2007	DBLP DOI BibTeX RDF
11	Swaroop Ghosh, Patrick Ndai, Swarup Bhunia, Kaushik Roy 0001	Tolerance to Small Delay Defects by Adaptive Clock Stretching.	IOLTS	2007	DBLP DOI BibTeX RDF
11	Gao Shu, Nick J. Avis	Workflow-Based Distributed Visualization.	GCC	2007	DBLP DOI BibTeX RDF
11	Thomas Kottke, Andreas Steininger	A Fail-Silent Reconfigurable Superscalar Processor.	PRDC	2007	DBLP DOI BibTeX RDF
11	Nabil Hasasneh, Ian M. Bell, Chris R. Jesshope	High Level Modelling and Design For a Microthreaded Scheduler to Support Microgrids.	AICCSA	2007	DBLP DOI BibTeX RDF
11	Andrew D. Hilton, Amir Roth	Ginger: control independence using tag rewriting.	ISCA	2007	DBLP DOI BibTeX RDF	control independence, out-of-order renaming, selective re-dispatch, branch misprediction
11	Jiang Long, Andrew Seawright	Synthesizing SVA Local Variables for Formal Verification.	DAC	2007	DBLP DOI BibTeX RDF
11	Alexander J. Macdonald, David F. Brailsford, Steven R. Bagley, John William Lumley	Speculative document evaluation.	ACM Symposium on Document Engineering	2007	DBLP DOI BibTeX RDF	VDP, speculative evaluation, optimisation, SVG, document layout, PPML
11	Tae-Young Kim, Jongho Kim, Hyunmin Hur	A Unified Shader Based on the OpenGL ES 2.0 for 3D Mobile Game Development.	Edutainment	2007	DBLP DOI BibTeX RDF
11	Ming Zhang 0017, Subhasish Mitra, T. M. Mak, Norbert Seifert, Nicholas J. Wang, Quan Shi, Kee Sup Kim, Naresh R. Shanbhag, Sanjay J. Patel	Sequential Element Design With Built-In Soft Error Resilience.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
11	Athanasios Kakarountas, Haralambos Michail, Athanasios Milidonis, Costas E. Goutis, George Theodoridis	High-Speed FPGA Implementation of Secure Hash Algorithm for IPSec and VPN Applications.	J. Supercomput.	2006	DBLP DOI BibTeX RDF	high-speed performance, Security, FPGA, hash function, hardware implementation
11	Seong-Won Lee, Jean-Luc Gaudiot	Throttling-Based Resource Management in High Performance Multithreaded Architectures.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Resource management, power management, multithreading, resource utilization, throttling
11	Yijun Li, Magdy A. Bayoumi	A Three-Level Parallel High-Speed Low-Power Architecture for EBCOT of JPEG 2000.	IEEE Trans. Circuits Syst. Video Technol.	2006	DBLP DOI BibTeX RDF
11	Animesh Datta, Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy 0001	Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
11	David A. Ellsworth, Bryan Green, Chris Henze, Patrick J. Moran, Timothy Sandstrom	Concurrent Visualization in a Production Supercomputing Environment.	IEEE Trans. Vis. Comput. Graph.	2006	DBLP DOI BibTeX RDF	concurrent visualization, interactive visual computing, high temporal resolution visualization, GEOS4 global climate model, hurricane visualization, ECCO, ocean modeling, Supercomputing, time-varying data
11	Ming-Jung Seow, Vijayan K. Asari	Recurrent neural network as a linear attractor for pattern association.	IEEE Trans. Neural Networks	2006	DBLP DOI BibTeX RDF
11	Nicholas J. Wang, Sanjay J. Patel	ReStore: Symptom-Based Soft Error Detection in Microprocessors.	IEEE Trans. Dependable Secur. Comput.	2006	DBLP DOI BibTeX RDF	Simulation, fault tolerance, fault injection, redundant design
11	Shadrokh Samavi, Shahram Shirani, Nader Karimi	Real-time processing and compression of DNA microarray images.	IEEE Trans. Image Process.	2006	DBLP DOI BibTeX RDF
11	Sanghyun Park, Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek, Eugene Earlie	Bypass aware instruction scheduling for register file power reduction.	LCTES	2006	DBLP DOI BibTeX RDF	architecture-sensitive compiler, bypass-sensitive, forwarding paths, operation table, processor bypasses, reservation table, power consumption, register file
11	Sumeet Kumar, Aneesh Aggarwal	Self-checking instructions: reducing instruction redundancy for concurrent error detection.	PACT	2006	DBLP DOI BibTeX RDF	RISC/CISC, reducing instruction redundancy, redundant multi-threading, self-checking instructions, concurrent error detection, VLIW architectures
11	Jie S. Hu, Shuai Wang 0006, Sotirios G. Ziavras	In-Register Duplication: Exploiting Narrow-Width Value for Improving Register File Reliability.	DSN	2006	DBLP DOI BibTeX RDF
11	Xue-mi Zhao, Zhiying Wang 0003, Hongyi Lu, Kui Dai	A 6.35Mbps 1024-bit RSA crypto coprocessor in a 0.18um CMOS technology.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
11	Peter A. Beerel, Nam-Hoon Kim, Andrew Lines, Mike Davies	Slack Matching Asynchronous Designs.	ASYNC	2006	DBLP DOI BibTeX RDF
11	Hai Li 0001, Yiran Chen 0001, Kaushik Roy 0001, Cheng-Kok Koh	SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design.	ASP-DAC	2006	DBLP DOI BibTeX RDF
11	William N. Chelton, Mohammed Benaissa	High-Speed Pipelined EGG Processor on FPGA.	SiPS	2006	DBLP DOI BibTeX RDF
11	Christian Ferdinand, Florian Martin 0001, Christoph Cullmann, Marc Schlickling, Ingmar Stein, Stephan Thesing, Reinhold Heckmann	New Developments in WCET Analysis.	Program Analysis and Compilation	2006	DBLP DOI BibTeX RDF
11	Kishan Chand Gupta, Pradeep Kumar Mishra, Pinakpani Pal	A General Methodology for Pipelining the Point Multiplication Operation in Curve Based Cryptography.	ACNS	2006	DBLP DOI BibTeX RDF
11	Bok Dong Kim, Sang Ok Koo, Hyok Don Kwon, Seong Dae Jung, Soon Ki Jung, Minho Lee, YongWoo Rho, SungJa Koo	Integrated visualization for geometry PIG data.	APVIS	2006	DBLP DOI BibTeX RDF	features visualization, geometry PIG, multi-channel data, navigation, large data visualization
11	Gerhard Lienhart, Andreas Kugel, Reinhard Männer	Rapid development of high performance floating-point pipelines for scientific simulation.	IPDPS	2006	DBLP DOI BibTeX RDF
11	Takatoshi Ikeda, Fumihiko Ino, Kenichi Hagihara	A code motion technique for accelerating general-purpose computation on the GPU.	IPDPS	2006	DBLP DOI BibTeX RDF
11	Bernhard Fechner	Analysis of checksum-based execution schemes for pipelined processors.	IPDPS	2006	DBLP DOI BibTeX RDF
11	Yongfeng Gu, Tom Van Court, Martin C. Herbordt	Integrating FPGA Acceleration into the Protomol Molecular Dynamics Code: Preliminary Report.	FCCM	2006	DBLP DOI BibTeX RDF
11	K. Scott Hemmert, Keith D. Underwood	Open Source High Performance Floating-Point Modules.	FCCM	2006	DBLP DOI BibTeX RDF	IEEE floating point, FPGA, reconfigurable computing
11	Yousef El-Kurdi, Warren J. Gross, Dennis Giannacopoulos	Sparse Matrix-Vector Multiplication for Finite Element Method Matrices on FPGAs.	FCCM	2006	DBLP DOI BibTeX RDF
11		Multi-paradigm and Multi-grain Parallel Execution Model Based on SMP-Cluster.	John Vincent Atanasoff Symposium	2006	DBLP DOI BibTeX RDF
11	Abiola Oduguwa, Ashutosh Tiwari, S. Fiorentino, Rajkumar Roy	Multi-objective optimisation of the protein-ligand docking problem in drug discovery.	GECCO	2006	DBLP DOI BibTeX RDF	evolutionary computing, drug discovery, multi-objective optimisation, protein-ligand docking
11	Rastislav Lukac, Konstantinos N. Plataniotis	Cost-Effective Sharpening of Single-Sensor Camera Images.	ICME	2006	DBLP DOI BibTeX RDF
11	Hua Xiong, Haoyu Peng, Aihong Qin, Jiaoying Shi	Parallel occlusion culling on GPUs cluster.	VRCIA	2006	DBLP DOI BibTeX RDF	GPUs cluster, parallel rendering, occlusion culling, tiled display, immersive environments, cluster rendering
11	Greg Hoover, Forrest Brewer, Timothy Sherwood	Extensible control architectures.	CASES	2006	DBLP DOI BibTeX RDF	specification methodology, control architecture
11	Jin Lee, Sin-Chong Park, Sungchung Park	A pipelined VLSI architecture for a list sphere decoder.	ISCAS	2006	DBLP DOI BibTeX RDF
11	Mohammad Taherzadeh-Sani, Anas A. Hamoui	Digital background calibration of interstage-gain and capacitor-mismatch errors in pipelined ADCs.	ISCAS	2006	DBLP DOI BibTeX RDF
11	Mohammad Taherzadeh-Sani, Anas A. Hamoui	Analysis of dynamic element matching (DEM) in pipelined ADCs.	ISCAS	2006	DBLP DOI BibTeX RDF
11	Tae-Young Kim, Kyoung-Su Oh, Byeong-Seok Shin, Cheol-Su Lim	Programmable Vertex Processing Unit for Mobile Game Development.	ICEC	2006	DBLP DOI BibTeX RDF
11	Osama Daifallah Al-Khaleel, Christos A. Papachristou, Francis G. Wolff, Kiamal Z. Pekmestzi	A Large Scale Adaptable Multiplier for Cryptographic Applications.	AHS	2006	DBLP DOI BibTeX RDF
11	Christopher Zach, Mario Sormann, Konrad F. Karner	High-Performance Multi-View Reconstruction.	3DPVT	2006	DBLP DOI BibTeX RDF
11	Mythri Alle, Jayanta Biswas, S. K. Nandy 0001	High Performance VLSI Architecture Design for H.264 CAVLC Decoder.	ASAP	2006	DBLP DOI BibTeX RDF
11	Andrew Havlir, David Z. Pan	Simultaneous Statistical Delay and Slew Optimization for Interconnect Pipelines.	ISQED	2006	DBLP DOI BibTeX RDF
11	Raphael Fonte Boa, Alexandre Marques Amaral, Dulcinéia Oliveira da Penha, Carlos Augusto Paiva da Silva Martins, Petr Ekel	Parallel Image Segmentation in Reconfigurable Chip Multiprocessors.	ISPA Workshops	2006	DBLP DOI BibTeX RDF
11	Yuan-Long Jeang, Tzuu-Shaang Wey, Hung-Yu Wang, Chih-Chung Tai	A Single-Stream Pipelined Instruction Decompression System for Embedded Microprocessors.	IIH-MSP	2006	DBLP DOI BibTeX RDF
11	Mee Young Sung, Suk-Min Whang, Yonghee Yoo, Nam-Joong Kim, Jong Seung Park, Wonik Choi	Parallel Processing for Reducing the Bottleneck in Realtime Graphics Rendering.	PCM	2006	DBLP DOI BibTeX RDF	Realtime graphics rendering, Distribution of rendering operations, Optimization, Parallel processing, Multithreading, Bottleneck
11	Smitha Shyam, Kypros Constantinides, Sujay Phadke, Valeria Bertacco, Todd M. Austin	Ultra low-cost defect protection for microprocessor pipelines.	ASPLOS	2006	DBLP DOI BibTeX RDF	defect-protection, reliability, pipelines, low-cost
11	João Graça, Nuno J. Mamede, João D. Pereira	A Framework for Integrating Natural Language Tools.	PROPOR	2006	DBLP DOI BibTeX RDF
11	Yi-Chih Chao, Shih-Tse Wei, Jar-Ferr Yang, Bin-Da Liu	Combined CAVLC Decoder and Inverse Quantizer for Efficient H.264/AVC Decoding.	APCCAS	2006	DBLP DOI BibTeX RDF
11	Daehong Kim, Dongwan Shin, Kiyoung Choi	Pipelining with common operands for power-efficient linear systems.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
11	Emil Talpes, Diana Marculescu	Execution cache-based microarchitecture for power-efficient superscalar processors.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
11	Shanq-Jang Ruan, Kun-Lin Tsai, Edwin Naroska, Feipei Lai	Bipartitioning and encoding in low-power pipelined circuits.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	Low-power design
11	Ivano Barbieri, Massimo Bariani, Alberto Cabitto, Marco Raggio	A Simulation and Exploration Technology for Multimedia-Application-Driven Architectures.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	Hw-Sw co-design, simulation speed, simulation accuracy, simulation, multimedia, system on chip, DSP, flexibility, VLIW, architecture exploration, ISA
11	Fred A. Bower, Sule Ozev, Daniel J. Sorin	Autonomic Microprocessor Execution via Self-Repairing Arrays.	IEEE Trans. Dependable Secur. Comput.	2005	DBLP DOI BibTeX RDF	Logic design reliability and testing, microprocessors and microcomputers