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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 75 occurrences of 42 keywords
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Results
Found 70 publication records. Showing 70 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
125 | Rei-Fu Huang, Chao-Hsun Chen, Cheng-Wen Wu |
Economic Aspects of Memory Built-in Self-Repair. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(2), pp. 164-172, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
BIRA, BIST, yield, overhead, economic models, BISR, redundancy analysis, built-in self-repair |
84 | Yu-Ying Hsiao, Chao-Hsun Chen, Cheng-Wen Wu |
A Built-In Self-Repair Scheme for NOR-Type Flash Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA, pp. 114-119, 2006, IEEE Computer Society, 0-7695-2514-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
80 | Uthman Alsaiari, Resve A. Saleh |
Power, Delay and Yield Analysis of BIST/BISR PLAs Using Column Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 703-710, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
80 | Lisa M. Guerra, Miodrag Potkonjak, Jan M. Rabaey |
Behavioral-level synthesis of heterogeneous BISR reconfigurable ASIC's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 6(1), pp. 158-167, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
75 | Alfredo Benso, Silvia Chiusano, Giorgio Di Natale, Paolo Prinetto, Monica Lobetti Bodoni |
A Family of Self-Repair SRAM Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 3-5 July 2000, Palma de Mallorca, Spain, pp. 214-218, 2000, IEEE Computer Society, 0-7695-0646-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Memory Self-Repair, Memory BIST, BISR |
70 | Liviu Miclea, Szilárd Enyedi, Alfredo Benso |
Itelligent Agents and BIST/BISR - Working Together in Distributed Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2002, Baltimore, MD, USA, October 7-10, 2002, pp. 940-946, 2002, IEEE Computer Society, 0-7803-7543-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
distributed systems BIST, distributed BISR, Intelligent agent, self-repair, embedded testing, high-level testing |
67 | Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone |
Material Fatigue and Reliability of MEMS Accelerometers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 1-3 October 2008, Boston, MA, USA, pp. 314-322, 2008, IEEE Computer Society, 978-0-7695-3365-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
67 | S. Habermann, René Kothe, Heinrich Theodor Vierhaus |
Built-in Self Repair by Reconfiguration of FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 10-12 July 2006, Como, Italy, pp. 187-188, 2006, IEEE Computer Society, 0-7695-2620-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
67 | Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone |
Reliability Analysis of Self-Repairable MEMS Accelerometer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, pp. 236-244, 2006, IEEE Computer Society, 0-7695-2706-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
67 | Jin-Fu Li 0001, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu |
A built-in self-repair design for RAMs with 2-D redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(6), pp. 742-745, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
67 | Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu |
A Processor-Based Built-In Self-Repair Design for Embedded Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 366-371, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
67 | Jin-Fu Li 0001, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu, Peir-Yuan Tsai, Archer Hsu, Eugene Chow |
A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 393-402, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
built-in redundancy-analysis, built-in self-test, memory testing, semiconductor memory, built-in self-repair |
58 | Da-Ming Chang, Jin-Fu Li 0001, Yu-Jen Huang |
A Built-In Redundancy-Analysis Scheme for Random Access Memories with Two-Level Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 24(1-3), pp. 181-192, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Built-in self-repair (BISR), Built-in redundancy-analysis (BIRA), Two-level redundancy, Random access memory, System-on-chip (SOC) |
58 | Michael Nicolaidis, Lorena Anghel, Nadir Achouri |
Memory Defect Tolerance Architectures for Nanotechnologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(4), pp. 445-455, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
word repair, nanotechnologies, BISR, memory repair, high defect densities |
51 | Tsu-Wei Tseng, Chun-Hsien Wu, Yu-Jen Huang, Jin-Fu Li 0001, Alex Pao, Kevin Chiu, Eliot Chen |
A Built-In Self-Repair Scheme for Multiport RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA, pp. 355-360, 2007, IEEE Computer Society, 0-7695-2812-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
51 | Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone |
Design and Analysis of Self-Repairable MEMS Accelerometer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 3-5 October 2005, Monterey, CA, USA, pp. 21-32, 2005, IEEE Computer Society, 0-7695-2464-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
51 | Rei-Fu Huang, Chin-Lung Su, Cheng-Wen Wu, Shen-Tien Lin, Kun-Lun Luo, Yeong-Jar Chang |
Fail Pattern Identification for Memory Built-In Self-Repair. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, pp. 366-371, 2004, IEEE Computer Society, 0-7695-2235-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
51 | Lorena Anghel, Nadir Achouri, Michael Nicolaidis |
Evaluation of Memory Built-in Self Repair Techniques for High Defect Density Technologie. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2004), 3-5 March 2004, Papeete, Tahiti, pp. 315-320, 2004, IEEE Computer Society, 0-7695-2076-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
41 | Rei-Fu Huang, Jin-Fu Li 0001, Jen-Chieh Yeh, Cheng-Wen Wu |
Raisin: Redundancy Analysis Algorithm Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(4), pp. 386-396, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
repair rate, BIRA, Raisin, yield, BISR, redundancy analysis, algorithm simulation |
41 | Kwang-Ting (Tim) Cheng |
Cocktail approach to functional verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(2), pp. 108, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
validation, functional verification, multiprocessor SoC, SiP, BISR |
41 | Kang Yi, Kyeong-Hoon Jung, Shih-Yang Cheng, Young-Hwan Park, Fadi J. Kurdahi, Ahmed M. Eltawil |
Design and Analysis of Low Power Image Filters Toward Defect-Resilient Embedded Memories for Multimedia SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings, pp. 295-308, 2006, Springer, 3-540-40056-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Low power image filter design, Memory yield enhancement, Memory-error resilient design, H.264 codec, BIST, Embedded memory, BISR |
41 | Kanad Chakraborty |
Testing and Reliability Techniques for High-Bandwidth Embedded RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(1), pp. 89-108, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
multiport RAM, BIST (built-in self-test), BISR (built-in self-repair), column-multiplexed addressing, fault tolerance, reliability, bandwidth |
41 | Minsu Choi, Noh-Jin Park, K. M. George, Byoungjae Jin, Nohpill Park, Yong-Bin Kim, Fabrizio Lombardi |
Fault Tolerant Memory Design for HW/SW Co-Reliability in Massively Parallel Computing Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NCA ![In: 2nd IEEE International Symposium on Network Computing and Applications (NCA 2003), 16-18 April 2003, Cambridge, MA, USA, pp. 341-350, 2003, IEEE Computer Society, 0-7695-1938-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Built-in-self-repair (BISR), Field Reconfiguration, HW/SW Co-reliability, Reliability Assurance, Reliability, High performance computing, Yield, Massively parallel computing, Fault-tolerant memory, Modular Redundancy |
34 | Olivier Ginez, Jean-Michel Portal, Hassen Aziza |
An on-line testing scheme for repairing purposes in Flash memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, April 15-17, 2009, Liberec, Czech Republic, pp. 120-123, 2009, IEEE Computer Society, 978-1-4244-3341-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
34 | Wei Pei, Wen-Ben Jone, Yiming Hu |
Fault Modeling and Detection for Drowsy SRAM Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(6), pp. 1084-1100, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Irith Pomeranz, Sudhakar M. Reddy |
Semi-Concurrent On-Line Testing of Transition Faults Through Output Response Comparison of Identical Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 26-28 September 2007, Rome, Italy., pp. 457-455, 2007, IEEE Computer Society, 0-7695-2885-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Tsu-Wei Tseng, Jin-Fu Li 0001, Da-Ming Chang |
A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 53-58, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Yu-Jen Huang, Da-Ming Chang, Jin-Fu Li 0001 |
A Built-In Redundancy-Analysis Scheme for Self-Repairable RAMs with Two-Level Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, pp. 362-370, 2006, IEEE Computer Society, 0-7695-2706-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Inki Hong, Miodrag Potkonjak, Ramesh Karri |
A heterogeneous built-in self-repair approach using system-level synthesis flexibility. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Reliab. ![In: IEEE Trans. Reliab. 53(1), pp. 93-101, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Rita Zappa, Carolina Selva, Danilo Rimondi, Cosimo Torelli, M. Crestan, Giovanni Mastrodomenico, Lara Albani |
Micro Programmable Built-In Self Repair for SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, CA, USA, pp. 72-77, 2004, IEEE Computer Society, 0-7695-2193-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
34 | Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri |
Optimal Spare Utilization in Repairable and Reliable Memory Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 11th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2003), 28-29 July 2003, San Jose, CA, USA, pp. 64-71, 2003, IEEE Computer Society, 0-7695-2004-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Embedded Memory Repair and Reliability, Fault-Tolerant Memory Core, System-on-chip, Yield, Built-In-Self-Repair |
34 | Minsu Choi, Nohpill Park, Fabrizio Lombardi, Yong-Bin Kim, Vincenzo Piuri |
Balanced Redundancy Utilization in Embedded Memory Cores for Dependable Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 6-8 November 2002, Vancouver, BC, Canada, Proceedings, pp. 419-427, 2002, IEEE Computer Society, 0-7695-1831-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
29 | Qian Yu, Qing Li 0006, Rui He, Gareth Tyson, Wanxin Shi, Jianhui Lv, Zhenhui Yuan, Peng Zhang, Yulong Lan, Zhicheng Li |
BiSR: Bidirectionally Optimized Super-Resolution for Mobile Video Streaming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WWW ![In: Proceedings of the ACM Web Conference 2023, WWW 2023, Austin, TX, USA, 30 April 2023 - 4 May 2023, pp. 3121-3131, 2023, ACM, 978-1-4503-9416-1. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
29 | Wei Zou, Benoit Nadeau-Dostie |
Configurable BISR Chain For Fast Repair Data Loading. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: IEEE International Test Conference, ITC 2022, Anaheim, CA, USA, September 23-30, 2022, pp. 56-62, 2022, IEEE, 978-1-6654-6270-9. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
29 | Sabyasachee Banerjee |
Experimental result of our BISR work. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2020 |
DOI RDF |
|
29 | Venkat Sundar Gadepalli, Hatice Gulcin Ozer, Ayse Selen Yilmaz, Maciej Pietrzak, Amy Webb |
BISR-RNAseq: an efficient and scalable RNAseq analysis workflow with interactive report generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BMC Bioinform. ![In: BMC Bioinform. 20-S(24), pp. 670, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
29 | Wei-Kai Cheng, Jian-Kai Chen, Shih-Hsu Huang |
Integration of Retention-aware Refresh and BISR Techniques for DRAM Refresh Power Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: International SoC Design Conference, ISOCC 2018, Daegu, South Korea, November 12-15, 2018, pp. 50-51, 2018, IEEE, 978-1-5386-7960-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
29 | Tianjian Li, Yan Han, Xiaoyao Liang, Hsien-Hsin S. Lee, Li Jiang 0002 |
Fault clustering technique for 3D memory BISR. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2017, Lausanne, Switzerland, March 27-31, 2017, pp. 560-565, 2017, IEEE, 978-3-9815370-8-6. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
29 | Chih-Sheng Hou, Jin-Fu Li 0001 |
High Repair-Efficiency BISR Scheme for RAMs by Reusing Bitmap for Bit Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 23(9), pp. 1720-1728, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
29 | Madhuri Elsa Eapen, C. Pradeep, Anila Ann Varghese, Jisha M. Nair |
Placement Strategies for Faulty Cells in Module Relocation Based BISR Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IBICA ![In: Innovations in Bio-Inspired Computing and Applications - Proceedings of the 6th International Conference on Innovations in Bio-Inspired Computing and Applications (IBICA 2015) held in Kochi, India during December 16-18, 2015, pp. 437-446, 2015, Springer, 978-3-319-28030-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
29 | Andrej Kincel, Marcel Baláz |
Case study: BISR for a processor multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, DDECS 2014, Warsaw, Poland, 23-25 April, 2014, pp. 314-317, 2014, IEEE Computer Society, 978-1-4799-4560-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
29 | Gang Wang, Xu Wang, Xinke Chen, Shuangbai Xue |
Test and Repair Flow for Shared BISR in Asynchronous Multi-processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 20th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2014, Potsdam, Germany, May 12-14, 2014, pp. 105-107, 2014, IEEE Computer Society, 978-1-4799-3789-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
29 | Georgios Zervakis 0001, Nikolaos Eftaxiopoulos-Sarris, Kostas Tsoumanis, Nicholas Axelos, Kiamal Z. Pekmestzi |
A segmentation-based BISR scheme. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 19th Asia and South Pacific Design Automation Conference, ASP-DAC 2014, Singapore, January 20-23, 2014, pp. 652-657, 2014, IEEE, 978-1-4799-2816-3. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
29 | Maddu Karunaratne, Bejoy Oomann |
An Optimal Memory BISR Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. ![In: J. Comput. 8(9), pp. 2167-2174, 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP BibTeX RDF |
|
29 | Chun-Chuan Chi, Yung-Fa Chou, Ding-Ming Kwai, Yu-Ying Hsiao, Cheng-Wen Wu, Yu-Tsao Hsing, Li-Ming Denq, Tsung-Hsiang Lin |
3D-IC BISR for stacked memories using cross-die spares. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-DAT ![In: Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, VLSI-DAT 2012, Hsinchu, Taiwan, April 23-25, 2012, pp. 1-4, 2012, IEEE, 978-1-4577-2080-2. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
29 | Kun-Chih Chen, Shu-Yen Lin, Wen-Chung Shen, An-Yeu Wu |
A scalable built-in self-recovery (BISR) VLSI architecture and design methodology for 2D-mesh based on-chip networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Autom. Embed. Syst. ![In: Des. Autom. Embed. Syst. 15(2), pp. 111-132, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
29 | Shyue-Kung Lu, Chun-Lin Yang, Yuang-Cheng Hsiao, Cheng-Wen Wu |
Efficient BISR Techniques for Embedded Memories Considering Cluster Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 18(2), pp. 184-193, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
29 | Kiamal Z. Pekmestzi, Nicholas Axelos, Isidoros Sideris, Nikos K. Moshopoulos |
A BISR Architecture for Embedded Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 7-9 July 2008, Rhodes, Greece, pp. 149-154, 2008, IEEE Computer Society, 978-0-7695-3264-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
29 | Chun-Lin Yang, Yuang-Cheng Hsiao, Shyue-Kung Lu |
Efficient BISR Techniques for Embedded Memories Considering Cluster Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 13th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2007), 17-19 December, 2007, Melbourne, Victoria, Australia, pp. 224-231, 2007, IEEE Computer Society, 0-7695-3054-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Shyue-Kung Lu, Chun-Lin Yang, Han-Wen Lin |
Efficient BISR Techniques for Word-Oriented Embedded Memories with Hierarchical Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACIS-ICIS ![In: 5th Annual IEEE/ACIS International Conference on Computer and Information Science (ICIS 2006) and 1st IEEE/ACIS International Workshop on Component-Based Software Engineering, Software Architecture and Reuse (COMSAR 2006), 10-12 July 2006, Honolulu, Hawaii, USA, pp. 355-360, 2006, IEEE Computer Society, 0-7695-2613-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Li-Ming Denq, Tzu-chiang Wang, Cheng-Wen Wu |
An Enhanced SRAM BISR Design with Reduced Timing Penalty. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ATS ![In: 15th Asian Test Symposium, ATS 2006, Fukuoka, Japan, November 20-23, 2006, pp. 25-30, 2006, IEEE, 0-7695-2628-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Gustavo Neuberger, Fernanda Lima Kastensmidt, Ricardo Reis 0001 |
TOC-BISR: A Self-Repair Scheme for Memories in Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IESS ![In: From Specification to Embedded Systems Application [International Embedded Systems Symposium, IESS 2005, Manaus, Brazil, August 2005], pp. 157-168, 2005, Springer, 978-0-387-27557-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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29 | Michael Nicolaidis, Slimane Boutobza, Nadir Achouri, R. D. Shawn Blanton, Julie Segal, David Y. Lepejian, Ben Chu, Tony Singh, Harvey Berman |
Designing and Implementing Efficient BISR Techniques for Embedded RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATW ![In: 2nd Latin American Test Workshop, LATW 2001, Cancun, Mexico, February 11-14, 2001., pp. 248-252, 2001, IEEE. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP BibTeX RDF |
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29 | Yoshihiro Nagura, Michael Mullins, Anthony Sauvageau, Yoshinoro Fujiwara, Katsuya Furue, Ryuji Ohmura, Tatsunori Komoike, Takenori Okitaka, Tetsushi Tanizaki, Katsumi Dosaka, Kazutami Arimoto, Yukiyoshi Koda, Tetsuo Tada |
Test cost reduction by at-speed BISR for embedded DRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October - 1 November 2001, pp. 182-187, 2001, IEEE Computer Society, 0-7803-7169-0. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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29 | Inki Hong, Miodrag Potkonjak, Ramesh Karri |
Heterogeneous BISR-approach using System Level Synthesis Flexibility. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the ASP-DAC '98, Asia and South Pacific Design Automation Conference 1998, Pacifico Yokohama, Yokohama, Japan, February 10-13, 1998, pp. 289-294, 1998, IEEE, 0-7803-4425-1. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
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29 | Miodrag Potkonjak, Lisa M. Guerra, Jan M. Rabaey |
Heterogeneous BISR techniques for yield and reliability enhancement using high level synthesis transformations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: International Conference on Application-Specific Array Processors, ASAP 1993, Proceedings, Venice, Italy, 25-27 October, 1993, pp. 454-465, 1993, IEEE, 0-8186-3492-8. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
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24 | André K. Nieuwland, Richard P. Kleihorst |
IC Cost Reduction by Applying Embedded Fault Tolerance for Soft Errors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 20(5), pp. 533-542, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
IC cost, IC production, fault tolerant, redundancy, yield, soft error, on-line test, defect density, SEU, SER, BISR |
24 | Kanad Chakraborty, Anurag Gupta, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder |
A Physical Design Tool for Built-in Self-Repairable Static RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 714-, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Built-in, (BISR), reliability, yield, self-repair |
17 | Uthman Alsaiari, Resve A. Saleh |
Partitioning for Selective Flip-Flop Redundancy in Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 9th International Symposium on Quality of Electronic Design (ISQED 2008), 17-19 March 2008, San Jose, CA, USA, pp. 798-803, 2008, IEEE Computer Society, 978-0-7695-3117-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Partitioning, Redundancy, Yield, Flip-Flop |
17 | R. Chandramouli |
Managing Test and Repair of Embedded Memory Subsystem in SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 452, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
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17 | Chih-Tsun Huang, Jen-Chieh Yeh, Yuan-Yuan Shih, Rei-Fu Huang, Cheng-Wen Wu |
On Test and Diagnostics of Flash Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 13th Asian Test Symposium (ATS 2004), 15-17 November 2004, Kenting, Taiwan, pp. 260-265, 2004, IEEE Computer Society, 0-7695-2235-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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17 | Said Hamdioui, Georgi Gaydadjiev, Ad J. van de Goor |
The State-of-Art and Future Trends in Testing Embedded Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 12th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2004), 9-10 August 2004, San Jose, CA, USA, pp. 54-59, 2004, IEEE Computer Society, 0-7695-2193-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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17 | Michael Nicolaidis, Nadir Achouri, Lorena Anghel |
A Diversified Memory Built-In Self-Repair Approach for Nanotechnologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 22nd IEEE VLSI Test Symposium (VTS 2004), 25-29 April 2004, Napa Valley, CA, USA, pp. 313-318, 2004, IEEE Computer Society, 0-7695-2134-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
ECC codes, word repair, nanotechnologies, memory repair, high defect densities |
17 | Liviu Miclea, Szilárd Enyedi, Gavril Toderean, Alfredo Benso, Paolo Prinetto |
Towards Microagent based DBIST/DBISR. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 867-874, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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17 | Robert C. Aitken |
A Modular Wrapper Enabling High Speed BIST and Repair for Small Wide Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 997-1005, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
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17 | Liviu Miclea, Szilárd Enyedi, Gavril Toderean, Alfredo Benso, Paolo Prinetto |
Agent Based DBIST/DBISR And Its Web/Wireless Management. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 952-960, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
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17 | Rei-Fu Huang, Jin-Fu Li 0001, Jen-Chieh Yeh, Cheng-Wen Wu |
A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 10th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor, France, pp. 68-, 2002, IEEE Computer Society, 0-7695-1617-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
simulation, memory testing, embedded memory, redundancy analysis, memory repair |
17 | Rei-Fu Huang, Jin-Fu Li 0001, Jen-Chieh Yeh, Cheng-Wen Wu |
A Simulator for E aluating Redundancy Analysis Algorithms of Repairable Embedded Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTW ![In: 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 8-10 July 2002, Isle of Bendor, France, pp. 262-, 2002, IEEE Computer Society, 0-7695-1641-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
simulation, memory testing, embedded memory, redundancy analysis, memory repair |
17 | Kanad Chakraborty, Shriram Kulkarni, Mayukh Bhattacharya, Pinaki Mazumder, Anurag Gupta |
A physical design tool for built-in self-repairable RAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(2), pp. 352-364, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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17 | Pinaki Mazumder, Jih-Shyr Yih |
A new built-in self-repair approach to VLSI memory yield enhancement by using neural-type circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(1), pp. 124-136, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
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