Search results for "COOL"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
139	Karen Holtzblatt, David B. Rondeau, Les Holtzblatt	Understanding "cool".	CHI Extended Abstracts	2010	DBLP DOI BibTeX RDF	compelling design, product and system design, cool
121	Xiongfei Liao, Wu Jigang, Thambipillai Srikanthan	A temperature-aware virtual submesh allocation scheme for noc-based manycore chips.	SPAA	2008	DBLP DOI BibTeX RDF	manycore chips, submesh allocation, algorithm, noc, temperature
99	Kritsada Sriphaew, Hiroya Takamura, Manabu Okumura	Cool Blog Identi?cation Using Topic-Based Models.	Web Intelligence	2008	DBLP DOI BibTeX RDF
86	Kristen Nygaard	COOL (comprehensive object-oriented learning).	ITiCSE	2002	DBLP DOI BibTeX RDF
86	Kritsada Sriphaew, Hiroya Takamura, Manabu Okumura	Cool Blog Classification from Positive and Unlabeled Examples.	PAKDD	2009	DBLP DOI BibTeX RDF	Cool blog, PU-learning, weighting examples, bagging
80	Tsugio Makimoto, Kazuhiko Eguchi, Mitsugu Yoneyama	The Cooler the Better: New Directions in the Nomadic Age.	Computer	2001	DBLP DOI BibTeX RDF
72	Mikhail N. Dorojevets	COOL Approach to Petaflops Computing (invited paper).	PaCT	1999	DBLP DOI BibTeX RDF
67	Raksit Ashok, Saurabh Chheda, Csaba Andras Moritz	Coupling compiler-enabled and conventional memory accessing for energy efficiency.	ACM Trans. Comput. Syst.	2004	DBLP DOI BibTeX RDF	translation buffers, virtually addressed caches, Energy efficiency
67	Sejun Song, Jim Huang	Internet router outage measurement: an embedded approach.	NOMS (1)	2004	DBLP DOI BibTeX RDF
67	Bernard K. Gunther	The Circuit Object Organization Library.	ACAC	2000	DBLP DOI BibTeX RDF
59	Robert C. Aitken	ITC is Cool.	IEEE Des. Test Comput.	2005	DBLP DOI BibTeX RDF	high-frequency test, board and system test, test compression, silicon debug, International Test Conference, ITC
58	Sangyeob Kim, Soyeon Kim, Seongyon Hong, Sangjin Kim, Donghyeon Han, Jiwon Choi, Hoi-Jun Yoo	COOL-NPU: Complementary Online Learning Neural Processing Unit with CNN-SNN Heterogeneous Core and Event-driven Backpropagation.	COOL CHIPS	2023	DBLP DOI BibTeX RDF
58	Vinod Pangracious, Ranjitha Dash, Ashok Kumar Turuk	3D-cool: Design and development of adaptive thermal-aware three-dimensional NoC-based multiprocessor chip.	COOL CHIPS	2018	DBLP DOI BibTeX RDF
58	Hideharu Amano, Tadao Nakamura, Hiroaki Kobayashi, Hironori Kasahara, Yoshiaki Hagiwara, Jeffrey L. Burns, David Brash	Panel discussions: "Cool chips for the next decade".	COOL Chips	2017	DBLP DOI BibTeX RDF
58	Fumio Arakawa	Panel discussions: Toward wearable computing era, how COOL chip architecture and tools will evolve?	COOL Chips	2014	DBLP DOI BibTeX RDF
58	Yukoh Matsumoto, Tomoyuki Morimoto, Michiya Hagimoto, Hiroyuki Uchida, Nobuyuki Hikichi, Fumito Imura, Hiroshi Nakagawa, Masahiro Aoyagi	Cool System scalable 3-D stacked heterogeneous Multi-Core / Multi-Chip architecture for ultra low-power digital TV applications.	COOL Chips	2012	DBLP DOI BibTeX RDF
58	Marco Chacin, Hiroyuki Uchida, Michiya Hagimoto, Takashi Miyazaki, Takeshi Ohkawa, Rimon Ikeno, Yukoh Matsumoto, Fumito Imura, Motohiro Suzuki, Katsuya Kikuchi, Hiroshi Nakagawa, Masahiro Aoyagi	COOL interconnect low power interconnection technology for scalable 3D LSI design.	COOL Chips	2011	DBLP DOI BibTeX RDF
45	Juan Miguel Gómez 0001, Fernando Paniagua Martín, Ángel García-Crespo, Christoph Bussler	Modelling B2B Conversations with COOL for SemanticWeb Services.	AICT/ICIW	2006	DBLP DOI BibTeX RDF
45	Rob J. van Glabbeek	On Cool Congruence Formats for Weak Bisimulations.	ICTAC	2005	DBLP DOI BibTeX RDF
45	Osman S. Unsal, Israel Koren, C. Mani Krishna 0001, Csaba Andras Moritz	Cool-Fetch: A Compiler-Enabled IPC Estimation Based Framework for Energy Reduction.	Interaction between Compilers and Computer Architectures	2004	DBLP DOI BibTeX RDF
45	Thomas Strang, Claudia Linnhoff-Popien, Korbinian Frank	CoOL: A Context Ontology Language to Enable Contextual Interoperability.	DAIS	2003	DBLP DOI BibTeX RDF
45	Raksit Ashok, Saurabh Chheda, Csaba Andras Moritz	Cool-Mem: combining statically speculative memory accessing with selective address translation for energy efficiency.	ASPLOS	2002	DBLP DOI BibTeX RDF
45	Volker Braun, Jens Knoop, Dirk Koschützki	Cool: A Control-Flow Generator for System Analysis.	CC	1998	DBLP DOI BibTeX RDF
45	Rodger Lea, Christian Jacquemot	The COOL architecture and abstractions for object-oriented distributed operating systems.	ACM SIGOPS European Workshop	1992	DBLP DOI BibTeX RDF
40	Georgios Meditskos, Nick Bassiliades	O-DEVICE: An Object-Oriented Knowledge Base System for OWL Ontologies.	SETN	2006	DBLP DOI BibTeX RDF
40	Kunio Uchiyama, Pradip Bose	Guest Editors' Introduction: Energy-Efficient Design.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Cool Chips VII, ACEED, Cell processor, Energy-efficient design
39		IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2023, Tokyo, Japan, April 19-21, 2023	COOL CHIPS	2023	DBLP DOI BibTeX RDF
39	Anawin Opasatian, Makoto Ikeda	Lookup Table Modular Reduction: A Low-Latency Modular Reduction for Fast ECC Processor.	COOL CHIPS	2023	DBLP DOI BibTeX RDF
39	Viktor Razilov, Juncen Zhong, Emil Matús, Gerhard P. Fettweis	Dual Vector Load for Improved Pipelining in Vector Processors.	COOL CHIPS	2023	DBLP DOI BibTeX RDF
39	Infall Syafalni, Mohamad Imam Firdaus, Andi M. Riyadhus Ilmy, Nana Sutisna, Trio Adiono	MazeCov-Q: An Efficient Maze-Based Reinforcement Learning Accelerator for Coverage.	COOL CHIPS	2023	DBLP DOI BibTeX RDF
39	Genta Inoue, Daiki Okonogi, Thiem Van Chu, Jaehoon Yu, Masato Motomura, Kazushi Kawamura	Flexibly Controllable Dynamic Cooling Methods for Solid-State Annealing Processors to Improve Combinatorial Optimization Performance.	COOL CHIPS	2023	DBLP DOI BibTeX RDF
39	Ziquan Qin, Kaijie Wei, Hideharu Amano, Kazuhiro Nakadai	Low power implementation of Geometric High-order Decorrelation-based Source Separation on an FPGA board.	COOL CHIPS	2023	DBLP DOI BibTeX RDF
39	Donghyeon Han, Junha Ryu, Sangyeob Kim, Sangjin Kim, Jongjun Park, Hoi-Jun Yoo	A Low-power Neural 3D Rendering Processor with Bio-inspired Visual Perception Core and Hybrid DNN Acceleration.	COOL CHIPS	2023	DBLP DOI BibTeX RDF
39	Tobias Kaiser, Friedel Gerfers	A 2.41-μW/MHz, 437-PE/mm2 CGRA in 22 nm FD-SOI With RISC-Like Code Generation.	COOL CHIPS	2023	DBLP DOI BibTeX RDF
39	Tatsuya Kubo, Shinya Takamaeda-Yamazaki	Cachet: A High-Performance Joint-Subtree Integrity Verification for Secure Non-Volatile Memory.	COOL CHIPS	2023	DBLP DOI BibTeX RDF
39	Takeshi Ohkawa, Masahiro Aoyagi	FPGA Emulation of Through-Silicon-Via (TSV) Dataflow Network for 3D Standard Chip Stacking System.	COOL CHIPS	2023	DBLP DOI BibTeX RDF
39	Jinsung Yoon, Donghyun Lee, Neungyun Kim, Su-Jung Lee, Gil-Ho Kwak, Tae-Hwan Kim	A Real-Time Keyword Spotting System Based on an End-To-End Binary Convolutional Neural Network in FPGA.	COOL CHIPS	2023	DBLP DOI BibTeX RDF
39		IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2022, Tokyo, Japan, April 20-22, 2022	COOL CHIPS	2022	DBLP DOI BibTeX RDF
39	Moritz Scherer, Alfio Di Mauro, Georg Rutishauser, Tim Fischer 0001, Luca Benini	A 1036 TOp/s/W, 12.2 mW, 2.72 μJ/Inference All Digital TNN Accelerator in 22 nm FDX Technology for TinyML Applications.	COOL CHIPS	2022	DBLP DOI BibTeX RDF
39	Yang Chen, Lin Liu, Xuelin Feng, Jinglin Shi	DXT501: An SDR-Based Baseband MP-SoC for Multi-Protocol Industrial Wireless Communication.	COOL CHIPS	2022	DBLP DOI BibTeX RDF
39	Takuya Kojima, Hayate Okuhara, Masaaki Kondo, Hideharu Amano	Body Bias Control on a CGRA based on Convex Optimization.	COOL CHIPS	2022	DBLP DOI BibTeX RDF
39	Kaoru Masada, Ryohei Nakayama, Makoto Ikeda	Hardware Acceleration of Aggregate Signature Generation and Authentication by BLS Signature over BLS12-381 curve.	COOL CHIPS	2022	DBLP DOI BibTeX RDF
39	Kensuke Iizuka, Haruna Takagi, Aika Kamei, Kazuei Hironaka, Hideharu Amano	Power Analysis of Directly-connected FPGA Clusters.	COOL CHIPS	2022	DBLP DOI BibTeX RDF
39	Yuki Abe, Kazutoshi Kobayashi, Jun Shiomi, Hiroyuki Ochi	Zero-standby-power Nonvolatile Standard Cell Memory Using FiCC for IoT Processors with Intermittent Operations.	COOL CHIPS	2022	DBLP DOI BibTeX RDF
39	Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Koyo Nitta, Kimikazu Sano, Masayuki Sato 0001, Hiroe Iwasaki, Hiroaki Kobayashi	An Efficient Reference Image Sharing Method for the Parallel Video Encoding Architecture.	COOL CHIPS	2022	DBLP DOI BibTeX RDF
39	Dongseok Im, Gwangtae Park, Junha Ryu, Zhiyong Li, Sanghoon Kang, Donghyeon Han, Jinsu Lee, Wonhoon Park, Hankyul Kwon, Hoi-Jun Yoo	A Low-power and Real-time 3D Object Recognition Processor with Dense RGB-D Data Acquisition in Mobile Platforms.	COOL CHIPS	2022	DBLP DOI BibTeX RDF
39	Shine Parekkadan Sunny, Satyajit Das	Reinforcement Learning based Efficient Mapping of DNN Models onto Accelerators.	COOL CHIPS	2022	DBLP DOI BibTeX RDF
39	Hoang Gia Vu, Ngoc-Dai Bui	Encoder-based Many-Pattern Matching on FPGAs.	COOL CHIPS	2022	DBLP DOI BibTeX RDF
39	Yasuhiro Mochida, Daisuke Shirai, Koichi Takasugi	Ultra-low Latency 8K Video-transmission System Utilizing Disaggregation Configuration.	COOL CHIPS	2022	DBLP DOI BibTeX RDF
39	Reon Oshio, Sugahara Takuya, Atsushi Sawada, Mutsumi Kimura, Renyuan Zhang, Yasuhiko Nakashima	A Memcapacitive Spiking Neural Network with Circuit Nonlinearity-aware Training.	COOL CHIPS	2022	DBLP DOI BibTeX RDF
39		IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2021, Tokyo, Japan, April 14-16, 2021	COOL CHIPS	2021	DBLP DOI BibTeX RDF
39	Tomoki Shimizu, Kohei Ito, Kensuke Iizuka, Kazuei Hironaka, Hideharu Amano	Hybrid Network of Packet Switching and STDM in a Multi-FPGA System.	COOL CHIPS	2021	DBLP DOI BibTeX RDF
39	Donghyeon Han, Dongseok Im, Gwangtae Park, Youngwoo Kim, Seokchan Song, Juhyoung Lee, Hoi-Jun Yoo	An Energy-Efficient Deep Neural Network Training Processor with Bit-Slice-Level Reconfigurability and Sparsity Exploitation.	COOL CHIPS	2021	DBLP DOI BibTeX RDF
39	Shunsuke Tsukada, Hikaru Takayashiki, Masayuki Sato 0001, Kazuhiko Komatsu, Hiroaki Kobayashi	A Metadata Prefetching Mechanism for Hybrid Memory Architectures.	COOL CHIPS	2021	DBLP DOI BibTeX RDF
39	Eishi Arima, Yuetsu Kodama, Tetsuya Odajima, Miwako Tsuji, Mitsuhisa Sato	Power/Performance/Area Evaluations for Next-Generation HPC Processors using the A64FX Chip.	COOL CHIPS	2021	DBLP DOI BibTeX RDF
39	Van Dai Phan, Hoai Luan Pham, Thi Hong Tran, Yasuhiko Nakashima	High Performance Multicore SHA-256 Accelerator using Fully Parallel Computation and Local Memory.	COOL CHIPS	2021	DBLP DOI BibTeX RDF
39	Ayan Datta, Karanvir Singh, Arpita Dutta, Kousik Debnath	A Timing Aware Connectivity Optimization Technique for Improving Energy Efficiency of High-Performance CPUs.	COOL CHIPS	2021	DBLP DOI BibTeX RDF
39	Zhenshan Bao, Kang Zhan, Wenbo Zhang 0003, Junnan Guo	LSFQ: A Low Precision Full Integer Quantization for High-Performance FPGA-Based CNN Acceleration.	COOL CHIPS	2021	DBLP DOI BibTeX RDF
39	Sugahara Takuya, Renyuan Zhang, Yasuhiko Nakashima	Training Low-Latency Spiking Neural Network through Knowledge Distillation.	COOL CHIPS	2021	DBLP DOI BibTeX RDF
39	Takaki Urabe, Hiroyuki Ochi, Kazutoshi Kobayashi	Nonvolatile SRAM Using Fishbone-in-Cage Capacitor in a 180 nm Standard CMOS Process for Zero-Standby and Instant-Powerup Embedded Memory on IoT.	COOL CHIPS	2021	DBLP DOI BibTeX RDF
39	Stanislav Sedukhin, Yoichi Tomioka, Kohei Yamamoto	In Search of the Performance- and Energy-Efficient CNN Accelerators.	COOL CHIPS	2021	DBLP DOI BibTeX RDF
39		2020 IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2020, Kokubunji, Japan, April 15-17, 2020	COOL CHIPS	2020	DBLP BibTeX RDF
39	Shota Nakabeppu, Yosuke Ide, Masahiko Takahashi, Yuta Tsukahara, Hiromi Suzuki, Haruki Shishido, Nobuyuki Yamasaki	Space Responsive Multithreaded Processor (SRMTP) for Spacecraft Control.	COOL CHIPS	2020	DBLP DOI BibTeX RDF
39	Junichiro Kadomoto, Hidetsugu Irie, Shuichi Sakai	A RISC-V Processor with an Inter-Chiplet Wireless Communication Interface for Shape-Changeable Computers.	COOL CHIPS	2020	DBLP DOI BibTeX RDF
39	Masayuki Sato 0001, Xue Hao, Kazuhiko Komatsu, Hiroaki Kobayashi	Energy-efficient Design of an STT-RAM-based Hybrid Cache Architecture.	COOL CHIPS	2020	DBLP DOI BibTeX RDF
39	Takuya Sakuma, Hiroki Matsutani	An Area-Efficient Implementation of Recurrent Neural Network Core for Unsupervised Anomaly Detection.	COOL CHIPS	2020	DBLP DOI BibTeX RDF
39	Dennis Walter, André Scharfe, Alexander Oefelein, Florian Schraut, Heiner Bauer, Farkas Csaszar, Robert Niebsch, Jörg Schreiter, Holger Eisenreich, Sebastian Höppner	A 0.55V 6.3uW/MHz Arm Cortex-M4 MCU with Adaptive Reverse Body Bias and Single Rail SRAM.	COOL CHIPS	2020	DBLP DOI BibTeX RDF
39	Jisu Kwon, Moon Gi Seok, Daejin Park	User Insensible Sliding Firmware Update Technique for Flash-Area/Time-Cost Reduction toward Low-Power Embedded Software Replacement.	COOL CHIPS	2020	DBLP DOI BibTeX RDF
39	Markus Hiienkari, Navneet Gupta, Jukka Teittinen, Jesse Simonsson, Matthew J. Turnquist, Jonas Eriksson, Risto Anttila, Ohto Myllynen, Hannu Rämäkkö, Sofia Mäkikyrö, Lauri Koskinen	A 0.4-0.9V, 2.87pJ/cycle Near-Threshold ARM Cortex-M3 CPU with In-Situ Monitoring and Adaptive-Logic Scan.	COOL CHIPS	2020	DBLP DOI BibTeX RDF
39	Kimiyoshi Usami, Sosuke Akiba, Hideharu Amano, Takeharu Ikezoe, Keizo Hiraga, Kenta Suzuki, Yasuo Kanda	Non-Volatile Coarse Grained Reconfigurable Array Enabling Two-step Store Control for Energy Minimization.	COOL CHIPS	2020	DBLP DOI BibTeX RDF
39	Haerang Choi, Yosep Lee, Jae-Joon Kim, Sungjoo Yoo	A Novel In-DRAM Accelerator Architecture for Binary Neural Network.	COOL CHIPS	2020	DBLP DOI BibTeX RDF
39	Yasuhiro Mochida, Takahiro Yamaguchi, Ken Nakamura	MMT-based Multi-channel Video Transmission System with Synchronous Processing Architecture.	COOL CHIPS	2020	DBLP DOI BibTeX RDF
39	Dionysios Diamantopoulos, Florian Scheidegger, Stefan Mach, Fabian Schuiki, Germain Haugou, Michael Schaffner, Frank K. Gürkaynak, Christoph Hagleitner, A. Cristiano I. Malossi, Luca Benini	XwattPilot: A Full-stack Cloud System Enabling Agile Development of Transprecision Software for Low-power SoCs.	COOL CHIPS	2020	DBLP DOI BibTeX RDF
39	Meenatchi Jagasivamani, Candace Walden, Devesh Singh, Luyi Kang, Mehdi Asnaashari, Sylvain Dubois, Bruce L. Jacob, Donald Yeung	Tileable Monolithic ReRAM Memory Design.	COOL CHIPS	2020	DBLP DOI BibTeX RDF
39		IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2019, Yokohama, Japan, April 17-19, 2019	COOL CHIPS	2019	DBLP BibTeX RDF
39	Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Tatsuya Osawa, Takayuki Onishi, Koyo Nitta, Hiroe Iwasaki, Atsushi Shimizu	Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture.	COOL CHIPS	2019	DBLP DOI BibTeX RDF
39	Kyosuke Tanaka, Hayato Yamaki, Shinobu Miwa, Hiroki Honda	Multi-Level Packet Processing Caches.	COOL CHIPS	2019	DBLP DOI BibTeX RDF
39	Yuta Tokusashi, Hiroki Matsutani, Hideharu Amano	Key-value Store Chip Design for Low Power Consumption.	COOL CHIPS	2019	DBLP DOI BibTeX RDF
39	Mulya Agung, Muhammad Alfian Amrizal, Ryusuke Egawa, Hiroyuki Takizawa	The Impacts of Locality and Memory Congestion-aware Thread Mapping on Energy Consumption of Modern NUMA Systems.	COOL CHIPS	2019	DBLP DOI BibTeX RDF
39	Robert Wittig, Mattis Hasler, Emil Matús, Gerhard P. Fettweis	Statistical Access Interval Prediction for Tightly Coupled Memory Systems.	COOL CHIPS	2019	DBLP DOI BibTeX RDF
39	Eri Ogawa, Kazuaki Ishizaki, Hiroshi Inoue, Swagath Venkataramani, Jungwook Choi, Wei Wang 0333, Vijayalakshmi Srinivasan, Moriyoshi Ohara, Kailash Gopalakrishnan	A Compiler for Deep Neural Network Accelerators to Generate Optimized Code for a Wide Range of Data Parameters from a Hand-crafted Computation Kernel.	COOL CHIPS	2019	DBLP DOI BibTeX RDF
39	Yugo Yamauchi, Kazusa Musha, Hideharu Amano	Implementing a large application(LSTM) on the multi-FPGA system: Flow-in-Cloud.	COOL CHIPS	2019	DBLP DOI BibTeX RDF
39	Tomoya Itsubo, Mineto Tsukada, Hiroki Matsutani	Performance and Cost Evaluations of Online Sequential Learning and Unsupervised Anomaly Detection Core.	COOL CHIPS	2019	DBLP DOI BibTeX RDF
39	Alberto Gianelli, Nick Iliev, Shamma Nasrin, Mariagrazia Graziano, Amit Ranjan Trivedi	Low Power Speaker Identification using Look Up-free Gaussian Mixture Model in CMOS.	COOL CHIPS	2019	DBLP DOI BibTeX RDF
39	Ken Tanabe, Hiroshi Kubota, Akihide Sai, Nobu Matsumoto	Inter-Frame Smart-Accumulation Technique for Long-Range and High-Pixel Resolution LiDAR.	COOL CHIPS	2019	DBLP DOI BibTeX RDF
39	Ravi Theja Gollapudi, Gokturk Yuksek, Kanad Ghose	Cache-Aware Dynamic Classification and Scheduling for Linux.	COOL CHIPS	2019	DBLP DOI BibTeX RDF
39	Yusuke Shirota, Satoshi Shirai, Tatsunori Kanai	Hybrid Access in Storage-class Memory-aware Low Power Virtual Memory System.	COOL CHIPS	2019	DBLP DOI BibTeX RDF
39	Shinichi Sasaki, Asuka Maki, Daisuke Miyashita, Jun Deguchi	Post Training Weight Compression with Distribution-based Filter-wise Quantization Step.	COOL CHIPS	2019	DBLP DOI BibTeX RDF
39	Masayuki Sato 0001, Yongcheng Chen, Haruya Kikuchi, Kazuhiko Komatsu, Hiroaki Kobayashi	Perceptron-based Cache Bypassing for Way-Adaptable Caches.	COOL CHIPS	2019	DBLP DOI BibTeX RDF
39		2018 IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2018, Yokohama, Japan, April 18-20, 2018	COOL CHIPS	2018	DBLP BibTeX RDF
39	Ryosuke Kazami, Hayate Okuhara, Hideharu Amano	Design automation methodology of a critical path monitor for adaptive voltage controls.	COOL CHIPS	2018	DBLP DOI BibTeX RDF
39	Tetsuya Odajima, Yuetsu Kodama, Mitsuhisa Sato	Power performance analysis of ARM scalable vector extension.	COOL CHIPS	2018	DBLP DOI BibTeX RDF
39	Mathieu Coustans, Abdelkarim Cherkaoui, Laurent Fesquet, Christian Terrier, Stephanie Salgado, Thomas Eberhardt, Maher Kayal	Subthreshold logic for low-area and energy efficient true random number generator.	COOL CHIPS	2018	DBLP DOI BibTeX RDF
39	Ken Tanabe, Hiroshi Kubota, Akihide Sai, Nobu Matsumoto	Data selection and de-noising based on reliability for long-range and high-pixel resolution LiDAR.	COOL CHIPS	2018	DBLP DOI BibTeX RDF
39	Noriyuki Uetake, Renyuan Zhang, Takashi Nakada, Yasuhiko Nakashima	A programmable analog calculation unit for vector computations.	COOL CHIPS	2018	DBLP DOI BibTeX RDF
39	Andrawes Al Bahou, Geethan Karunaratne, Renzo Andri, Lukas Cavigelli, Luca Benini	XNORBIN: A 95 TOp/s/W hardware accelerator for binary convolutional neural networks.	COOL CHIPS	2018	DBLP DOI BibTeX RDF
39	Koji Inoue, Takuya Araki, Takumi Maruyama, Pritish Narayanan, Takashi Oshima, Martin Schulz 0001	Panel discussions: "Challenges to the scaling limits: How can we achieve sustainable power-performance improvements?".	COOL CHIPS	2018	DBLP DOI BibTeX RDF
39	Masayuki Sato 0001, Zehua Li, Ryusuke Egawa, Hiroaki Kobayashi	An energy-aware set-level refreshing mechanism for eDRAM last-level caches.	COOL CHIPS	2018	DBLP DOI BibTeX RDF
39	Dionysios Diamantopoulos, Heiner Giefers, Christoph Hagleitner	ecTALK: Energy efficient coherent transprecision accelerators - The bidirectional long short-term memory neural network case.	COOL CHIPS	2018	DBLP DOI BibTeX RDF
39	Takahiro Ichikura, Ryusuke Yamano, Yuma Kikutani, Renyuan Zhang, Yasuhiko Nakashima	EMAXVR: A programmable accelerator employing near ALU utilization to DSA.	COOL CHIPS	2018	DBLP DOI BibTeX RDF