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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 6443 publication records. Showing 6443 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
77 | Patrick Schaumont, Bart Vanthournout, Ivo Bolsens, Hugo De Man |
Synthesis of pipelined DSP accelerators with dynamic scheduling. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
DSP algorithms, FFT butterfly accelerator block, application specific DSP accelerators, highly pipelined data paths, pipelined DSP accelerator synthesis, pipelined bit-parallel hardware, silicon, scheduling, parallel architectures, application specific integrated circuits, dynamic scheduling, pipeline processing, circuit CAD, digital signal processing chips, datapath, controller architecture, network synthesis, run-time schedules |
77 | Hyun-Gyu Kim, Hyeong-Cheol Oh |
A DSP-Enhanced 32-Bit Embedded Microprocessor. |
EUC |
2005 |
DBLP DOI BibTeX RDF |
DSP-enhanced microprocessor, hardware address generator, register extension, embedded microprocessor, SIMD |
71 | Wei-Kai Cheng, Youn-Long Lin |
Code generation of nested loops for DSP processors with heterogeneous registers and structural pipelining. |
ACM Trans. Design Autom. Electr. Syst. |
1999 |
DBLP DOI BibTeX RDF |
code generation, DSP |
71 | Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita |
Power analysis and low-power scheduling techniques for embedded DSP software. |
ISSS |
1995 |
DBLP DOI BibTeX RDF |
circuit state, embedded DSP software, general-purpose commercial microprocessors, instruction-level power model, measurement based power analysis, micro-architectural power model, on-chip Booth multiplier, scheduling, real-time systems, application specific integrated circuits, energy consumption, scheduling algorithm, power analysis, energy minimization, circuit CAD, digital signal processing chips, instruction sets, energy reduction, low-power scheduling, DSP processor |
70 | David Zaretsky, Gaurav Mittal, Xiaoyong Tang, Prithviraj Banerjee |
Overview of the FREEDOM Compiler for Mapping DSP Software to FPGAs. |
FCCM |
2004 |
DBLP DOI BibTeX RDF |
|
70 | Catherine H. Gebotys, Robert J. Gebotys |
Designing for Low Power in Complex Embedded DSP Systems. |
HICSS |
1999 |
DBLP DOI BibTeX RDF |
|
65 | Yung-Chia Lin, Chia-Han Lu, Chung-Ju Wu, Chung-Lin Tang, Yi-Ping You, Ya-Chiao Moo, Jenq Kuen Lee |
Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores. |
J. Signal Process. Syst. |
2008 |
DBLP DOI BibTeX RDF |
ping-pong register files, clustering, parallel processing, compiler, DSP, VLIW |
65 | Jung L. Lee, Myung Hoon Sunwoo |
Implementation of a Wireless Multimedia DSP Chip for Mobile Applications. |
J. VLSI Signal Process. |
2005 |
DBLP DOI BibTeX RDF |
multimedia, DSP, instruction |
64 | J. Geoffrey Chase, Christopher G. Pretty, Alex Bedarida, Philippe Bettler |
An Applications-Based Approach to Measuring DSP Efficiency. |
DELTA |
2002 |
DBLP DOI BibTeX RDF |
Reconfigurable DSP, Signal Processing, DSP Architecture, Application Analysis |
64 | Chung-Kai Chen, Ling-Hua Tseng, Shih-Chang Chen, Young-Jia Lin, Yi-Ping You, Chia-Han Lu, Jenq Kuen Lee |
Enabling compiler flow for embedded VLIW DSP processors with distributed register files. |
LCTES |
2007 |
DBLP DOI BibTeX RDF |
distributed register files, embedded VLIW DSP compilers, software pipelining |
64 | Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen |
A compact DSP core with static floating-point unit & its microcode generation. |
ACM Great Lakes Symposium on VLSI |
2004 |
DBLP DOI BibTeX RDF |
DSP core, digital signal processor, floating-point units |
63 | Chi Wu, Kun-Yuan Hsieh, Yung-Chia Lin, Chung-Ju Wu, Wen-Li Shih, Shih-Chang Chen, Chung-Kai Chen, Chien-Ching Huang, Yi-Ping You, Jenq Kuen Lee |
Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors. |
RTCSA |
2006 |
DBLP DOI BibTeX RDF |
|
63 | Stefanos Kaxiras, Girija J. Narlikar, Alan D. Berenbaum, Zhigang Hu |
Comparing power consumption of an SMT and a CMP DSP for mobile phone workloads. |
CASES |
2001 |
DBLP DOI BibTeX RDF |
|
63 | Catherine H. Gebotys, Robert J. Gebotys |
Complexities in DSP Software Compilation: Performance, Code Size Power, Retargetability. |
HICSS (3) |
1998 |
DBLP DOI BibTeX RDF |
|
59 | Roger F. Woods, John V. McCanny, John G. McWhirter |
From Bit Level Systolic Arrays to HDTV Processor Chips. |
J. Signal Process. Syst. |
2008 |
DBLP DOI BibTeX RDF |
SoC architectures, DSP systems, pipelining, systolic arrays |
57 | Naser Sedaghati-Mokhtari, Mahdi Nazm Bojnordi, Sied Mehdi Fakhraie |
MDST: Multiprocessor DSP Simulation Toolkit for Voice Processing Applications. |
MASCOTS |
2007 |
DBLP DOI BibTeX RDF |
MDST, Multiprocessor DSP Simulation toolkit, Voice processing applications |
57 | Xi-min Wang, Zhe Wang |
Design and Implementation of Memory Pools for Embedded DSP. |
CSSE (2) |
2008 |
DBLP DOI BibTeX RDF |
|
57 | Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chih-Wei Jen |
A Compact DSP Core with Static Floating-Point Arithmetic. |
J. VLSI Signal Process. |
2006 |
DBLP DOI BibTeX RDF |
|
57 | Peter Koch 0001 |
A Project-oriented Master Programme in "DSP Algorithms and ASIC Architectures". |
MSE |
1999 |
DBLP DOI BibTeX RDF |
|
55 | Fabian Vargas 0001, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr., Diogo B. Brum, Eduardo Luis Rhod |
Merging a DSP-Oriented Signal Integrity Technique and SW-Based Fault Handling Mechanisms to Ensure Reliable DSP Systems. |
J. Electron. Test. |
2004 |
DBLP DOI BibTeX RDF |
digital signal processing (DSP) systems, electromagnetic interference (EMI), speech recognition system (SRS), on-line testing, noise immunity |
53 | Uwe Meyer-Bäse, Antonio GarcÃa 0001, Fred J. Taylor |
Implementation of a Communications Channelizer using FPGAs and RNS Arithmetic. |
J. VLSI Signal Process. |
2001 |
DBLP DOI BibTeX RDF |
field-programmable logic (FPL), complex programmable logic devices (CPLD), zero-IF filter, field programmable gate array (FPGA), digital signal processing (DSP), residue number system (RNS), channelizer |
52 | Fei Dai 0001, Jie Wu 0001 |
Efficient Broadcasting in Ad Hoc Wireless Networks Using Directional Antennas. |
IEEE Trans. Parallel Distributed Syst. |
2006 |
DBLP DOI BibTeX RDF |
self-pruning, simulation, broadcasting, directional antennas, Ad hoc wireless networks, localized algorithms |
52 | Fei Dai 0001, Jie Wu 0001 |
Efficient Broadcasting in Ad Hoc Networks Using Directional Antennas. |
NETWORKING |
2005 |
DBLP DOI BibTeX RDF |
|
52 | Prithviraj Banerjee, Vikram Saxena, Juan Ramon Uribe, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, Robert Anderson |
Making area-performance tradeoffs at the high level using the AccelFPGA compiler for FPGAs. |
FPGA |
2003 |
DBLP DOI BibTeX RDF |
|
52 | Meikang Qiu, Zhiping Jia, Chun Xue, Zili Shao, Edwin Hsing-Mean Sha |
Voltage Assignment with Guaranteed Probability Satisfying Timing Constraint for Real-time Multiproceesor DSP. |
J. VLSI Signal Process. |
2007 |
DBLP DOI BibTeX RDF |
real-time, probability, DSP, DVS, assignment |
51 | Catherine H. Gebotys |
DSP address optimization using a minimum cost circulation technique. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
DSP software compliation, DSP addressing, Applied Optimization, Network Flow, software synthesis |
50 | Saulo Oliveira Dornellas Luiz, Genildo de Moura Vasconcelos, Leandro Dias da Silva |
Formal specification of DSP gateway for data transmission between processor cores of OMAP platform. |
SAC |
2008 |
DBLP DOI BibTeX RDF |
OMAP161x platform, modelling, model checking, embedded systems, timed-automata, discrete event systems, inter-processor communication |
50 | Shiv Balakrishnan, Chris Eddington |
Efficient DSP algorithm development for FPGA and ASIC technologies. |
VLSI-SoC |
2007 |
DBLP DOI BibTeX RDF |
|
50 | Robert Bogdan Staszewski, Roman Staszewski, John L. Wallberg, Tom Jung, Chih-Ming Hung, Jinseok Koh, Dirk Leipold, Kenneth Maggio, Poras T. Balsara |
SoC with an integrated DSP and a 2.4-GHz RF transmitter. |
IEEE Trans. Very Large Scale Integr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
50 | Chia-Jui Hsu, Shuvra S. Bhattacharyya |
Porting DSP Applications across Design Tools Using the Dataflow Interchange Format. |
IEEE International Workshop on Rapid System Prototyping |
2005 |
DBLP DOI BibTeX RDF |
|
50 | Hyun-Gyu Kim, Hyeong-Cheol Oh |
A Low-Power DSP-Enhanced 32-Bit EISC Processor. |
HiPEAC |
2005 |
DBLP DOI BibTeX RDF |
|
50 | Yung-Chia Lin, Yuan-Shin Hwang, Jenq Kuen Lee |
Compiler Optimizations with DSP-Specific Semantic Descriptions. |
LCPC |
2002 |
DBLP DOI BibTeX RDF |
|
50 | Sanjive Agarwala, Charles Fuoco, Tim Anderson, Dave Comisky, Christopher Mobley |
A Multi-Level Memory System Architecture for High-Performance DSP Applications. |
ICCD |
2000 |
DBLP DOI BibTeX RDF |
|
48 | Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, Omar Sattari, Michael A. Lai, Jeremy W. Webb, Eric W. Work, Tinoosh Mohsenin, Bevan M. Baas |
Architecture and Evaluation of an Asynchronous Array of Simple Processors. |
J. Signal Process. Syst. |
2008 |
DBLP DOI BibTeX RDF |
programmable DSP, digital signal processing, DSP, multi-core, array processor, GALS, many-core, chip multi-processor, globally asynchronous locally synchronous |
47 | Partha Biswas, Nikil D. Dutt |
Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions. |
IEEE Trans. Computers |
2005 |
DBLP DOI BibTeX RDF |
DSP, VLIW, ASIP, Coprocessors, instruction set extensions, code size reduction |
46 | Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee |
Automatic translation of software binaries onto FPGAs. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
compiler, reconfigurable computing, binary translation, hardware-software co-design, decompilation |
45 | Hani Rizk, Christos A. Papachristou, Francis G. Wolff |
A Self Test Program Design Technique for Embedded DSP Cores. |
J. Electron. Test. |
2006 |
DBLP DOI BibTeX RDF |
self test programs, pseudorandom BIST, LSFR, DSP, ATPG |
44 | Dong-Ik Ko, Shuvra S. Bhattacharyya |
Modeling of Block-Based DSP Systems. |
J. VLSI Signal Process. |
2005 |
DBLP DOI BibTeX RDF |
DSP software synthesis, quasi-static scheduling, memory management, dataflow modeling |
44 | David P. Magee |
Matlab extensions for the development, testing and verification of real-time DSP software. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
C intrinsics, DSP software, optimization, verification, matlab |
44 | Bernhard Rinner, Martin Schmid, Reinhold Weiss |
Rapid Prototyping of Flexible Embedded Systems on Multi-DSP Architectures. |
DATE |
2003 |
DBLP DOI BibTeX RDF |
multi-DSP architectures, task reconfiguration, embedded system, rapid prototyping, testability |
44 | Fabian Vargas 0001, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr., Diogo B. Brum |
Briefing a New Approach to Improve the EMI Immunity of DSP Systems. |
Asian Test Symposium |
2003 |
DBLP DOI BibTeX RDF |
Digital Signal Processing (DSP) Systems, Electromagnetic Interference (EMI), On-Line Testing, Noise Immunity |
44 | Christopher G. Pretty, J. Geoffrey Chase |
Reconfigurable DSP's for Efficient MPEG-4 Video and Audio Decoding. |
DELTA |
2002 |
DBLP DOI BibTeX RDF |
Multimedia, Video, Signal Processing, Audio, MPEG-4, DSP Architecture, Application Analysis |
44 | Y. Wang, Y. Tang, Y. Jiang, Y.-G. Chung, S.-S. Song, M.-S. Lim |
Novel Memory Reference Reduction Methods for FFT Implementations on DSP Processors. |
IEEE Trans. Signal Process. |
2007 |
DBLP DOI BibTeX RDF |
|
44 | Ashish Mathur, Sourav Roy, Rajat Bhatia, Arup Chakraborty, Vijay Bhargava, Jatin Bhartia |
JouleQuest: An Accurate Power Model for the StarCore DSP Platform. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
44 | Behzad Akbarpour, Sofiène Tahar |
An approach for the formal verification of DSP designs using Theorem proving. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
44 | Chung-Ju Wu, Sheng-Yuan Chen, Jenq Kuen Lee |
Copy Propagation Optimizations for VLIW DSP Processors with Distributed Register Files. |
LCPC |
2006 |
DBLP DOI BibTeX RDF |
|
44 | Yung-Chia Lin, Chung-Lin Tang, Chung-Ju Wu, Ming-Yu Hung, Yi-Ping You, Ya-Chiao Moo, Sheng-Yuan Chen, Jenq Kuen Lee |
Compiler Supports and Optimizations for PAC VLIW DSP Processors. |
LCPC |
2005 |
DBLP DOI BibTeX RDF |
|
44 | Catherine H. Gebotys, Robert J. Gebotys |
An empirical comparison of algorithmic, instruction, and architectural power prediction models for high performance embedded DSP processors. |
ISLPED |
1998 |
DBLP DOI BibTeX RDF |
|
44 | Anissa Zergaïnoh, Pierre Duhamel, Jean Pierre Vidal |
Efficient Implementation Methodology of Fast FIR Filtering Algorithms on DSP. |
J. VLSI Signal Process. |
1997 |
DBLP DOI BibTeX RDF |
|
41 | Byeong-Doo Choi, Min-Cheol Hwang, Ju-Hun Nam, Kyung-Hoon Lee, Sung-Jea Ko |
High-Performance Motion-JPEG2000 Encoder Using Overlapped Block Transferring and Pipelined Processing. |
PCM (2) |
2004 |
DBLP DOI BibTeX RDF |
OBT, Wavelet, DSP, JPEG2000 |
40 | Mohammad H. Tehranipour, Seid Mehdi Fakhraie, Zainalabedin Navabi, M. R. Movahedin |
A Low-Cost At-Speed BIST Architecture for Embedded Processor and SRAM Cores. |
J. Electron. Test. |
2004 |
DBLP DOI BibTeX RDF |
BIST architecture, DSP/microprocessor, UTS-DSP, bit/word-oriented memory, memory testing, march test |
40 | Inki Hong, Miodrag Potkonjak, Ramesh Karri |
Power optimization using divide-and-conquer techniques for minimization of the number of operations. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
DSP computations, architectural techniques, divide-and-conquer compilation, portable wireless DSP applications, compilation, power consumption, data flow graphs |
40 | Partha Biswas, Nikil D. Dutt |
Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensions. |
CASES |
2003 |
DBLP DOI BibTeX RDF |
dependence conflict graph, heterogeneous-connectivity-based DSP, restricted data dependence graph, instruction set extensions, instruction set architecture, static single assignment |
39 | Uwe Meyer-Bäse, Suhasini Rao, Javier RamÃrez 0001, Antonio GarcÃa 0001 |
Area*Time Optimized Hogenauer Channelizer Design Using FPL Devices. |
FPL |
2004 |
DBLP DOI BibTeX RDF |
|
39 | B. Bosi, Guy Bois, Yvon Savaria |
Reconfigurable pipelined 2-D convolvers for fast digital signal processing. |
IEEE Trans. Very Large Scale Integr. Syst. |
1999 |
DBLP DOI BibTeX RDF |
|
39 | Sati Banerjee, Paul M. Chau, Ronald D. Fellman |
Rapid prototyping methodology for multiprocessor implementation of digital signal processing systems. |
J. VLSI Signal Process. |
1995 |
DBLP DOI BibTeX RDF |
|
38 | Guoqiang Xu, Mei Xie |
License Plate Multi-DSP and Multi-FPGA Design and Realization in Highway Toll System. |
ISICA |
2009 |
DBLP DOI BibTeX RDF |
FPGA, DSP, License Plate Recognition |
38 | Jianbin Huang, Zongwu Xie, Hong Liu 0002, Kai Sun, Yechao Liu, Zainan Jiang |
DSP/FPGA-based Controller Architecture for Flexible Joint Robot with Enhanced Impedance Performance. |
J. Intell. Robotic Syst. |
2008 |
DBLP DOI BibTeX RDF |
M-LVDS serial data bus, Torque ripple, FPGA, DSP, Impedance control, Flexible joint |
38 | Messaoud Ahmed Ouameur, Daniel Massicotte |
Real-time DSP and FPGA Implementation of Wiener LMS Based Multipath Channel Estimation in 3G CDMA Systems. |
J. VLSI Signal Process. |
2007 |
DBLP DOI BibTeX RDF |
delay acquisition, Wiener LMS, FPGA, VLSI, FFT, DSP, WCDMA, channel estimation, cdma2000 |
38 | Hai Yan, Shengli Zhou, Zhijie Jerry Shi, Baosheng Li |
A DSP implementation of OFDM acoustic modem. |
Underwater Networks |
2007 |
DBLP DOI BibTeX RDF |
acoustic modem, DSP, OFDM, multicarrier |
38 | Atsushi Hatabu, Takashi Miyazaki, Ichiro Kuroda |
QVGA/CIF Resolution MPEG-4 Video Codec Based on a Low-Power and General-Purpose DSP. |
J. VLSI Signal Process. |
2005 |
DBLP DOI BibTeX RDF |
PD77210, successive similarity detection algorithm (SSDA), DMA queue, low power, motion estimation, DSP, MPEG-4, computational cost |
38 | Brad L. Hutchings, Brent E. Nelson |
GigaOp DSP on FPGA. |
J. VLSI Signal Process. |
2004 |
DBLP DOI BibTeX RDF |
FPGA, DSP |
38 | Daniel Ménard, Daniel Chillet, François Charot, Olivier Sentieys |
Automatic floating-point to fixed-point conversion for DSP code generation. |
CASES |
2002 |
DBLP DOI BibTeX RDF |
digital signal processing systems, floating-point to fixed-point conversion, quantization noise, code generation, DSP, fixed-point |
37 | Daw-Tung Lin, Chung-Yu Yang |
H.264/AVC Video Encoder Realization and Acceleration on TI DM642 DSP. |
PSIVT |
2009 |
DBLP DOI BibTeX RDF |
H.264/AVC encoder, TM320DM642 DSP, optimization, motion estimation, quantization, mode decision |
37 | Kun-Yuan Hsieh, Yung-Chia Lin, Chien-Ching Huang, Jenq Kuen Lee |
Enhancing Microkernel Performance on VLIW DSP Processors via Multiset Context Switch. |
J. Signal Process. Syst. |
2008 |
DBLP DOI BibTeX RDF |
VLIW DSP processor, optimizing context switch overhead, microkernel design |
37 | Erik Schüler, Marcelo Ienczczak Erigson, Luigi Carro |
Functionally Fault-tolerant DSP Microprocessor using Sigma-delta Modulated Signals. |
J. Electron. Test. |
2007 |
DBLP DOI BibTeX RDF |
error tolerant system, single event upset (SEU), Digital SignalProcessing (DSP), fault-tolerance, sigma-delta |
37 | Yu-Chun Peng, Meng-Ting Lu, Homer H. Chen |
DSP implementation of digital image stabilizer. |
ICME |
2005 |
DBLP DOI BibTeX RDF |
BF561 analog device, DSP implementation, digital image stabilization algorithm, hand-held video camera, block-based motion estimation, image sequence, digital signal processing, median filter |
37 | Wei Zhao, Christos A. Papachristou |
Synthesis of reusable DSP cores based on multiple behaviors. |
ICCAD |
1996 |
DBLP DOI BibTeX RDF |
RTL components, RTL structure, design process complexity, design time, multiple behaviors, reusable DSP cores synthesis, digital signal processing chips |
37 | Ming-Yung Ko, Chung-Ching Shen, Shuvra S. Bhattacharyya |
Memory-constrained Block Processing for DSP Software Optimization. |
J. Signal Process. Syst. |
2008 |
DBLP DOI BibTeX RDF |
block processing, block diagram compiler, activation overhead, embedded systems, memory management, vectorization, dataflow, context switch |
37 | Tay-Jyi Lin, Shin-Kai Chen, Yu-Ting Kuo, Chih-Wei Liu, Pi-Chen Hsiao |
Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications. |
J. Signal Process. Syst. |
2008 |
DBLP DOI BibTeX RDF |
register organization, VLIW, digital signal processor, micro-architecture, instruction encoding |
37 | Cameron H. G. Wright, Michael G. Morrow, Mark C. Allie, Thad B. Welch |
Enhancing engineering education and outreach using real-time DSP. |
ICASSP |
2008 |
DBLP DOI BibTeX RDF |
|
37 | Hongfu Zhou |
DC Servo System Design Based on Fuzzy Control with DSP. |
ICNSC |
2008 |
DBLP DOI BibTeX RDF |
|
37 | Ming-Yung Ko, Praveen K. Murthy, Shuvra S. Bhattacharyya |
Beyond single-appearance schedules: Efficient DSP software synthesis using nested procedure calls. |
ACM Trans. Embed. Comput. Syst. |
2007 |
DBLP DOI BibTeX RDF |
block diagram compiler, hierarchical graph decomposition, procedural implementation, embedded systems, design methodology, memory optimization, Synchronous dataflow |
37 | Chien-Chih Liu, Hsueh-Ming Hang |
Acceleration and Implementation of JPEG2000 Encoder on TI DSP Platform. |
ICIP (3) |
2007 |
DBLP DOI BibTeX RDF |
|
37 | Nelson Yen-Chung Chang, Ting-Min Lin, Tsung-Hsien Tsai, Yu-Cheng Tseng, Tian-Sheuan Chang |
Real-Time DSP Implementation on Local Stereo Matching. |
ICME |
2007 |
DBLP DOI BibTeX RDF |
|
37 | Babak Zamanlooy, Vahid Hamiati Vaghef, Sattar Mirzakuchaki, Ali Shojaee Bakhtiari, Reza Ebrahimi Atani |
A Real Time Infrared Imaging System Based on DSP & FPGA. |
PSIVT |
2007 |
DBLP DOI BibTeX RDF |
IRFPA, Nonuniformity Detection, Nonuniformity Correction |
37 | Ming-Yung Ko, Chung-Ching Shen, Shuvra S. Bhattacharyya |
Memory-constrained Block Processing Optimization for Synthesis of DSP Software. |
ICSAMOS |
2006 |
DBLP DOI BibTeX RDF |
|
37 | Ying Yi, Mark Milward, Sami Khawam, Ioannis Nousias, Tughrul Arslan |
Automatic synthesis and scheduling of multirate DSP algorithms. |
ASP-DAC |
2005 |
DBLP DOI BibTeX RDF |
|
37 | Ming-Yung Ko, Praveen K. Murthy, Shuvra S. Bhattacharyya |
Compact Procedural Implementation in DSP Software Synthesis Through Recursive Graph Decomposition. |
SCOPES |
2004 |
DBLP DOI BibTeX RDF |
|
37 | Kiyotaka Takahashi, Eigo Mori |
Architectural Design of a DSP Scripting Language for Mobile Multimedia Terminals. |
AINA (2) |
2004 |
DBLP DOI BibTeX RDF |
|
37 | Jae Sung Lee, Myung Hoon Sunwoo |
Design of New DSP Instructions and Their Hardware Architecture for High-Speed FFT. |
J. VLSI Signal Process. |
2003 |
DBLP DOI BibTeX RDF |
application specific digital signal processor, DMT, fast Fourier transform, OFDM |
37 | Madhubanti Mukherjee, Ranga Vemuri |
A Novel Synthesis Strategy Driven by Partial Evaluation Based Circuit Reduction for Application Specific DSP Circuits. |
ICCD |
2003 |
DBLP DOI BibTeX RDF |
|
37 | Ya-Lan Tsao, Ming Hsuan Tan, Jun-Xian Teng, Shyh-Jye Jou |
Parameterized and low power DSP core for embedded systems. |
ISCAS (5) |
2003 |
DBLP DOI BibTeX RDF |
|
37 | Francesco Pessolano, Joep L. W. Kessels, Ad M. G. Peeters |
MDSP: A High-Performance Low-Power DSP Architecture. |
PATMOS |
2002 |
DBLP DOI BibTeX RDF |
|
37 | Shyh-Jye Jou, Hsiao Ping Lee, Yi-Ting Chen, Ming Hsuan Tan, Ya-Lan Tsao |
An embedded DSP core for wireless communication. |
ISCAS (4) |
2002 |
DBLP DOI BibTeX RDF |
|
37 | Jung Hoo Lee, Jae Sung Lee, Myung Hoon Sunwoo, Kyung Ho Kim |
Design of new DSP instructions and their hardware architecture for the Viterbi decoding algorithm. |
ISCAS (5) |
2002 |
DBLP DOI BibTeX RDF |
|
37 | Anu Purhonen |
Quality Attribute Taxonomies for DSP Software Architecture Design. |
PFE |
2001 |
DBLP DOI BibTeX RDF |
|
37 | Mike J. G. Lewis, L. E. M. Brackenbury |
Exploiting Typical DSP Data Access Patterns and Asynchrony for a Low Power Multiported Register Bank. |
ASYNC |
2001 |
DBLP DOI BibTeX RDF |
|
37 | Ajit Gupte, Mahesh Mehendale, Ramesh Ramamritham, Deepa Nair |
Performance Considerations in Embedded DSP based System-On-a-Chip Designs. |
VLSI Design |
2001 |
DBLP DOI BibTeX RDF |
|
37 | S. Ramanathan, S. K. Nandy 0001, V. Visvanathan |
Reconfigurable Filter Coprocessor Architecture for DSP Applications. |
J. VLSI Signal Process. |
2000 |
DBLP DOI BibTeX RDF |
reconfigurable coprocessors, filter coprocessor architecture, systolic architectures and digital signal processing, pipelined architectures, low-power architectures |
37 | David W. Currie, Alan J. Hu, Sreeranga P. Rajan |
Automatic formal verification of DSP software. |
DAC |
2000 |
DBLP DOI BibTeX RDF |
|
37 | Soohwan Ong, Hyunjune Yoo, Myung Hoon Sunwoo |
A MDSP (multimedia DSP) chip for portable multimedia applications. |
ISCAS (4) |
1999 |
DBLP DOI BibTeX RDF |
|
37 | Ingrid Verbauwhede, Mihran Touriguian |
A Low Power DSP Engine for Wireless Communications. |
J. VLSI Signal Process. |
1998 |
DBLP DOI BibTeX RDF |
|
37 | Hanho Lee, Gerald E. Sobelman |
Digit-Serial DSP Library for Optimized FPGA Configuration. |
FCCM |
1998 |
DBLP DOI BibTeX RDF |
|
37 | Patrick Schaumont, Bart Vanthournout, Ivo Bolsens, Hugo De Man |
Synthesis of pipelined DSP accelerators with dynamic scheduling. |
IEEE Trans. Very Large Scale Integr. Syst. |
1997 |
DBLP DOI BibTeX RDF |
|
37 | Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita |
Power analysis and minimization techniques for embedded DSP software. |
IEEE Trans. Very Large Scale Integr. Syst. |
1997 |
DBLP DOI BibTeX RDF |
|
37 | Catherine H. Gebotys |
An optimal methodology for synthesis of DSP multichip architectures. |
J. VLSI Signal Process. |
1995 |
DBLP DOI BibTeX RDF |
|
37 | Pierre G. Paulin, Clifford Liem, Trevor C. May, Shailesh Sutarwala |
DSP design tool requirements for embedded systems: A telecommunications industrial perspective. |
J. VLSI Signal Process. |
1995 |
DBLP DOI BibTeX RDF |
|
35 | Ne Kyaw Zwa Lwin, H. Sivaramakrishnan, Kwen-Siong Chong, Tong Lin 0001, Wei Shu, Joseph S. Chang |
Single-Event-Transient Resilient Memory for DSP in Space Applications. |
DSP |
2018 |
DBLP DOI BibTeX RDF |
|
35 | Ahmad Moniri, Ilia Kisil, Anthony G. Constantinides, Danilo P. Mandic |
Refreshing DSP Courses through Biopresence in the Curriculum: A Successful Paradigm. |
DSP |
2018 |
DBLP DOI BibTeX RDF |
|
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