Search results for "ECL"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
121	Ty Mey Eap, Marek Hatala, Griff Richards	Digital repository interoperability: design, implementation and deployment of the ecl protocol and connecting middleware.	WWW (Alternate Track Papers & Posters)	2004	DBLP DOI BibTeX RDF	middleware, protocols, interoperability
98	Xuegang Hu, Yuhong Zhang 0002, Xinya Wang	The Representation and Resolution of Rough Sets Based on the Extended Concept Lattice.	FSKD (1)	2005	DBLP DOI BibTeX RDF	Rough set, Rule, KDD, Concept Lattice
92	João Navarro Jr., Reinaldo Silveira, Fábio L. Romao, Wilhelmus A. M. Van Noije	A 1.4 Gbit/s CMOS driver for 50 Ω ECL systems.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF	CMOS driver, ECL systems, speed performance, effective length, circuit operation, current source switching, output load, SDH/SONET system, CMOS-ECL convertor output buffer, 0.8 mum, 0.7 mum, 1.4 Gbit/s, 50 ohm, CMOS logic circuits, output buffer
82	Martin Hepp, Jörg Leukel, Volker Schmitz	A quantitative analysis of product categorization standards: content, coverage, and maintenance of eCl@ss, UNSPSC, eOTD, and the RosettaNet Technical Dictionary.	Knowl. Inf. Syst.	2007	DBLP DOI BibTeX RDF	Products and services classification, UNSPSC, eCl@ss, RosettaNet, Ontologies, Metrics, Electronic commerce, Electronic catalogs
72	Francesco Centurelli, G. Lulli, Piero Marietti, Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti	High-speed CMOS-to-ECL pad driver in 0.18µm CMOS.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
72	Massimo Alioto, Gaetano Palumbo	Highly accurate and simple models for CML and ECL gates.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
72	Elizabeth J. Brauer, Sung-Mo Kang	An algorithm for functional verification of digital ECL circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
56	Yasushi Ogawa, Tatsuki Ishii, Yoichi Shiraishi, Hidekazu Terai, Tokinori Kozawa, Kyoji Yuyama, Kyoji Chiba	Efficient placement algorithms optimizing delay for high-speed ECL masterslice LSIs.	DAC	1986	DBLP DOI BibTeX RDF
56	Takuji Ogihara, Shuichi Saruyama, Shinichi Murai	PATEGE: an automatic DC parametric test generation system for series gated ECL circuits.	DAC	1985	DBLP DOI BibTeX RDF
49	Marek Hatala, Griff Richards, Timmy Eap, Jordan Willms	The interoperability of learning object repositories and services: standards, implementations and lessons learned.	WWW (Alternate Track Papers & Posters)	2004	DBLP DOI BibTeX RDF	interoperability, learning object repositories
49	Stepan P. Nadrchal	Event Language for Real-Time On-the-Fly Control According to the Initial Requirements.	Ada-Europe	2004	DBLP DOI BibTeX RDF
49	Jean-François Raskin, Pierre-Yves Schobbens, Thomas A. Henzinger	Axioms for Real-Time Logics.	CONCUR	1998	DBLP DOI BibTeX RDF
42	Martin Hepp, Jos de Bruijn	GenTax: A Generic Methodology for Deriving OWL and RDF-S Ontologies from Hierarchical Classifications, Thesauri, and Inconsistent Taxonomies.	ESWC	2007	DBLP DOI BibTeX RDF	RDF-S, UNSPSC, eCl@ss, classifications, reuse, OWL, taxonomies, e-business, Ontology engineering, ontology learning, thesauri
40	Paul Rabinovich	ECL: A TLS Extension for Authentication in Complex PKIs.	ICYCS	2008	DBLP DOI BibTeX RDF
40	Mohamed Hammami, Dzmitry V. Tsishkou, Liming Chen 0002	Data-Mining Based Skin-Color Modeling Using the ECL Skin-Color Images Database.	International Conference on Computational Science	2004	DBLP DOI BibTeX RDF
40	Andrew T. Yang, Yu-Hsu Chang, Daniel G. Saab, Ibrahim N. Hajj	Switch-level timing simulation of bipolar ECL circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
40	James B. Kuo, Tsen-Shau Yang, Robert W. Dutton, Bruce A. Wooley	Two-dimensional transient analysis of a collector-up ECL inverter.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
33	Tomoyuki Yamada	Logical Dynamics of Commands and Obligations.	JSAI	2006	DBLP DOI BibTeX RDF
33	Martin Hepp, Jörg Leukel, Volker Schmitz	Content Metrics for Products and Services Categorization Standards.	EEE	2005	DBLP DOI BibTeX RDF
33	Magy Seif El-Nasr, Ian Horswill	Automating Lighting Design for Interactive Entertainment.	Comput. Entertain.	2004	DBLP DOI BibTeX RDF	3-D simulations, visual compositing, game design, visual design, game development, immersive environments, Interactive entertainment, lighting design
33	Marek Hatala, Griff Richards, Timmy Eap, Jordan Willms	The eduSource Communication Language: implementing open network for learning repositories and services.	SAC	2004	DBLP DOI BibTeX RDF	interoperability, learning object repositories
33	Vojin G. Oklobdzija	An algorithmic and novel design of a leading zero detector circuit: comparison with logic synthesis.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
33	Derek C. Wong, Giovanni De Micheli, Michael J. Flynn	Designing high-performance digital circuits using wave pipelining: algorithms and practical experiences.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
33	M. Chastain, G. Gostin, James E. Mankovich, Steven J. Wallach	The convex C240 architecture.	SC	1988	DBLP DOI BibTeX RDF
27	Steve Brown, Germán Gutiérrez, Reed Nelson, Chris VanKrevelen	A gate-array based 500 MHz triple channel ATE controller with 40 pS timing verniers.	VTS	1995	DBLP DOI BibTeX RDF	emitter-coupled logic, triple channel ATE controller, timing verniers, precision edge timing, drive waveforms, returning signals, system clock frequency, ECL, 500 MHz, 40 ps, timing, clocks, automatic test equipment, logic arrays, programmable controllers, gate array, high speed testing
26	Martin Hepp	GoodRelations: An Ontology for Describing Products and Services Offers on the Web.	EKAW	2008	DBLP DOI BibTeX RDF	eClassOWL, UNSPSC, eCl@ss, Semantic Web, E-Commerce, E-Procurement
26	Tatsuo Higuchi 0001, Michitaka Kameyama	Static-Hazard-Free T-Gate for Ternary Memory Element and Its Application to Ternary Counters.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	Counter based on shift register, emitter coupled logic (ECL), feedback shift register (FSR), signed ternary number representation, static-hazard-free T-gate, symmetrical modulo-M counter, synchronous and asynchronous signed ternary counter, ternary memory element, up-down counting
26	Daniel Etiemble, Michel Israël	Implementation of Ternary Circuits with Binary Integrated Circuits.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	Circuit realization of multivalued functions, COSMOS integrated circuits, ECL integrated circuits, fundamental ternary circuits, multivalued circuits, ternary logic implementation, TTL integrated circuits, combinational circuits
23	Yunsheng Zhang, Zijing Ren, Zichen Ding, Hong Qian, Haiqiang Li, Chao Tao	Co-ECL: Covariant Network with Equivariant Contrastive Learning for Oriented Object Detection in Remote Sensing Images.	Remote. Sens.	2024	DBLP DOI BibTeX RDF
23	Henri Arno, Klaas Mulier, Joke Baeck, Thomas Demeester	From Numbers to Words: Multi-Modal Bankruptcy Prediction Using the ECL Dataset.	CoRR	2024	DBLP DOI BibTeX RDF
23	Chen Zhou 0004, Shuaijian Dai, Shengzhi Lai, Yuanqiao Lin, Xuechen Zhang 0002, Ning Li, Weichuan Yu	ECL 3.0: a sensitive peptide identification tool for cross-linking mass spectrometry data analysis.	BMC Bioinform.	2023	DBLP DOI BibTeX RDF
23	Yilan Zhang, Jianqi Chen, Ke Wang, Fengying Xie	ECL: Class-Enhancement Contrastive Learning for Long-tailed Skin Lesion Classification.	CoRR	2023	DBLP DOI BibTeX RDF
23	Sam Bourgault, Jennifer Jacobs 0001	Expressive Computation Lab (ECL): UC Santa Barbara.	XRDS	2023	DBLP DOI BibTeX RDF
23	Yilan Zhang, Jianqi Chen, Ke Wang, Fengying Xie	ECL: Class-Enhancement Contrastive Learning for Long-Tailed Skin Lesion Classification.	MICCAI (2)	2023	DBLP DOI BibTeX RDF
23	Sicheng Hu, Zhongyuan Wang 0001, Peng Yi 0002, Zheng He, Jinsheng Xiao, Jing Xiao 0004	ECL: Exclusive Curriculum Learning for Video Super-Resolution.	ICME	2022	DBLP DOI BibTeX RDF
23	Joseph Taylor, Elmer Ccopa Rivera, Solomon Kim, Reise Campbell, Rodney L. Summerscales, Hyun J. Kwon	Machine Learning Analysis for Phenolic Compound Monitoring Using a Mobile Phone-Based ECL Sensor.	Sensors	2021	DBLP DOI BibTeX RDF
23	Wenxiang Zhen, Shaojun Li, Shurui Cao, Yongbo Su, Zhi Jin	A broadband high bandwidth utilization ECL static frequency divider in InP DHBT process.	IEICE Electron. Express	2020	DBLP DOI BibTeX RDF
23	Daniel Kochmanski	On ECL, the Embeddable Common Lisp (ELS keynote).	ELS	2020	DBLP BibTeX RDF
23	Yilin Xu, Pascal Maier, Matthias Blaicher, Philipp-Immanuel Dietrich, Pablo Marin-Palomo, Wladislaw Hartmann, Muhammad Rodlin Billah, Ute Troppenz, Martin Möhrle, Sebastian Randel, Wolfgang Freude, Christian Koos	InP/Silicon Hybrid External-Cavity Lasers (ECL) using Photonic Wirebonds as Coupling Elements.	OFC	2020	DBLP BibTeX RDF
23	Mahdi Tala, Oliver Schrape, Milos Krstic, Davide Bertozzi	Interfacing 3D-stacked Electronic and Optical NoCs with Mixed CMOS-ECL Bridges: a Realistic Preliminary Assessment.	ACM Great Lakes Symposium on VLSI	2018	DBLP DOI BibTeX RDF
23	Alex Stolz, Martin Hepp	Integrating Product Classification Standards into Schema.org: eCl@ss and UNSPSC on the Web of Data.	OTM Workshops	2017	DBLP DOI BibTeX RDF
23	Dieynaba Mall, Karim Konaté, Al-Sakib Khan Pathan	ECL-EKM: An enhanced Certificateless Effective Key Management protocol for dynamic WSN.	NSysS	2017	DBLP DOI BibTeX RDF
23	Lili Xu, Edin Muharemagic, Amy W. Apon	ECL-watch: A big data application performance tuning tool in the HPCC systems platform.	IEEE BigData	2017	DBLP DOI BibTeX RDF
23	Fengchao Yu, Ning Li, Weichuan Yu	ECL: an exhaustive search tool for the identification of cross-linked peptides using whole database.	BMC Bioinform.	2016	DBLP DOI BibTeX RDF
23	Anthony M. Middleton, David Alan Bayliss, Gavin Halliday, Arjuna Chala, Borko Furht	The HPCC/ECL Platform for Big Data.	Big Data Technologies and Applications	2016	DBLP DOI BibTeX RDF
23	Paolo Gentilini, Maurizio Martelli, Giuseppe Rosolini	Explicit Constructive Logic ECL: a New Representation of Construction and Selection of Logical Information by an Epistemic Agent.	Fundam. Informaticae	2015	DBLP DOI BibTeX RDF
23	Fukang Luo, Guimin Xiang, Xiaoyun Pu, Juanchun Yu, Ming Chen, Guohui Chen	A Novel Ultrasensitive ECL Sensor for DNA Detection Based on Nicking Endonuclease-Assisted Target Recycling Amplification, Rolling Circle Amplification and Hemin/G-Quadruplex.	Sensors	2015	DBLP DOI BibTeX RDF
23	Oliver Schrape, Markus Appel, Frank Winkler 0001, Milos Krstic	Low-power design methodology for CML and ECL circuits.	PATMOS	2014	DBLP DOI BibTeX RDF
23	Chia-Cheng Zhu, Chung-Nan Lee	Improvement of Small-write Performance Using the ECL-based Technique.	MoMM	2014	DBLP DOI BibTeX RDF
23	Paolo Gentilini, Maurizio Martelli	Explicit Constructive Logic ECL: a New Representation of Construction and Selection of Logical Information by an Epistemic Agent.	CILC	2013	DBLP BibTeX RDF
23	Oliver Schrape, Markus Appel, Frank Winkler 0001, Milos Krstic	A 12 Gb/s standard cell based ECL 4: 1 serializer with asynchronous parallel interface.	ICECS	2013	DBLP DOI BibTeX RDF
23	Chao Zhu 0003, Boyang Gao, Charles-Edmond Bichot, Emmanuel Dellandréa, Liming Chen 0002, Ningning Liu, Yu Zhang 0052	ECL-LIRIS at TrecVid 2011: Semantic Indexing.	TRECVID	2011	DBLP BibTeX RDF
23	Alberto J. Palma, Miguel A. Carvajal, Nuria López-Ruiz, Julio Ballesta-Claver, Maria del Carmen Valencia-Mirón, Luis F. Capitán-Vallvey	Portable Instrumentation Platform for Ecl-based Sensors and Biosensors.	BIODEVICES	2011	DBLP BibTeX RDF
23	Frank Winkler 0001, Gerald Kell, Oliver Schrape, Hans Gustat, Ulrich Jagdhold	HDL-Synthese und Simulation von Hochgeschwindigkeits-Digitalschaltungen mit gemischten CMOS- und ECL-Bibliotheken.	MBMV	2009	DBLP BibTeX RDF
23	Antonio Martínez-Olmos, Alberto J. Palma, Julio Ballesta-Claver, Maria del Carmen Valencia-Mirón, Luis F. Capitán-Vallvey	Hand-held Luminometer with ECL-based Biosensor for Lactate Determination.	BIODEVICES	2009	DBLP BibTeX RDF
23	David B. Cedrés, Eric Gamess	ECL Experiments Control Language for Scientific Computing.	PDPTA	2008	DBLP BibTeX RDF
23	Alfio Dario Grasso, Gaetano Palumbo	Optimized design of ECL gates with a power constraint.	ECCTD	2005	DBLP DOI BibTeX RDF
23	Friedhelm Hausmann, Thomas Einsporn	eCl@ss - The leading classification system.	GI Jahrestagung (2)	2005	DBLP BibTeX RDF
23	C. Zhang, P. Yalamanchili, M. Al-Sheikhley, Aris Christou	Metal migration in epoxy encapsulated ECL devices.	Microelectron. Reliab.	2004	DBLP DOI BibTeX RDF
23	Lluís Ribas, Joaquín Saiz	On Hardware Description in ECL.	FDL	2003	DBLP BibTeX RDF
23	Kenichi Ohhata, Fumihiko Arakawa, Takeshi Kusunoki, Hiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Masahiko Nishiyama, Kunihiko Yamaguchi, Noriyuki Homma, Atsuo Hotta	Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an access time of 550 ps and an operating frequency of 900 MHz.	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
23	Hiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Masahiko Nishiyama, Kenichi Ohhata, Fumihiko Arakawa, Takeshi Kusunoki, Kunihiko Yamaguchi, Atsuo Hotta, Noriyuki Homma	A 550-ps access 900-MHz 1-Mb ECL-CMOS SRAM.	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
23	Min-Hsing P. Chen, André Ivanov, Sassan Tabatabaei	Defect Oriented Testing of an ECL/CMOS Level Converter Circuit.	LATW	2000	DBLP BibTeX RDF
23	Hormoz Djahanshahi, Flemming Hansen, C. André T. Salama	Gigabit-per-second, ECL-compatible I/O interface in 0.35-μm CMOS.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
23	Hormoz Djahanshahi, Flemming Hansen, C. André T. Salama	Giga bit per second per pin differential CMOS circuits for pseudo ECL signaling.	CICC	1999	DBLP DOI BibTeX RDF
23	Luciano Lavagno, Ellen Sentovich	ECL: A Specification Environment for System-Level Design.	DAC	1999	DBLP DOI BibTeX RDF
23	Andrea Diermeier	Interfacing between LVDS and ECL.	Microprocess. Microsystems	1998	DBLP DOI BibTeX RDF
23	Hormoz Djahanshahi, Flemming Hansen, C. André T. Salama	High-speed ECL-compatible serial I/O in 0.35 μm CMOS.	ICECS	1998	DBLP DOI BibTeX RDF
23	Vojin G. Oklobdzija	An ECL gate with improved speed and low power in a BiCMOS process.	IEEE J. Solid State Circuits	1996	DBLP DOI BibTeX RDF
23	Kimio Ueda, Nagisa Sasaki, Hisayasu Sato, Koichiro Mashiko	A fully compensated active pull-down ECL circuit with self-adjusting driving capability.	IEEE J. Solid State Circuits	1996	DBLP DOI BibTeX RDF
23	Keiichi Higeta, Masami Usami, Masayuki Ohayashi, Yasuhiro Fujimura, Masahiko Nishiyama, Satoru Isomura, Kunihiko Yamaguchi, Youji Idei, Hiroaki Nambu, Kenichi Ohhata, Nadateru Hanta	A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry.	IEEE J. Solid State Circuits	1996	DBLP DOI BibTeX RDF
23	Norman P. Jouppi, Stefanos Sidiropoulos, Suresh Menon	A speed, power, and supply noise evaluation of ECL driver circuits.	IEEE J. Solid State Circuits	1996	DBLP DOI BibTeX RDF
23	Tadahiro Kuroda, Tetsuya Fujita, Makato Noda, Yasushi Itabashi, Satohiko Kabumoto, T. S. Wong, Dave Beeson, Dave Gray	Capacitor-free level-sensitive active pull-down ECL circuit with self-adjusting driving capability.	IEEE J. Solid State Circuits	1996	DBLP DOI BibTeX RDF
23	Khaled M. Sharaf, Mohamed I. Elmasry	Analysis and optimization of series-gated CML and ECL high-speed bipolar circuits.	IEEE J. Solid State Circuits	1996	DBLP DOI BibTeX RDF
23	Sankaran M. Menon, Yashwant K. Malaiya, Anura P. Jayasumana	Fault Modeling of ECL for High Fault Coverage of Physical Defects.	VLSI Design	1996	DBLP DOI BibTeX RDF
23	C. T. Chuang, B. Wu, C. J. Anderson	High-speed low-power cross-coupled active-pull-down ECL circuit.	IEEE J. Solid State Circuits	1995	DBLP DOI BibTeX RDF
23	Loke Kun Tan, Edward W. Roth, Gordon E. Yee, Henry Samueli	An 800-MHz quadrature digital synthesizer with ECL-compatible output drivers in 0.8 μm CMOS.	IEEE J. Solid State Circuits	1995	DBLP DOI BibTeX RDF
23	Martin Rau, Hans-Jörg Pfleiderer	An ECL to CMOS level converter with complementary bipolar output stage.	IEEE J. Solid State Circuits	1995	DBLP DOI BibTeX RDF
23	Hiroalu Nambu, Kazuo Kanetani, Youji Idei, Tom Masuda, Keiichi Higeta, Masayuki Ohayashi, Masami Usami, Kunihiko Yamaguchi, Toshiyuki Kikuchi, Takahide Ikeda, Kenichi Ohhata, Takeshi Kusunoki, Noriyuki Homma	A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM.	IEEE J. Solid State Circuits	1995	DBLP DOI BibTeX RDF
23	Akira Onozawa, Hitoshi Kitazawa, Kenji Kawai	Post-layout optimization of power and timing for ECL LSIs.	ED&TC	1995	DBLP DOI BibTeX RDF
23	Udo Jorczyk, Wilfried Daehn, Oliver Neumann	Fault modeling of differential ECL.	EURO-DAC	1995	DBLP DOI BibTeX RDF
23	Richard X. Gu, Mohamed I. Elmasry	High-speed dynamic reference voltage (DRV) CMOS/ECL interface circuits.	IEEE J. Solid State Circuits	1994	DBLP DOI BibTeX RDF
23	C. T. Chuang, K. Chin	High-speed low-power direct-coupled complementary push-pull ECL circuit.	IEEE J. Solid State Circuits	1994	DBLP DOI BibTeX RDF
23	Norman P. Jouppi, Patrick D. Boyle, John S. Fitch	Designing, packaging, and testing a 300-MHz, 115 W ECL microprocessor.	IEEE Micro	1994	DBLP DOI BibTeX RDF
23	Khaled M. Sharaf, Mohamed I. Elmasry	Low-power differential CML and ECL BiCMOS circuit techniques.	Great Lakes Symposium on VLSI	1994	DBLP DOI BibTeX RDF
23	Robert N. Mayo, Hervé J. Touati	Boolean matching for full-custom ECL gates.	ICCAD	1993	DBLP DOI BibTeX RDF
23	Elizabeth J. Brauer, Sung-Mo Kang	Functional Verification of ECL Circuits Including Voltage Regulators.	ISCAS	1993	DBLP BibTeX RDF
23	Monjurul Haque, Salim Chowdhury	Analysis and Reliable Design of ECL Circuits with Distributed RLC Interconnections.	DAC	1993	DBLP DOI BibTeX RDF
23	John Andrews	IEEE 1149.1 Applied to Mixed TTL-ECL and Differential Logic.	ITC	1992	DBLP DOI BibTeX RDF
23	Sankaran M. Menon, Anura P. Jayasumana, Yashwant K. Malaiya	On Bridging Faults in ECL Circuits.	VLSI Design	1992	DBLP DOI BibTeX RDF
23	Bob Foster, Curtis Alexander, Allen Roberts, David Roberts	An ECL RISC multiprocessor.	Compcon	1991	DBLP DOI BibTeX RDF
23	Sankaran M. Menon, Anura P. Jayasumana, Yashwant K. Malaiya	Gate level representation of ECL circuits for fault modeling.	Great Lakes Symposium on VLSI	1991	DBLP DOI BibTeX RDF
23	Jiann-Shiun Yuan, Juin J. Liou, David M. Wu	Testing the impact of process defects on ECL power-delay performance.	VTS	1991	DBLP DOI BibTeX RDF
23	Kyle G. Welch, James A. Monzel, Donald S. Kent, Donald W. Joseph	Delay testing and failure analysis of ECL logic with embedded memories.	VTS	1991	DBLP DOI BibTeX RDF
23	Van Morgan, David Gregory	An ECL Logic Synthesis System.	DAC	1991	DBLP DOI BibTeX RDF
23	Emil W. Brown, Anant Agrawal, Trevor Creary, Michael F. Klein, Dave Murata, Joseph Petolino	Implementing Sparc in ECL.	IEEE Micro	1990	DBLP DOI BibTeX RDF
23	Ashis Khan	CMOS and ECL implementation of MIPS RISC architecture.	Microprocess. Microsystems	1990	DBLP DOI BibTeX RDF
23	David Roberts, Tim Layman, George Taylor	An ECL RISC microprocessor designed for two level cache.	Compcon	1990	DBLP DOI BibTeX RDF
23	G. Taylor, G. Sanguinetti, R. Lane	An approach to 150 K gate low power ECL cell based integrated circuits.	ICCD	1990	DBLP DOI BibTeX RDF
23	Donald A. Lewine, James Guyer, Bill Baxter, Chris Moriondo	An ECL implementation of the Motorola 88000.	COMPCON	1989	DBLP DOI BibTeX RDF