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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 3198 occurrences of 1135 keywords
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Results
Found 7385 publication records. Showing 7385 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
66 | Sudip K. Nag, Rob A. Rutenbar |
Performance-driven simultaneous place and route for island-style FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 332-338, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Xilinx 4000-series FPGAs, island-style FPGAs, performance-driven simultaneous placement/routing, place and route tools, FPGAs, field programmable gate arrays, logic CAD, network routing, circuit layout CAD, industrial designs, circuit layout |
61 | Jason Cong, Songjie Xu |
Performance-driven technology mapping for heterogeneous FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(11), pp. 1268-1281, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
57 | Bruce A. Draper, Walid A. Najjar, A. P. Wim Böhm, Jeffrey Hammes, Robert Rinker, Charlie Ross, Monica Chawathe, José Bins |
Compiling and Optimizing Image Processing Algorithms for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAMP ![In: Fifth International Workshop on Computer Architectures for Machine Perception (CAMP 2000), September 11-13, 2000, Padova, Italy, pp. 222-231, 2000, IEEE Computer Society, 0-7695-0740-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
SA-C, language features, SA-C algorithms, performance numbers, image processing routines, Annapolis Microsystems WildForce board, Xilinx 4036XL FPGAs, FPGAs, VHDL, optimizing compiler, high-level language, data flow graphs, data flow graphs, image processing algorithms |
53 | Vinay Verma, Shantanu Dutt, Vishal Suthar |
Efficient on-line testing of FPGAs with provable diagnosabilities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 498-503, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
built-in self-tester (BISTer), roving tester (ROTE), FPGAs, functional testing, on-line testing, diagnosability |
52 | Bernard Girau |
Digital Hardware Implementation of 2D Compatible Neural Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IJCNN (3) ![In: Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, IJCNN 2000, Neural Computing: New Challenges and Perspectives for the New Millennium, Como, Italy, July 24-27, 2000, Volume 3, pp. 506-514, 2000, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
49 | Toshinori Sueyoshi |
Basic Knowledge to Understand FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Principles and Structures of FPGAs ![In: Principles and Structures of FPGAs., pp. 1-22, 2018, Springer, 978-981-13-0823-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
49 | Jeffrey B. Goeders, Graham M. Holland, Lesley Shannon, Steven J. E. Wilton |
Systems-on-Chip on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGAs for Software Programmers ![In: FPGAs for Software Programmers, pp. 261-283, 2016, Springer, 978-3-319-26406-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
49 | Hugo A. Andrade, Stephan Ahrends, Simon Hogg |
Making FPGAs Accessible with LabVIEW. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGAs for Software Programmers ![In: FPGAs for Software Programmers, pp. 63-79, 2016, Springer, 978-3-319-26406-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
49 | Frank Hannig |
A Quick Tour of High-Level Synthesis Solutions for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGAs for Software Programmers ![In: FPGAs for Software Programmers, pp. 49-59, 2016, Springer, 978-3-319-26406-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
48 | Yajun Ran, Malgorzata Marek-Sadowska |
Crosstalk noise in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 944-949, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
FPGAs, noise, crosstalk, switch box |
47 | Chandra Mulpuri, Scott Hauck |
Runtime and quality tradeoffs in FPGA placement and routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2001, Monterey, CA, USA, February 11-13, 2001, pp. 29-36, 2001, ACM, 1-58113-341-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
fast CAD for FPGAs, FPGAs, routing, computer-aided design, placement |
44 | Jason Cong, Hui Huang 0001, Xin Yuan 0005 |
Technology mapping and architecture evalution for k/m-macrocell-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 10(1), pp. 3-23, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
FPGA, technology mapping, CPLD, PLD |
44 | Andrés David García García, Luis Fernando González Pérez, Reynaldo Félix Acuña |
Power Consumption Management on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CONIELECOMP ![In: 15th International Conference on Electronics, Communications, and Computers (CONIELECOMP 2005), 28 February 2005 - 2 March 2005, Puebla, Mexico, pp. 240-245, 2005, IEEE Computer Society, 0-7695-2283-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Genetic Algorithms, Field Programmable Gate Array, Power Consumption, Partial Reconfiguration, Circuit Design |
44 | Young-Su Kwon, Bong-Il Park, Chong-Min Kyung |
SCATOMi: Scheduling Driven Circuit Partitioning Algorithm for Multiple FPGAs using Time-multiplexed, Off-chip, Multicasting Interconnection Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 419-425, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
44 | Jason Cong, Hui Huang 0001, Xin Yuan 0005 |
Technology mapping for k/m-macrocell based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2000, Monterey, CA, USA, February 10-11, 2000, pp. 51-59, 2000, ACM, 1-58113-193-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
43 | Katarzyna Leijten-Nowak, Jef L. van Meerbergen |
An FPGA architecture with enhanced datapath functionality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 195-204, 2003, ACM, 1-58113-651-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
adder inverting property, application-domain tuning, logic block architectures, FPGAs, DSP, symmetry |
42 | Steve Trimberger |
Security in SRAM FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 24(6), pp. 581, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
security, FPGAs, reverse-engineering, encryption, bitstream |
42 | Priya Sundararajan, Aman Gayasen, Narayanan Vijaykrishnan, Tim Tuan |
Thermal characterization and optimization in platform FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 443-447, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Virtex4, platform FPGAs, thermal floorplan, placement, temperature, thermal |
40 | Christophe Bobda, Nils Steenbock |
A Rapid Prototyping Environment for Distributed Reconfigurable Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 13th IEEE International Workshop on Rapid System Prototyping (RSP 2002), 1-3 July 2002, Darmstadt, Germany, pp. 153-158, 2002, IEEE Computer Society, 0-7695-1703-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
40 | Bernard Girau |
Building a 2D-Compatible Multilayer Neural Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IJCNN (2) ![In: Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks, IJCNN 2000, Neural Computing: New Challenges and Perspectives for the New Millennium, Como, Italy, July 24-27, 2000, Volume 2, pp. 59-64, 2000, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
39 | Masahiro Iida |
What Is an FPGA? ![Search on Bibsonomy](Pics/bibsonomy.png) |
Principles and Structures of FPGAs ![In: Principles and Structures of FPGAs., pp. 23-45, 2018, Springer, 978-981-13-0823-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
39 | Masahiro Iida |
Design Methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Principles and Structures of FPGAs ![In: Principles and Structures of FPGAs., pp. 117-135, 2018, Springer, 978-981-13-0823-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
39 | Tomonori Izumi, Yukio Mitsuyama |
Design Flow and Design Tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Principles and Structures of FPGAs ![In: Principles and Structures of FPGAs., pp. 87-115, 2018, Springer, 978-981-13-0823-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
39 | Kentaro Sano, Hiroki Nakahara |
Hardware Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Principles and Structures of FPGAs ![In: Principles and Structures of FPGAs., pp. 137-177, 2018, Springer, 978-981-13-0823-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
39 | Tsutomu Maruyama, Yoshiki Yamaguchi, Yasunori Osana |
Programmable Logic Devices (PLDs) in Practical Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Principles and Structures of FPGAs ![In: Principles and Structures of FPGAs., pp. 179-205, 2018, Springer, 978-981-13-0823-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
39 | Motoki Amagasaki, Yuichiro Shibata |
FPGA Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Principles and Structures of FPGAs ![In: Principles and Structures of FPGAs., pp. 47-86, 2018, Springer, 978-981-13-0823-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
39 | Masato Motomura, Masanori Hariyama, Minoru Watanabe |
Advanced Devices and Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Principles and Structures of FPGAs ![In: Principles and Structures of FPGAs., pp. 207-231, 2018, Springer, 978-981-13-0823-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
39 | Moritz Schmid, Christian Schmitt 0003, Frank Hannig, Gorker Alp Malazgirt, Nehir Sönmez, Arda Yurdakul, Adrián Cristal |
Big Data and HPC Acceleration with Vivado HLS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGAs for Software Programmers ![In: FPGAs for Software Programmers, pp. 115-136, 2016, Springer, 978-3-319-26406-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
39 | Hayden Kwok-Hay So, Cheng Liu |
FPGA Overlays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGAs for Software Programmers ![In: FPGAs for Software Programmers, pp. 285-305, 2016, Springer, 978-3-319-26406-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
39 | Deshanand P. Singh, Peter Yiannacouras |
OpenCL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGAs for Software Programmers ![In: FPGAs for Software Programmers, pp. 97-114, 2016, Springer, 978-3-319-26406-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
39 | Andreas Agne, Marco Platzner, Christian Plessl, Markus Happe, Enno Lübbers |
ReconOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGAs for Software Programmers ![In: FPGAs for Software Programmers, pp. 227-244, 2016, Springer, 978-3-319-26406-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
39 | Dirk Koch, Daniel Ziener, Frank Hannig |
FPGA Versus Software Programming: Why, When, and How? ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGAs for Software Programmers ![In: FPGAs for Software Programmers, pp. 1-21, 2016, Springer, 978-3-319-26406-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
39 | João M. P. Cardoso, Markus Weinhardt |
High-Level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGAs for Software Programmers ![In: FPGAs for Software Programmers, pp. 23-47, 2016, Springer, 978-3-319-26406-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
39 | Walid A. Najjar, Jason R. Villarreal, Robert J. Halstead |
ROCCC 2.0. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGAs for Software Programmers ![In: FPGAs for Software Programmers, pp. 191-204, 2016, Springer, 978-3-319-26406-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
39 | Moritz Schmid, Oliver Reiche, Frank Hannig, Jürgen Teich |
HIPAcc. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGAs for Software Programmers ![In: FPGAs for Software Programmers, pp. 205-223, 2016, Springer, 978-3-319-26406-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
39 | Andrew Canis, Jongsok Choi, Blair Fort, Bain Syrowik, Ruolong Lian, Yu Ting Chen, Hsuan Hsiao, Jeffrey B. Goeders, Stephen Dean Brown, Jason Helge Anderson |
LegUp High-Level Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGAs for Software Programmers ![In: FPGAs for Software Programmers, pp. 175-190, 2016, Springer, 978-3-319-26406-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
39 | Jason Cong, Muhuan Huang, Peichen Pan, Yuxin Wang, Peng Zhang 0007 |
Source-to-Source Optimization for HLS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGAs for Software Programmers ![In: FPGAs for Software Programmers, pp. 137-163, 2016, Springer, 978-3-319-26406-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
39 | Kermin Fleming, Michael Adler |
The LEAP FPGA Operating System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGAs for Software Programmers ![In: FPGAs for Software Programmers, pp. 245-258, 2016, Springer, 978-3-319-26406-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
39 | Oriol Arcas-Abella, Nehir Sönmez |
Bluespec SystemVerilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGAs for Software Programmers ![In: FPGAs for Software Programmers, pp. 165-172, 2016, Springer, 978-3-319-26406-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
39 | Tobias Becker, Oskar Mencer, Georgi Gaydadjiev |
Spatial Programming with OpenSPL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGAs for Software Programmers ![In: FPGAs for Software Programmers, pp. 81-95, 2016, Springer, 978-3-319-26406-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
38 | David Sheldon, Frank Vahid |
Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 155-160, 2008, ACM, 978-1-60558-470-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
BRAM, high-throughput design, pattern counting, redesigning circuit, FPGA, design patterns, stream, memory, ASIC |
38 | Luca Sterpone, Massimo Violante |
A new decompression system for the configuration process of SRAM-based FPGAS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 241-246, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
configuration mechanisms, compression algorithm, SRAM-based FPGA |
38 | Owen Callanan, David Gregg, Andy Nisbet, Mike Peardon |
High Performance Scientific Computing Using FPGAs with IEEE Floating Point and Logarithmic Arithmetic for Lattice QCD. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-6, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
38 | Stefan Mohl |
Innovative technologies I - Using FPGAs in supercomputers: breaking with reconfigurable computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, November 11-17, 2006, Tampa, FL, USA, pp. 251, 2006, ACM Press, 0-7695-2700-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
38 | Young-Su Kwon, C.-M. Kyung |
ATOMi: An Algorithm for Circuit Partitioning Into Multiple FPGAs Using Time-Multiplexed, Off-Chip, Multicasting Interconnection Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(7), pp. 861-864, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | André DeHon, Brad L. Hutchings, Daryl Rudusky, James Hwang, Nikhil, Salil Raje, Adrian Stoica |
What is the right model for programming and using modern FPGAs? ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 119, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
38 | Adam Donlin, Patrick Lysaght, Brandon Blodget, Gerd Troeger |
A Virtual File System for Dynamically Reconfigurable FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 14th International Conference , FPL 2004, Leuven, Belgium, August 30-September 1, 2004, Proceedings, pp. 1127-1129, 2004, Springer, 3-540-22989-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
37 | Mark I. Parsons, Francis W. Wray |
Programming FPGAs - Programming FPGAs: challenges and successes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, November 11-17, 2006, Tampa, FL, USA, pp. 25, 2006, ACM Press, 0-7695-2700-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
37 | John Marty Emmert, Akash Randhar, Dinesh Bhatia |
Fast Floorplanning for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm, 8th International Workshop, FPL'98, Tallinn, Estonia, August 31 - September 3, 1998, Proceedings, pp. 129-138, 1998, Springer, 3-540-64948-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
37 | Tien-Toan Do, Holger Kropp, Carsten Reuter, Peter Pirsch |
A Flexible Implementation of High-Performance FIR Filters on Xilinx FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm, 8th International Workshop, FPL'98, Tallinn, Estonia, August 31 - September 3, 1998, Proceedings, pp. 441-445, 1998, Springer, 3-540-64948-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
36 | Jason Lee, Lesley Shannon |
Predicting the performance of application-specific NoCs implemented on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 23-32, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
performance, FPGAs, topologies, heterogeneous, NoCs, homogeneous, application-specific, routability |
36 | Qiang Wang, Subodh Gupta, Jason Helge Anderson |
Clock power reduction for virtex-5 FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 13-22, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
optimization, field-programmable gate arrays, fpgas, low-power design, power, clocking |
36 | Quang Dinh, Deming Chen, Martin D. F. Wong |
A routing approach to reduce glitches in low power FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009, pp. 99-106, 2009, ACM, 978-1-60558-449-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
glitch reduction, path balancing, fpgas, routing, low power |
36 | Gang Zhou, Harald Michalik, László Hinsenkamp |
Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings, pp. 193-203, 2009, Springer, 978-3-642-00640-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
AES-GCM, pipelined Karatsuba multiplier, FPGAs, finite field arithmetic |
36 | Stephen Neuendorffer, Kees A. Vissers |
Streaming Systems in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 8th International Workshop, SAMOS 2008, Samos, Greece, July 21-24, 2008. Proceedings, pp. 147-156, 2008, Springer, 978-3-540-70549-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
digital convergence, FPGAs, dataflow |
36 | David Zaretsky, Gaurav Mittal, Xiaoyong Tang, Prithviraj Banerjee |
Evaluation of scheduling and allocation algorithms while mapping assembly code onto FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, Boston, MA, USA, April 26-28, 2004, pp. 397-400, 2004, ACM, 1-58113-853-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
scheduling, optimizations, FPGAs, compilers, binary translation, chaining, hardware synthesis |
36 | Pedro C. Diniz, Joonseok Park |
Data Search and Reorganization Using FPGAs: Application to Spatial Pointer-based Data Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 8-11 April 2003, Napa, CA, USA, Proceedings, pp. 207-217, 2003, IEEE Computer Society, 0-7695-1979-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Custom Computing, Data search and Data Reorganization Engines, Hardware support for Pointer Operations, Field-Programmable- Gate-Arrays (FPGAs) |
36 | Marco Platzner, Bernhard Rinner, Reinhold Weiss |
A distributed computer architecture for qualitative simulation based on a multi-DSP and FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 3rd Euromicro Workshop on Parallel and Distributed Processing (PDP '95), January 25-27, 1995, San Remo, Italy, pp. 311-318, 1995, IEEE Computer Society, 0-8186-7031-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
distributed computer architecture, multi-DSP, application-specific computer architecture, constraint-check-function, performance, FPGAs, parallel architectures, computer architecture, digital simulation, hardware design, special purpose computers, design strategies, qualitative simulation |
36 | Jae-Tack Yoo, Erik Brunvand, Kent F. Smith |
Automatic rapid prototyping of semi-custom VLSI circuits using Actel FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 148-151, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
automatic rapid prototyping, semicustom VLSI circuits, Actel FPGAs, cell-matrix based environment, synchronous pipelined version, asynchronous pipelined version, field programmable gate arrays, field programmable gate arrays, VLSI, logic CAD, integrated circuit design, CMOS logic circuits, circuit CAD, array multiplier, CMOS IC |
36 | Stanley Habib, Quan Xu |
Technology mapping algorithms for sequential circuits using look-up table based FPGAS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Great Lakes Symposium on VLSI ![In: 5th Great Lakes Symposium on VLSI (GLS-VLSI '95), March 16-18, 1995, The State University of New York at Buffalo, USA, pp. 164-167, 1995, IEEE Computer Society, 0-8186-7035-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
technology mapping algorithms, FPGAS, routing results, adjacent combinational parts, field programmable gate arrays, delays, sequential circuits, sequential circuits, logic CAD, network routing, flip-flops, flip-flops, circuit layout CAD, table lookup, time delay, look-up table |
34 | Balasubramanian Sethuraman |
Novel Methodologies for Performance & Power Efficient Reconfigurable Networks-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-2, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
34 | Christophe Bobda, Nils Steenbock |
Singular Value Decomposition on Distributed Reconfigurable Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 12th IEEE International Workshop on Rapid System Prototyping (RSP 2001), 25-27 June 2001, Monterey, CA, USA, pp. 38-43, 2001, IEEE Computer Society, 0-7695-1206-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
34 | Xuan Zhang, Cesar Ortega-Sanchez, Iain Murray 0002 |
Reconfigurable PDA for the Visually Impaired Using FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 3-5 December 2008, Cancun, Mexico, Proceedings, pp. 1-6, 2008, IEEE Computer Society, 978-0-7695-3474-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FPGAs, embedded systems, Assistive technology, system on a chip |
34 | Bin Zhou, David Hwang |
Implementations and Optimizations of Pipeline FFTs on Xilinx FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 3-5 December 2008, Cancun, Mexico, Proceedings, pp. 325-330, 2008, IEEE Computer Society, 978-0-7695-3474-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Pipeline FFTs, FPGAs |
34 | Xiaofang Wang, Swetha Thota |
Design and Implementation of a Resource-Efficient Communication Architecture for Multiprocessors on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ReConFig ![In: ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 3-5 December 2008, Cancun, Mexico, Proceedings, pp. 25-30, 2008, IEEE Computer Society, 978-0-7695-3474-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FPGAs, multiprocessor, network-on-chip |
33 | Chen Chen 0018, Roozbeh Parsa, Nishant Patil, Soogine Chong, Kerem Akarvardar, J. Provine, David Lewis, Jeff Watt, Roger T. Howe, H.-S. Philip Wong, Subhasish Mitra |
Efficient FPGAs using nanoelectromechanical relays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 273-282, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
CMOS-NEM FPGA, nanoelectromechanical relay |
33 | Laurent Sauvage, Sylvain Guilley, Yves Mathieu |
Electromagnetic Radiations of FPGAs: High Spatial Resolution Cartography and Attack on a Cryptographic Module. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Reconfigurable Technol. Syst. ![In: ACM Trans. Reconfigurable Technol. Syst. 2(1), pp. 4:1-4:24, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
EMA, security, FPGA, DPA, SCA, cartography |
33 | Ping-Hung Yuh, Chia-Lin Yang, Chi-Feng Li, Chung-Hsiang Lin |
Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 14(4), pp. 52:1-52:26, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
scheduling, placement, Reconfigurable computing, leakage, partially dynamical reconfiguration |
33 | Michael Brown, Cyrus Bazeghi, Matthew R. Guthaus, Jose Renau |
Measuring and modeling variabilityusing low-cost FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 286, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
variability |
33 | Victor Dumitriu, Dennis Marcantonio, Lev Kirischian |
Run-Time Component Relocation in Partially-Reconfigurable FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSE (2) ![In: Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, CSE 2009, Vancouver, BC, Canada, August 29-31, 2009, pp. 909-914, 2009, IEEE Computer Society, 978-1-4244-5334-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
33 | Michael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott Hemmert |
Architectural Modifications to Enhance the Floating-Point Performance of FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(2), pp. 177-187, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
33 | Nan Guan, Qingxu Deng, Zonghua Gu 0001, Wenyao Xu, Ge Yu 0001 |
Schedulability analysis of preemptive and nonpreemptive EDF on partial runtime-reconfigurable FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(4), pp. 56:1-56:43, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
reconfigurable devices, FPGA, Real-time scheduling |
33 | Prasanth Mangalagiri, Sungmin Bae, Krishnan Ramakrishnan, Yuan Xie 0001, Vijaykrishnan Narayanan |
Thermal-aware reliability analysis for platform FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 722-727, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
33 | Luca Sterpone, Matteo Sonza Reorda, Massimo Violante, Fernanda Lima Kastensmidt, Luigi Carro |
Evaluating Different Solutions to Design Fault Tolerant Systems with SRAM-based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 23(1), pp. 47-54, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
reliability, fault tolerant systems, SEU, SRAM-based FPGA |
33 | Reza M. Rad, Mohammad Tehranipoor |
Evaluating area and performance of hybrid FPGAs with nanoscale clusters and CMOS routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 3(3), pp. 15, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
performance, FPGA, reliability, CMOS, Nanotechnology |
33 | Shilpa Bhoj, Dinesh Bhatia |
Thermal Modeling and Temperature Driven Placement for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1053-1056, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
33 | Luca Sterpone, Massimo Violante |
A New Reliability-Oriented Place and Route Algorithm for SRAM-Based FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 55(6), pp. 732-744, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
transient fault injection, FPGA, reliability, place and route |
33 | Lei Cheng 0001, Martin D. F. Wong |
Floorplan Design for Multimillion Gate FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(12), pp. 2795-2805, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Suresh Srinivasan, Narayanan Vijaykrishnan |
Variation Aware Placement for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 422-423, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | François-Xavier Standaert, François Macé, Eric Peeters, Jean-Jacques Quisquater |
Updates on the Security of FPGAs Against Power Analysis Attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures and Applications, Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006, Revised Selected Papers, pp. 335-346, 2006, Springer. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Suhap Sahin, Yasar Becerikli, Suleyman Yazici |
Neural Network Implementation in Hardware Using FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICONIP (3) ![In: Neural Information Processing, 13th International Conference, ICONIP 2006, Hong Kong, China, October 3-6, 2006, Proceedings, Part III, pp. 1105-1112, 2006, Springer, 3-540-46484-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
33 | Rajarshi Mukherjee, Seda Ogrenci Memik |
Evaluation of dual VDD fabrics for low power FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 1240-1243, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
33 | K. Scott Hemmert, Keith D. Underwood |
An Analysis of the Double-Precision Floating-Point FFT on FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 17-20 April 2005, Napa, CA, USA, Proceedings, pp. 171-180, 2005, IEEE Computer Society, 0-7695-2445-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
IEEE floating point, FPGA, FFT, Fast Fourier Transform, reconfigurable computing |
33 | Thomas J. Wollinger, Jorge Guajardo, Christof Paar |
Security on FPGAs: State-of-the-art implementations and attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 3(3), pp. 534-574, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
cryptographic applications, security, FPGA, Cryptography, reverse engineering, attacks, reconfigurable hardware |
33 | Paul Kohlbrenner, Kris Gaj |
An embedded true random number generator for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 71-78, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
TRNG, FPGA, random numbers, RNG, cryptographic |
33 | Mike Hutton |
Architecture and CAD for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2004, Pernambuco, Brazil, September 7-11, 2004, pp. 3, 2004, ACM. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
33 | Seonil Choi, Ronald Scrofano, Viktor K. Prasanna, Ju-wook Jang |
Energy-efficient signal processing using FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 225-234, 2003, ACM, 1-58113-651-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
energy efficient design techniques, matrix multiplicaiton, FPGA, FFT, performance estimation |
33 | Adrian J. Hilton, Gemma Townson, Jon G. Hall |
FPGAs in critical hardware/software systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 244, 2003, ACM, 1-58113-651-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
33 | Thomas J. Wollinger, Christof Paar |
How Secure Are FPGAs in Cryptographic Applications? ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 91-100, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
security, FPGA, cryptography, attacks, reconfigurable hardware |
33 | Herman Schmit |
Extra-dimensional Island-Style FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field Programmable Logic and Application, 13th International Conference, FPL 2003, Lisbon, Portugal, September 1-3, 2003, Proceedings, pp. 406-415, 2003, Springer, 3-540-40822-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
33 | Charles E. Stroud, Keshia N. Leach, Thomas A. Slaughter |
BIST for Xilinx 4000 and Spartan Series FPGAs: A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 1258-1267, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
33 | Shantanu Dutt, Vinay Verma, Hasan Arslan |
A search-based bump-and-refit approach to incremental routing for ECO applications in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 7(4), pp. 664-693, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Bump-and-refit (B&R) paradigm, ECO (engineering change order), bumping cost, incremental routing, switchbox, field programmable gate arrays, dynamic programming, global routing, detailed routing |
33 | Channakeshav, Kuan Zhou, Jong-Ru Guo, Chao You, Bryan S. Goda, Russell P. Kraft, John F. McDonald 0001 |
Fast SiGe HBT BiCMOS FPGAs with New Architecture and Power Saving Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 414-423, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
33 | Bryan S. Goda, Russell P. Kraft, Steven R. Carlough, Thomas W. Krawczyk Jr., John F. McDonald 0001 |
Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001, Proceedings, pp. 59-69, 2001, Springer, 3-540-42499-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
33 | John Marty Emmert, Jason A. Cheatham |
On-Line Incremental Routing for Interconnect Fault Tolerance in FPGAs Minus the Router . ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 24-26 October 2001, San Francisco, CA, USA, Proceedings, pp. 149-, 2001, IEEE Computer Society, 0-7695-1203-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
33 | Chi-Feng Wu, Cheng-Wen Wu |
Testing Interconnects of Dynamic Reconfigurable FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 1999 Conference on Asia South Pacific Design Automation, Wanchai, Hong Kong, China, January 18-21, 1999, pp. 279-282, 1999, IEEE Computer Society, 0-7803-5012-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
33 | Paul S. Graham, Brent E. Nelson |
Frequency-Domain Sonar Processing in FPGAs and DSPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 15-17 April 1998, Napa Valley, CA, USA, pp. 306-307, 1998, IEEE Computer Society, 0-8186-8900-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
33 | Jason Cong, Songjie Xu |
Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 35th Conference on Design Automation, Moscone center, San Francico, California, USA, June 15-19, 1998., pp. 704-707, 1998, ACM Press, 0-89791-964-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
technology mapping, programmable logic devices, PLA-style logic blocks |
33 | Maya B. Gokhale, D. Gomersall |
High level compilation for fine grained FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 5th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97), 16-18 April 1997, Napa Valley, CA, USA, pp. 165-174, 1997, IEEE Computer Society, 0-8186-8159-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
32 | John Woodfill, Brian Von Herzen |
Real-time stereo vision on the PARTS reconfigurable computer. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 5th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '97), 16-18 April 1997, Napa Valley, CA, USA, pp. 201-210, 1997, IEEE Computer Society, 0-8186-8159-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
powerful scalable reconfigurable computer, PARTS engine, real-time stereo vision, Xilinx 4025 FPGAs, partial torus, concurrent SRAM access, standard PCI card, stereo vision algorithm, stereo disparity computation, RISC-equivalent operations, 1 Mbyte, images, SRAMs, stereo image processing, personal computer, workstation, memory access |
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