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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 731 occurrences of 466 keywords
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Results
Found 747 publication records. Showing 746 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
129 | Ayose Falcón, Alex Ramírez, Mateo Valero |
A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), 14-18 February 2004, Madrid, Spain, pp. 244-253, 2004, IEEE Computer Society, 0-7695-2053-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
121 | Stephen Roderick Hines, Yuval Peress, Peter Gavin, David B. Whalley, Gary S. Tyson |
Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE). ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems, LCTES 2009, Dublin, Ireland, June 19-20, 2009, pp. 119-128, 2009, ACM, 978-1-60558-356-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
l0/filter cache, lookahead instruction fetch engine (life), tagless hit instruction cache (th-ic) |
120 | Pierre Michaud, André Seznec, Stéphan Jourdan |
Exploring Instruction-Fetch Bandwidth Requirement in Wide-Issue Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, Newport Beach, California, USA, October 12-16, 1999, pp. 2-10, 1999, IEEE Computer Society, 0-7695-0425-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
instruction-level parallelism, branch prediction, superscalar processors, instruction fetch |
103 | Daniel H. Friendly, Sanjay J. Patel, Yale N. Patt |
Alternative Fetch and Issue Policies for the Trace Cache Fetch Mechanism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the Thirtieth Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997, pp. 24-33, 1997, ACM/IEEE Computer Society, 0-8186-7977-8. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
high bandwidth fetch mechanisms, wide issue machines, inactive issue, speculative execution, trace cache, partial matching |
93 | Minxuan Zhang, Caixia Sun |
Enhancing DCache Warn Fetch Policy for SMT Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPA ![In: Parallel and Distributed Processing and Applications, Third International Symposium, ISPA 2005, Nanjing, China, November 2-5, 2005, Proceedings, pp. 216-223, 2005, Springer, 3-540-29769-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
L2 cache miss, I-fetch Policy, Fetch Priority, Resource Allocation, SMT |
93 | Thomas M. Conte, Sanjeev Banerjia, Sergei Y. Larin, Kishore N. Menezes, Sumedh W. Sathaye |
Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996, pp. 201-211, 1996, ACM/IEEE Computer Society, 0-8186-7641-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
TINKER experimental testbed, compressed encodings, compressed instruction encoding, i-fetch hardware, instruction fetch mechanisms, instruction words, multiple instruction issue, silo cache, parallel architectures, trace-driven simulations, instruction cache, VLIW architectures |
83 | Oliverio J. Santana, Alex Ramírez, Josep Lluís Larriba-Pey, Mateo Valero |
A low-complexity fetch architecture for high-performance superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 1(2), pp. 220-245, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
fetch architecture, instruction stream, high performance, Branch prediction, low complexity |
83 | Alex Ramírez, Josep Lluís Larriba-Pey, Carlos Navarro, Xavi Serrano, Mateo Valero, Josep Torrellas |
Optimization of Instruction Fetch for Decision Support Workloads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: Proceedings of the International Conference on Parallel Processing 1999, ICPP 1999, Wakamatsu, Japan, September 21-24, 1999, pp. 238-245, 1999, IEEE Computer Society, 0-7695-0350-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
High performance fetch, databases, profiling, compiler optimization, trace cache |
82 | Michele Co, Dee A. B. Weikle, Kevin Skadron |
Evaluating trace cache energy efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 3(4), pp. 450-476, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
fetch engine energy efficiency, Trace cache |
82 | Alex Ramírez, Oliverio J. Santana, Josep Lluís Larriba-Pey, Mateo Valero |
Fetching instruction streams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 35th Annual International Symposium on Microarchitecture, Istanbul, Turkey, November 18-22, 2002, pp. 371-382, 2002, ACM/IEEE Computer Society, 0-7695-1859-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Systems Application Architecture |
74 | Stijn Eyerman, Lieven Eeckhout |
Memory-level parallelism aware fetch policies for simultaneous multithreading processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 6(1), pp. 3:1-3:33, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Fetch Policy, Simultaneous Multithreading (SMT), Memory-Level Parallelism (MLP) |
74 | Daniel Chaver, Miguel A. Rojas, Luis Piñuel, Manuel Prieto 0001, Francisco Tirado, Michael C. Huang 0001 |
Energy-aware fetch mechanism: trace cache and BTB customization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005, pp. 42-47, 2005, ACM, 1-59593-137-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
adaptive, profiling, instruction fetch |
74 | Caixia Sun, Hong-Wei Tang, Minxuan Zhang |
A Fetch Policy Maximizing Throughput and Fairness for Two-Context SMT Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPT ![In: Advanced Parallel Processing Technologies, 6th International Workshop, APPT 2005, Hong Kong, China, October 27-28, 2005, Proceedings, pp. 13-22, 2005, Springer, 3-540-29639-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
74 | Osman S. Unsal, Israel Koren, C. Mani Krishna 0001, Csaba Andras Moritz |
Cool-Fetch: A Compiler-Enabled IPC Estimation Based Framework for Energy Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Interaction between Compilers and Computer Architectures ![In: 8th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-8 2004), 15 February 2004, Madrid, Spain, pp. 43-52, 2004, IEEE Computer Society, 0-7695-2061-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
74 | Paramjit S. Oberoi, Gurindar S. Sohi |
Out-of-Order Instruction Fetch Using Multiple Sequencers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPP ![In: 31st International Conference on Parallel Processing (ICPP 2002), 20-23 August 2002, Vancouver, BC, Canada, pp. 14-26, 2002, IEEE Computer Society, 0-7695-1677-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
74 | P.-H. Chang, Wen-mei W. Hwu |
Forward semantic: a compiler-assisted instruction fetch method for heavily pipelined processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 22nd Annual Workshop and Symposium on Microprogramming and Microarchitecture, 1989, Dublin, Ireland, August 14-16, 1989, pp. 188-198, 1989, ACM/IEEE, 0-89791-324-8. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
73 | Oliverio J. Santana, Alex Ramírez, Mateo Valero |
Enlarging Instruction Streams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(10), pp. 1342-1357, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Superscalar processor design, branch prediction, code optimization, instruction fetch, access latency |
73 | Alex Ramírez, Josep Lluís Larriba-Pey, Mateo Valero |
Software Trace Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 54(1), pp. 22-35, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
compiler optimizations, branch prediction, Pipeline processors, trace cache, instruction fetch |
66 | Aditya Dua, Nicholas Bambos, Jatinder Pal Singh |
Performance tradeoffs in mobile computing: to fetch or not to fetch? ![Search on Bibsonomy](Pics/bibsonomy.png) |
MOBIWAC ![In: Proceedings of the Fifth ACM International Workshop on Mobility Management & Wireless Access, MOBIWAC 2007, Chania, Crete Island, Greece, October 22, 2007, pp. 99-106, 2007, ACM, 978-1-59593-809-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
mobile computing, dynamic programming, buffer management, tandem queues |
65 | Robert Yung |
Design Decisions Influencing the UltraSPARC's Instruction Fetch Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996, pp. 178-190, 1996, ACM/IEEE Computer Society, 0-8186-7641-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
UltraSPARC, fast cycle time, in-cache prediction, instruction fetch architecture, instruction fetch unit, lower cycle-per-instruction, predictive set-associative cache, prefetch and dispatch unit, trade-off decisions, computer architecture, microprocessor |
65 | Soner Önder, Jun Xu, Rajiv Gupta 0001 |
Caching and Predicting Branch Sequences for Improved Fetch Effectiveness. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques, Newport Beach, California, USA, October 12-16, 1999, pp. 294-302, 1999, IEEE Computer Society, 0-7695-0425-6. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
branch sequence prediction, sequence table, fetch bandwidth, speculative execution |
65 | Stephen Roderick Hines, Gary S. Tyson, David B. Whalley |
Addressing instruction fetch bottlenecks by using an instruction register file. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), San Diego, California, USA, June 13-15, 2007, pp. 165-174, 2007, ACM, 978-1-59593-632-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
L0/filter cache, instruction packing, instruction register file |
65 | Caixia Sun, Hong-Wei Tang, Minxuan Zhang |
Controlling Performance of a Time-Criticial Thread in SMT Processors by Instruction Fetch Policy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDCAT ![In: Seventh International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2006), 4-7 December 2006, Taipei, Taiwan, pp. 217-222, 2006, IEEE Computer Society, 0-7695-2736-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
65 | Oliverio J. Santana, Alex Ramírez, Mateo Valero |
Reducing Fetch Architecture Complexity Using Procedure Inlining. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Interaction between Compilers and Computer Architectures ![In: 8th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-8 2004), 15 February 2004, Madrid, Spain, pp. 97-106, 2004, IEEE Computer Society, 0-7695-2061-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
65 | Juan C. Moure, Dolores Rexachs, Emilio Luque |
Optimizing a Decoupled Front-End Architecture: The Indexed Fetch Target Buffer (iFTB). ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2003. Parallel Processing, 9th International Euro-Par Conference, Klagenfurt, Austria, August 26-29, 2003. Proceedings, pp. 566-575, 2003, Springer, 3-540-40788-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
65 | Alper Buyuktosunoglu, Tejas Karkhanis, David H. Albonesi, Pradip Bose |
Energy Efficient Co-Adaptive Instruction Fetch and Issue. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003, San Diego, California, USA, pp. 147-156, 2003, IEEE Computer Society, 0-7695-1945-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
65 | Gurindar S. Sohi, James E. Smith 0001, James R. Goodman |
Restricted Fetch&Phi operations for parallel processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICS ![In: Proceedings of the 3rd international conference on Supercomputing, ICS 1989, Heraklion, Crete, Greece, June 5-9, 1989, pp. 410-416, 1989, ACM, 0-89791-309-4. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
64 | Han-Xin Sun, Kun-Peng Yang, Yulai Zhao 0003, Dong Tong 0001, Xu Cheng 0001 |
CASA: A New IFU Architecture for Power-Efficient Instruction Cache and TLB Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Comput. Sci. Technol. ![In: J. Comput. Sci. Technol. 23(1), pp. 141-153, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
instruction TLB, instruction fetch unit, power-efficient design, computer architecture, dynamic voltage scaling, instruction cache |
64 | Glenn Reinman, Brad Calder, Todd M. Austin |
Optimizations Enabled by a Decoupled Front-End Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 50(4), pp. 338-355, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
fetch architectures, branch prediction, Decoupled architectures, instruction prefetching |
64 | Afzal Hossain, Daniel J. Pease, James S. Burns, Nasima Parveen |
A Mathematical Model of Trace Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 13th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2002), 17-19 July 2002, San Jose, CA, USA, pp. 151-162, 2002, IEEE Computer Society, 0-7695-1712-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
57 | Osman S. Unsal, Israel Koren, C. Mani Krishna 0001, Csaba Andras Moritz |
Cool-Fetch: Compiler-Enabled Power-Aware Fetch Throttling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Comput. Archit. Lett. ![In: IEEE Comput. Archit. Lett. 1, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
instruction Ievel parallelism, fetch-throttling, Low power design, compiler architecture interaction |
56 | Eric L. Hill, Mikko H. Lipasti |
Stall cycle redistribution in a transparent fetch pipeline. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 31-36, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
pipeline gating, microarchitecture, dynamic power, instruction fetch |
56 | Francisco J. Cazorla, Enrique Fernández, Alex Ramírez, Mateo Valero |
Improving Memory Latency Aware Fetch Policies for SMT Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISHPC ![In: High Performance Computing, 5th International Symposium, ISHPC 2003, Tokyo-Odaiba, Japan, October 20-22, 2003, Proceedings, pp. 70-85, 2003, Springer, 3-540-20359-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
fetch policy, long latency loads, load miss predictors, multithreading, SMT |
56 | Sanjay J. Patel, Daniel H. Friendly, Yale N. Patt |
Evaluation of Design Options for the Trace Cache Fetch Mechanism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 48(2), pp. 193-204, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
High bandwidth fetch mechanisms, wide issue machines, speculative execution, instruction cache, trace cache |
56 | Emre Özer 0001, Ronald G. Dreslinski, Trevor N. Mudge, Stuart Biles, Krisztián Flautner |
Energy-Efficient Simultaneous Thread Fetch from Different Cache Levels in a Soft Real-Time SMT Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation, 8th International Workshop, SAMOS 2008, Samos, Greece, July 21-24, 2008. Proceedings, pp. 12-22, 2008, Springer, 978-3-540-70549-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Real-time, Energy Efficiency, Caches, Embedded Processors, SMT |
56 | Stijn Eyerman, Lieven Eeckhout |
A Memory-Level Parallelism Aware Fetch Policy for SMT Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 10-14 February 2007, Phoenix, Arizona, USA, pp. 240-249, 2007, IEEE Computer Society, 1-4244-0804-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
56 | Bernhard Fechner |
A Fault-Tolerant Dynamic Fetch Policy for SMT Processors in Multi-Bus Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PARELEC ![In: Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 13-17 September 2006, Bialystok, Poland, pp. 31-36, 2006, IEEE Computer Society, 0-7695-2554-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
56 | Juan L. Aragón, Alexander V. Veidenbaum |
Energy-Effective Instruction Fetch Unit for Wide Issue Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, ACSAC 2005, Singapore, October 24-26, 2005, Proceedings, pp. 15-27, 2005, Springer, 3-540-29643-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
56 | Juan C. Moure, R. B. García, Dolores Rexachs, Emilio Luque |
Improving Single-Thread Fetch Performance on a Multithreaded Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 4-6 September 2001, Warsaw, Poland, pp. 390-395, 2001, IEEE Computer Society, 0-7695-1239-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
56 | Carlos Navarro, Alex Ramírez, Josep Lluís Larriba-Pey, Mateo Valero |
On the Performance of Fetch Engines Running DSS Workloads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29 - September 1, 2000, Proceedings., pp. 940-949, 2000, Springer, 3-540-67956-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
56 | Artur Klauser, Dirk Grunwald |
Instruction Fetch Mechanisms for Multipath Execution Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 32, Haifa, Israel, November 16-18, 1999, pp. 38-47, 1999, ACM/IEEE Computer Society, 0-7695-0437-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
56 | Glenn Reinman, Brad Calder, Todd M. Austin |
Fetch Directed Instruction Prefetching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 32, Haifa, Israel, November 16-18, 1999, pp. 16-27, 1999, ACM/IEEE Computer Society, 0-7695-0437-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
55 | Sreeram Duvvuru, Siamak Arya |
Evaluation of a branch target address cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS (1) ![In: 28th Annual Hawaii International Conference on System Sciences (HICSS-28), January 3-6, 1995, Kihei, Maui, Hawaii, USA, pp. 173-180, 1995, IEEE Computer Society, 0-8186-6945-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
branch target address cache evaluation, sequential flow, pipeline bubbles, branch penalty, cycles per instruction, multiple instruction issue processors, branch resolution scheme, target instruction fetch, unpredictable branches, fully predicated processor architecture, fetch stage, branch target caching policies, branch target address cache, register-relative branches, performance evaluation, interrupts, interrupt, program compilers, pipeline processing, cache storage, storage allocation, instructions, program control structures, cache sizes |
55 | Weiyu Tang, Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau |
A predictive decode filter cache for reducing power consumption in embedded processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 12(2), pp. 14, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Cache, embedded processors, power optimization |
55 | Afzal Hossain, Daniel J. Pease, James S. Burns, Nasima Parveen |
Trace Cache Performance Parameters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings, pp. 348-355, 2002, IEEE Computer Society, 0-7695-1700-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
51 | David M. Martin Jr., Richard M. Smith, Michael Brittain, Ivan Fetch, Hailin Wu |
The privacy practices of web browser extensions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Commun. ACM ![In: Commun. ACM 44(2), pp. 45-50, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
47 | Andi Ahmad Dahlan, Toshikazu Nishimura |
Implementation of asynchronous predictive fetch to improve the performance of Ajax-enabled web applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
iiWAS ![In: iiWAS'2008 - The Tenth International Conference on Information Integration and Web-based Applications Services, 24-26 November 2008, Linz, Austria, pp. 345-350, 2008, ACM, 978-1-60558-349-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
predictive fetch, performance, web application, Ajax |
47 | Jude A. Rivers, Sameh W. Asaad, John-David Wellman, Jaime H. Moreno |
Reducing instruction fetch energy with backwards branch control information and buffering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003, Seoul, Korea, August 25-27, 2003, pp. 322-325, 2003, ACM, 1-58113-682-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
loop buffer, low-power, instruction fetch |
47 | Hans Vandierendonck, André Seznec |
Fetch Gating Control through Speculative Instruction Window Weighting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Trans. High Perform. Embed. Archit. Compil. ![In: Transactions on High-Performance Embedded Architectures and Compilers II, pp. 128-148, 2009, Springer, 978-3-642-00903-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
47 | Nikola Vujic, Marc González 0001, Xavier Martorell, Eduard Ayguadé |
Automatic Pre-Fetch and Modulo Scheduling Transformations for the Cell BE Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCPC ![In: Languages and Compilers for Parallel Computing, 21th International Workshop, LCPC 2008, Edmonton, Canada, July 31 - August 2, 2008, Revised Selected Papers, pp. 31-46, 2008, Springer, 978-3-540-89739-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Cell BE Architecture, Modulo Scheduling, Pre-fetching, Software Cache |
47 | Hans Vandierendonck, André Seznec |
Fetch Gating Control Through Speculative Instruction Window Weighting. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings, pp. 120-135, 2007, Springer, 978-3-540-69337-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
47 | Chieh-Yih Wan, Andrew T. Campbell, Lakshman Krishnamurthy |
Pump-slowly, fetch-quickly (PSFQ): a reliable transport protocol for sensor networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE J. Sel. Areas Commun. ![In: IEEE J. Sel. Areas Commun. 23(4), pp. 862-872, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
47 | Tzung-Rei Yang, Jong-Jiann Shieh |
Dynamic Fetch Engine for Simultaneous Multithreaded Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, ACSAC 2004, Beijing, China, September 7-9, 2004, Proceedings, pp. 489-502, 2004, Springer, 3-540-23003-3. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
47 | Jie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir |
Using Dynamic Branch Behavior for Power-Efficient Instruction Fetch. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), New Trends and Technologies for VLSI Systems Design, 20-21 February 2003, Tampa, FL, USA, pp. 127-132, 2003, IEEE Computer Society, 0-7695-1904-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
47 | James H. Anderson, Yong-Jik Kim |
Local-spin Mutual Exclusion Using Fetch-and-\phi Primitives. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDCS ![In: 23rd International Conference on Distributed Computing Systems (ICDCS 2003), 19-22 May 2003, Providence, RI, USA, pp. 538-, 2003, IEEE Computer Society, 0-7695-1920-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
47 | Heidi Pan, Krste Asanovic |
Heads and tails: a variable-length instruction format supporting parallel fetch and decode. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2001 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2001, Atlanta, Georgia, USA, November 16-17, 2001, pp. 168-175, 2001, ACM, 1-58113-399-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
47 | Eric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt |
Increasing the Instruction Fetch Rate via Block-structured Instruction Set Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 29th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 29, Paris, France, December 2-4, 1996, pp. 191-200, 1996, ACM/IEEE Computer Society, 0-8186-7641-8. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
47 | Thomas M. Conte, Kishore N. Menezes, Patrick M. Mills, Burzin A. Patel |
Optimization of Instruction Fetch Mechanisms for High Issue Rates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 22nd Annual International Symposium on Computer Architecture, ISCA '95, Santa Margherita Ligure, Italy, June 22-24, 1995, pp. 333-344, 1995, ACM, 0-89791-698-0. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
46 | Muhammad Shaaban, Edward Mulrane |
Improving trace cache hit rates using the sliding window fill mechanism and fill select table. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Memory System Performance ![In: Proceedings of the 2004 workshop on Memory System Performance, Washington, DC, USA, June 8, 2004, pp. 36-41, 2004, ACM, 1-58113-941-1. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
branch promotion, fetch mechanisms, fill mechanisms, superscalar processors, cache performance, trace cache |
38 | Reoma Matsuo, Ryota Shioya, Hideki Ando |
Improving the Instruction Fetch Throughput with Dynamically Configuring the Fetch Pipeline. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Comput. Archit. Lett. ![In: IEEE Comput. Archit. Lett. 18(2), pp. 170-173, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
38 | Pengfei Wang 0010, Jens Krinke, Kai Lu, Gen Li 0002, Steve Dodier-Lazaro |
How Double-Fetch Situations turn into Double-Fetch Vulnerabilities: A Study of Double Fetches in the Linux Kernel. ![Search on Bibsonomy](Pics/bibsonomy.png) |
USENIX Security Symposium ![In: 26th USENIX Security Symposium, USENIX Security 2017, Vancouver, BC, Canada, August 16-18, 2017., pp. 1-16, 2017, USENIX Association. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
|
38 | Prithviraj Banerjee, Abhijeet Dugar |
The Design, Analysis and Simulation of a Fault-Tolerant Interconnection Network Supporting the Fetch-and-Add Primitive. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 38(1), pp. 30-46, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
fault-tolerant interconnection network, fetch-and-add primitive, combining multistage interconnection network, 4*4 switches, four independent paths, scheduling, fault tolerant computing, multiprocessor interconnection networks, analytical models, network simulations, omega network |
38 | Caixia Sun, Hong-Wei Tang, Minxuan Zhang |
Enhancing ICOUNT2.8 Fetch Policy with Better Fairness for SMT Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asia-Pacific Computer Systems Architecture Conference ![In: Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, ACSAC 2006, Shanghai, China, September 6-8, 2006, Proceedings, pp. 459-465, 2006, Springer, 3-540-40056-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
38 | Abdelli Abdelkrim, Nadjib Badache |
A semantic based pre-fetch scheme for SMIL presentation proxy-delivery. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MMM ![In: 12th International Conference on Multi Media Modeling (MMM 2006), 4-6 January 2006, Beijing, China, 2006, IEEE, 1-4244-0028-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
38 | Ayose Falcón, Alex Ramírez, Mateo Valero |
Effective Instruction Prefetching via Fetch Prestaging. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, 2005, IEEE Computer Society, 0-7695-2312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
38 | Nikil Mehta, Brian Singer, R. Iris Bahar, Michael Leuchtenburg, Richard S. Weiss |
Fetch Halting on Critical Load Misses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 244-249, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
38 | Rafael R. dos Santos, Philippe Olivier Alexandre Navaux |
Analysing a Multistreamed Superscalar Speculative Fetch Mechanism. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par '98 Parallel Processing, 4th International Euro-Par Conference, Southampton, UK, September 1-4, 1998, Proceedings, pp. 1010-1017, 1998, Springer, 3-540-64952-2. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
38 | Freddy Gabbay, Avi Mendelson |
The Effect of Instruction Fetch Bandwidth on Value Prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 25th Annual International Symposium on Computer Architecture, ISCA 1998, Barcelona, Spain, June 27 - July 1, 1998, pp. 272-281, 1998, IEEE Computer Society, 0-8186-8491-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
37 | Deze Zeng, Minyi Guo, Song Guo 0001, Mianxiong Dong, Hai Jin 0001 |
The Design and Evaluation of a Selective Way Based Trace Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPT ![In: Advanced Parallel Processing Technologies, 8th International Symposium, APPT 2009, Rapperswil, Switzerland, August 24-25, 2009, Proceedings, pp. 95-109, 2009, Springer, 978-3-642-03643-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
instruction fetch unit design, selective way, energy efficient, computer architecture, trace cache |
37 | Wangyuan Zhang, Xin Fu, Tao Li 0006, José A. B. Fortes |
An Analysis of Microarchitecture Vulnerability to Soft Errors on Simultaneous Multithreaded Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: 2007 IEEE International Symposium on Performance Analysis of Systems and Software, April 25-27, 2007, San Jose, California, USA, Proceedings, pp. 169-178, 2007, IEEE Computer Society, 1-4244-1081-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
thread-aware reliability optimization, microarchitecture vulnerability, simultaneous multithreaded architecture, semiconductor transient fault, microprocessor reliability, processor throughput, soft error vulnerability analysis, SPEC CPU 2000 benchmark, microarchitecture structure, microarchitecture reliability profile, fetch policy, thread-level parallelism, multithreading architecture |
37 | Yehuda Afek, Eran Shalom |
Less Is More: Consensus Gaps Between Restricted and Unrestricted Objects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DISC ![In: Distributed Computing, 20th International Symposium, DISC 2006, Stockholm, Sweden, September 18-20, 2006, Proceedings, pp. 209-223, 2006, Springer, 3-540-44624-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Consensus hierarchy, Common2, Bounded-use, Bounded-size, Long-lived, Fetch&Add, Queues, Stacks, Set, Wait-free, Swap |
37 | Saurabh Chheda, Osman S. Unsal, Israel Koren, C. Mani Krishna 0001, Csaba Andras Moritz |
Combining compiler and runtime IPC predictions to reduce energy in next generation architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the First Conference on Computing Frontiers, 2004, Ischia, Italy, April 14-16, 2004, pp. 240-254, 2004, ACM, 1-58113-741-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
fetch throttling, low power design, instruction level parallelism, compiler architecture interaction, adaptive voltage scaling |
37 | Ayose Falcón, Oliverio J. Santana, Alex Ramírez, Mateo Valero |
Tolerating Branch Predictor Latency on SMT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISHPC ![In: High Performance Computing, 5th International Symposium, ISHPC 2003, Tokyo-Odaiba, Japan, October 20-22, 2003, Proceedings, pp. 86-98, 2003, Springer, 3-540-20359-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
branch predictor delay, decoupled fetch, predictorpipelining, SMT |
37 | Stéphan Jourdan, Lihu Rappoport, Yoav Almog, Mattan Erez, Adi Yoaz, Ronny Ronen |
eXtended Block Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, Toulouse, France, January 8-12, 2000, pp. 61-70, 2000, IEEE Computer Society, 0-7695-0550-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
fetch bandwidth, instruction cache, trace cache, Front-end |
37 | Jih-Ching Chiu, I-Huan Huang, Chung-Ping Chung |
Design of Instruction Stream Buffer with Trace Support for X86 Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, ICCD '00, Austin, Texas, USA, September 17-20, 2000, pp. 294-299, 2000, IEEE Computer Society, 0-7695-0801-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
instruction stream buffer, x86 architecture, multiple instruction fetch, superscalar processor, ILP, Trace cache |
37 | Oliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero |
DIA: A Complexity-Effective Decoding Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 58(4), pp. 448-462, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
37 | Chengmo Yang, Alex Orailoglu |
Power-efficient instruction delivery through trace reuse. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), Seattle, Washington, USA, September 16-20, 2006, pp. 192-201, 2006, ACM, 1-59593-264-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
adaptive processor, low-power design, instruction delivery |
37 | Oliverio J. Santana, Ayose Falcón, Alex Ramírez, Mateo Valero |
Branch predictor guided instruction decoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACT ![In: 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), Seattle, Washington, USA, September 16-20, 2006, pp. 202-211, 2006, ACM, 1-59593-264-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
complexity-effective, instruction decoding, branch predictor |
37 | Kugan Vivekanandarajah, Thambipillai Srikanthan, Saurav Bhattacharyya |
Decode filter cache for energy efficient instruction cache hierarchy in super scalar architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 373-379, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
37 | Hans Vandierendonck, Hans Logie, Koenraad De Bosschere |
Trace Substitution. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2003. Parallel Processing, 9th International Euro-Par Conference, Klagenfurt, Austria, August 26-29, 2003. Proceedings, pp. 556-565, 2003, Springer, 3-540-40788-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
37 | P. Krishna Gummadi, Richard J. Dunn, Stefan Saroiu, Steven D. Gribble, Henry M. Levy, John Zahorjan |
Measurement, modeling, and analysis of a peer-to-peer file-sharing workload. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SOSP ![In: Proceedings of the 19th ACM Symposium on Operating Systems Principles 2003, SOSP 2003, Bolton Landing, NY, USA, October 19-22, 2003, pp. 314-329, 2003, ACM, 1-58113-757-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
multimedia workloads, modeling, peer-to-peer, measurement, Zipf's law |
37 | Chin-Tser Huang, Mohamed G. Gouda, E. N. Elnozahy |
Convergence of IPsec in Presence of Resets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICDCS Workshops ![In: 23rd International Conference on Distributed Computing Systems Workshops (ICDCS 2003 Workshops), 19-22 May 2003, Providence, RI, USA, pp. 22-27, 2003, IEEE Computer Society, 0-7695-1921-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
37 | Nael B. Abu-Ghazaleh, Philip A. Wilsey |
On the Structure of Concurrent Interpreters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 15-19 April 2002, Fort Lauderdale, FL, USA, CD-ROM/Abstracts Proceedings, 2002, IEEE Computer Society, 0-7695-1573-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
37 | Roni Rosner, Avi Mendelson, Ronny Ronen |
Filtering Techniques to Improve Trace-Cache Efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE PACT ![In: 2001 International Conference on Parallel Architectures and Compilation Techniques (PACT 2001), 8-12 September 2001, Barcelona, Spain, pp. 37-48, 2001, IEEE Computer Society, 0-7695-1363-8. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
37 | Eric Rotenberg, Steve Bennett, James E. Smith 0001 |
A Trace Cache Microarchitecture and Evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 48(2), pp. 111-120, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
multiple branch prediction, superscalar processors, Instruction cache, trace cache, instruction fetching |
37 | Simonjit Dutta, Manoj Franklin |
Control Flow Prediction Schemes for Wide-Issue Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 10(4), pp. 346-359, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Block-level prediction, multiple-issue processors, multiple-branch prediction, tree-level prediction, speculative execution, trace cache, instruction-level parallelism (ILP) |
37 | Glenn Reinman, Todd M. Austin, Brad Calder |
A Scalable Front-End Architecture for Fast Instruction Delivery. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 26th Annual International Symposium on Computer Architecture, ISCA 1999, Atlanta, Georgia, USA, May 2-4, 1999, pp. 234-245, 1999, IEEE Computer Society, 0-7695-0170-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
37 | Sanjay J. Patel, Marius Evers, Yale N. Patt |
Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 25th Annual International Symposium on Computer Architecture, ISCA 1998, Barcelona, Spain, June 27 - July 1, 1998, pp. 262-271, 1998, IEEE Computer Society, 0-8186-8491-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
37 | Brad Calder, Dirk Grunwald |
Next Cache Line and Set Prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 22nd Annual International Symposium on Computer Architecture, ISCA '95, Santa Margherita Ligure, Italy, June 22-24, 1995, pp. 287-296, 1995, ACM, 0-89791-698-0. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
28 | Marcio Buss, Daniel Brand, Vugranam C. Sreedhar, Stephen A. Edwards |
Flexible pointer analysis using assign-fetch graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), Fortaleza, Ceara, Brazil, March 16-20, 2008, pp. 234-239, 2008, ACM, 978-1-59593-753-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
summary-based analysis, static analysis, pointer analysis |
28 | Michael Ferdman, Thomas F. Wenisch, Anastasia Ailamaki, Babak Falsafi, Andreas Moshovos |
Temporal instruction fetch streaming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), November 8-12, 2008, Lake Como, Italy, pp. 1-10, 2008, IEEE Computer Society, 978-1-4244-2836-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Ping Chao, Youn-Long Lin |
A motion compensation system with a high efficiency reference frame pre-fetch scheme for QFHD H.264/AVC decoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2008), 18-21 May 2008, Sheraton Seattle Hotel, Seattle, Washington, USA, pp. 256-259, 2008, IEEE, 978-1-4244-1683-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
28 | Andrew Robinson, Jim D. Garside |
Sensitive registers: a technique for reducing the fetch bandwidth in low-power microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007, pp. 138-143, 2007, ACM, 978-1-59593-605-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
processors, memory bandwidth, power efficiency, registers |
28 | Michael L. Walters, Kerstin Dautenhahn, Sarah N. Woods, Kheng Lee Koay |
Robotic etiquette: results from user studies involving a fetch and carry task. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HRI ![In: Proceedings of the Second ACM SIGCHI/SIGART Conference on Human-Robot Interaction, HRI 2007, Arlington, Virginia, USA, March 10-12, 2007, pp. 317-324, 2007, ACM, 978-1-59593-617-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
live interactions, human-robot interaction, social robot, personal spaces, user trials, social spaces |
28 | Prabhu Rajamani, Jatan P. Shah, Vadhiraj Sankaranarayanan, Rama Sangireddy |
High performance and alleviated hot-spot problem in processor frontend with enhanced instruction fetch bandwidth utilization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPCCC ![In: Proceedings of the 25th IEEE International Performance Computing and Communications Conference, IPCCC 2006, April 10-12, 2006, Phoenix, Arizona, USA, 2006, IEEE, 1-4244-0198-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Ziqian Liu, Changjia Chen |
Modeling Fetch-at-Most-Once Behavior in Peer-to-Peer File-Sharing Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APWeb Workshops ![In: Advanced Web and Network Technologies, and Applications, APWeb 2006 International Workshops: XRA, IWSN, MEGA, and ICSE, Harbin, China, January 16-18, 2006, Proceedings, pp. 717-724, 2006, Springer, 3-540-31158-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
28 | Stephen Hines, Gary S. Tyson, David B. Whalley |
Reducing Instruction Fetch Cost by Packing Instructions into RegisterWindows. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-38 2005), 12-16 November 2005, Barcelona, Spain, pp. 19-29, 2005, IEEE Computer Society, 0-7695-2440-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
28 | Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Enrique Fernández |
DCache Warn: An I-Fetch Policy to Increase SMT Efficiency. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), CD-ROM / Abstracts Proceedings, 26-30 April 2004, Santa Fe, New Mexico, USA, 2004, IEEE Computer Society, 0-7695-2132-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
28 | Gregory A. Muthler, David Crowe, Sanjay J. Patel, Steven Lumetta |
Instruction fetch deferral using static slack. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: Proceedings of the 35th Annual International Symposium on Microarchitecture, Istanbul, Turkey, November 18-22, 2002, pp. 51-61, 2002, ACM/IEEE Computer Society, 0-7695-1859-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
28 | Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo, Rebecca L. Stamm |
Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 23rd Annual International Symposium on Computer Architecture, Philadelphia, PA, USA, May 22-24, 1996, pp. 191-202, 1996, ACM, 0-89791-786-3. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
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