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Publication years (Num. hits)
1982-1989 (24) 1990-1992 (19) 1993-1994 (17) 1995-1996 (17) 1997-1998 (19) 1999 (16) 2000 (18) 2001 (16) 2002 (25) 2003 (27) 2004 (37) 2005 (39) 2006 (47) 2007 (44) 2008 (31) 2009 (27) 2010-2012 (18) 2013-2015 (23) 2016 (16) 2017-2018 (17) 2019-2020 (23) 2021-2022 (27) 2023 (21) 2024 (5)
Publication types (Num. hits)
article(180) incollection(10) inproceedings(381) phdthesis(2)
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Found 573 publication records. Showing 573 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
103Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu Effective decap insertion in area-array SoC floorplan design. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF decap insertion, floorplan, Power supply noise
93Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen Twin binary sequences: a nonredundant representation for general nonslicing floorplan. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
93Evangeline F. Y. Young, Chris C. N. Chu, Zion Cien Shen Twin binary sequences: a non-redundant representation for general non-slicing floorplan. Search on Bibsonomy ISPD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
84Claudia I. Horta, José A. Lima Slicing and non-slicing, unified and rotation independent, algebraic representation of floorplans. Search on Bibsonomy EUROMICRO The full citation details ... 1997 DBLP  DOI  BibTeX  RDF floorplan area optimization problem, rectangle envelope, nonoverlapping basic rectangles, floorplan topology, formal algebraic specification, SETS notation, VLSI physical design layout, module dimensions, arbitrarily complex composite floorplans, rotation-invariant single-expression formalism, generalized wheels floorplans, slicing representation, nonslicing representation, unified representation, topology-dimensionless description, floorplanning problem algorithms, algebraic specification, line segments, relative positioning
82Michael D. Moffitt, Aaron N. Ng, Igor L. Markov, Martha E. Pollack Constraint-driven floorplan repair. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF constraints, floorplanning, legalization
82Chih-Hung Lee, Wen-Yu Fu, Chung-Chiao Chang, Tsai-Ming Hsieh An efficient hierarchical approach for general floorplan area minimization. Search on Bibsonomy APCCAS (2) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
81Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham Floorplan representations: Complexity and connections. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Baxter permutation, Floorplan representation, O-tree, mosaic floorplan, number of combinations, twin binary trees
81P. S. Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya VLSI floorplan generation and area optimization using AND-OR graph search. Search on Bibsonomy VLSI Design The full citation details ... 1995 DBLP  DOI  BibTeX  RDF VLSI floorplan generation, AND-OR graph search, rectangular dualization, minimum-area floorplan, optimal sizing, heuristic search method, top-down first phase, search effort, bottom-up polynomial-time algorithm, nonslicible floorplans, VLSI, graph theory, circuit layout CAD, circuit optimisation, integrated circuit interconnections, aspect ratios, area optimization, adjacency graph
74Shin-Ichi Nakano Enumerating Floorplans with n Rooms. Search on Bibsonomy ISAAC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF Graphs, Enumeration, Listing, Plane graphs
74Jin-Tai Yan An efficient cut-based algorithm on minimizing the number of L-shaped channels for safe routing ordering. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
74Qing Dong 0002, Bo Yang 0004, Jing Li 0072, Shigetoshi Nakatake Incremental buffer insertion and module resizing algorithm using geometric programming. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF module resizing, floorplan, buffer insertion, geometric programming
72Michael D. Moffitt, Jarrod A. Roy, Igor L. Markov, Martha E. Pollack Constraint-driven floorplan repair. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF constraints, Floorplanning, legalization
72Chiu-Wing Sham, Evangeline F. Y. Young Area reduction by deadspace utilization on interconnect optimized floorplan. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF area reduction, Floorplanning
64Saurabh N. Adya, Igor L. Markov Fixed-outline floorplanning: enabling hierarchical design. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
64Zion Cien Shen, Chris C. N. Chu Bounds on the number of slicing, mosaic, and general floorplans. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
61Kenichi Ida, Yosuke Kimura Floorplan Design Using Improved Genetic Algorithm. Search on Bibsonomy ISMIS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
61Jiann-Horng Lin, Jing-Yang Jou, Iris Hui-Ru Jiang Hierarchical Floorplan Design on the Internet. Search on Bibsonomy ASP-DAC The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
61H. Cai On empty rooms in floorplan graphics: comments on a deficiency in two papers. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
60Chuan Lin 0002, Hai Zhou 0001, Chris C. N. Chu A revisit to floorplan optimization by Lagrangian relaxation. Search on Bibsonomy ICCAD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF floorplan, Lagrangian relaxation
53Jackey Z. Yan, Chris Chu DeFer: deferred decision making enabled fixed-outline floorplanner. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF deferred decision making, floorplanning, fixed outline
53Maolin Tang, Alvin Sebastian A Genetic Algorithm for VLSI Floorplanning Using O-Tree Representation. Search on Bibsonomy EvoWorkshops The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
53Vinod Narayananan, David LaPotin, Rajesh Gupta 0003, Gopalakrishnan Vijayan PEPPER - a timing driven early floorplanner. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF PEPPER, timing driven early floorplanner, chip complexities, early analysis, performance critical CMOS chips, wireability, floorplan optimization process, performance, computational complexity, optimisation, timing, system design, circuit layout CAD, CMOS integrated circuits, static timing analysis, integrated circuit layout, area, interconnect delay
50Zaichen Qian, Evangeline F. Y. Young Multi-voltage floorplan design with optimal voltage assignment. Search on Bibsonomy ISPD The full citation details ... 2009 DBLP  DOI  BibTeX  RDF multi-voltage assignment optimization branch-and-bound
50Xiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong Heuristic power/ground network and floorplan co-design method. Search on Bibsonomy ASP-DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
50Maolin Tang A New Greedy Algorithm for VLSI Floorplan Optimization. Search on Bibsonomy CSSE (4) The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
50Chen-Wei Liu, Yao-Wen Chang Power/Ground Network and Floorplan Cosynthesis for Fast Design Convergence. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
50Shih-Hsu Huang, Chu-Liao Wang, Man-Lin Huang A Floorplan-Based Power Network Analysis Methodology for System-on-Chip Designs. Search on Bibsonomy EUC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Reused Block, Modeling, Power Consumption, Voltage Drop
50Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs. Search on Bibsonomy VLSI Design The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
50Chen-Wei Liu, Yao-Wen Chang Floorplan and power/ground network co-synthesis for fast design convergence. Search on Bibsonomy ISPD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF power/ground analysis, simulated annealing, floorplanning, IR drop, power integrity
50Jin-Tai Yan, Kai-Ping Lin, Yue-Fong Luo Floorplan-aware decoupling capacitance budgeting on equivalent circuit model. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
50Yongpan Liu, Huazhong Yang, Rong Luo, Hui Wang 0004 A Hierarchical Approach for Incremental Floorplan Based on Genetic Algorithms. Search on Bibsonomy ICNC (3) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
50Dongku Kang, Hunsoo Choo, Kaushik Roy 0001 Floorplan-Aware Low-Complexity Digital Filter Synthesis for Low-Power & High-Speed. Search on Bibsonomy ICCD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
50Bo Yao, Hongyu Chen, Chung-Kuan Cheng, Ronald L. Graham Revisiting floorplan representations. Search on Bibsonomy ISPD The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
50D. F. Wong 0001, P. S. Sakhamuri Efficient Floorplan Area Optimization. Search on Bibsonomy DAC The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
50Ou He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng Bus via reduction based on floorplan revising. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2010 DBLP  DOI  BibTeX  RDF floorplan revising, via reduction, bus routing
50Dipanjan Sengupta, Resve A. Saleh Application-driven floorplan-aware voltage island design. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF dynamic programming, energy, floorplan, voltage island
50Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir Floorplan driven leakage power aware IP-based SoC design space exploration. Search on Bibsonomy CODES+ISSS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF floorplan, leakage power, temperature
50Srinivasan Murali, Paolo Meloni, Federico Angiolini, David Atienza, Salvatore Carta, Luca Benini, Giovanni De Micheli, Luigi Raffo Designing application-specific networks on chips with floorplan information. Search on Bibsonomy ICCAD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF networks on chips, topology, floorplan, deadlock-free routing
42Hushrav Mogal, Kia Bazargan Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction. Search on Bibsonomy ICCAD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
42Jin-Tai Yan, Kai-Ping Lin, Yen-Hsiang Chen Decoupling capacitance allocation in noise-aware floorplanning based on DBL representation. Search on Bibsonomy ISCAS (3) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
42Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao Simultaneous floor plan and buffer-block optimization. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
42Xuliang Zhang, Yoji Kajitani Space-planning: placement of modules with controlled empty area by single-sequence. Search on Bibsonomy ASP-DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
42Zahava Koren, Israel Koren On the effect of floorplanning on the yield of large area integrated circuits. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
42Parthasarathi Dasgupta, Anup K. Sen, Subhas C. Nandy, Bhargab B. Bhattacharya Geometric bipartitioning problem and its applications to VLSI. Search on Bibsonomy VLSI Design The full citation details ... 1996 DBLP  DOI  BibTeX  RDF geometric bipartitioning problem, layout design, rectilinear modules, staircase, monotone increasing, classical graph bisection problem, weighted permutation graph, integer edge weights, designated nodes, absolute value, edge weights, routing, computational complexity, VLSI, VLSI, graph theory, NP-complete, branch-and-bound, floorplan, heuristic algorithm, search problems, geometry, network routing, circuit layout CAD, hierarchical decomposition
42Jin-Tai Yan An efficient cut-based algorithm on minimizing the number of L-shaped channels for safe routing ordering. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF cut-based algorithm, L-shaped channels, safe routing ordering, geometrical topology, floorplan graph, channel precedence graph, S-cuts, redundant L-cuts, balanced L-cuts, non-minimal L-cuts, non-critical L-cuts, critical L-cuts, computational complexity, time complexity, circuit layout CAD, line segments, precedence relations
40Jia Wang 0003, Hai Zhou 0001 Linear constraint graph for floorplan optimization with soft blocks. Search on Bibsonomy ICCAD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
40Zhipeng Liu, Jinian Bian, Qiang Zhou 0001, Hui Dai Interconnect Delay and Power Optimization by Module Duplication for Integration of High Level Synthesis and Floorplan. Search on Bibsonomy ISVLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
40Vyas Krishnan, Srinivas Katkoori Minimizing wire delays by net-topology aware binding during floorplan- driven high level synthesis. Search on Bibsonomy VLSI-SoC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
40Jin-Tai Yan, Zhi-Wei Chen, Ming-Yuen Wu Area-Driven Decoupling Capacitance Allocation in Noise-Aware Floorplan for Signal Integrity. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
40Yunfeng Wang, Jinian Bian, Xianlong Hong, Liu Yang, Qiang Zhou 0001, Qiang Wu A New Methodology of Integrating High Level Synthesis and Floorplan for SoC Design. Search on Bibsonomy ICESS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
40Hayward H. Chan, Saurabh N. Adya, Igor L. Markov Are floorplan representations important in digital design? Search on Bibsonomy ISPD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF B*-tree, floorplanning, sequence pair, circuit layout
40Jin-Tai Yan, Chia-Wei Wu, Yen-Hsiang Chen Wiring area optimization in floorplan-aware hierarchical power grids. Search on Bibsonomy ISCAS (2) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
40Wing Seung Yuen, Evangeline F. Y. Young Slicing floorplan with clustering constraint. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
40Dongku Kang, Mark C. Johnson, Kaushik Roy 0001 Multiple-Vdd Scheduling/Allocation for Partitioned Floorplan. Search on Bibsonomy ICCD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
40Wai-Chiu Wong, Chiu-Wing Sham, Evangeline F. Y. Young Congestion Estimation with Buffer Planning in Floorplan Design. Search on Bibsonomy DATE The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
40Chang-Tzu Lin, De-Sheng Chen, Yiwen Wang 0003 GPE: A New Representation for VLSI Floorplan Problem. Search on Bibsonomy ICCD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
40Shih-Hsu Huang, Chu-Liao Wang An effective floorplan-based power distribution network design methodology under reliability constraints. Search on Bibsonomy ISCAS (1) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
40Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing. Search on Bibsonomy ASP-DAC/VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
40Evangeline F. Y. Young, Chris C. N. Chu, W. S. Luk, Y. C. Wong Handling soft modules in general nonslicing floorplan usingLagrangian relaxation. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
40Evangeline F. Y. Young, Martin D. F. Wong, Hannah Honghua Yang On extending slicing floorplan to handle L/T-shaped modules andabutment constraints. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
40Xiaobo Hu 0001, Danny Z. Chen, Rajeshkumar S. Sambandam Efficient list-approximation techniques for floorplan area minimization. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF k-link shortest paths, list approximation, floorplanning, area minimization
40Wing Seung Yuen, Fung Yu Young Slicing floorplan with clustering constraints. Search on Bibsonomy ASP-DAC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
40Gary K. H. Yeap, Majid Sarrafzadeh A unified approach to floorplan sizing and enumeration. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
40James P. Cohoon, Shailesh U. Hegde, Worthy N. Martin, Dana S. Richards Distributed genetic algorithms for the floorplan design problem. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1991 DBLP  DOI  BibTeX  RDF
40Cheng-Hsi Chen, Ioannis G. Tollis Parallel algorithms for slicing floorplan designs. Search on Bibsonomy SPDP The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
40Chang-Sheng Ying, Joshua Sook-Leung Wong, X. L. Hong, E. Q. Wang Path search on rectangular floorplan. Search on Bibsonomy EURO-DAC The full citation details ... 1990 DBLP  DOI  BibTeX  RDF
40Yen-Tai Lai, Sany M. Leinwand Algorithms for floorplan design via rectangular dualization. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1988 DBLP  DOI  BibTeX  RDF
39Rory McInerney, Kurt Leeper, Troy Hill, Heming Chan, Bulent Basaran, Lance McQuiddy Methodology for repeater insertion management in the RTL, layout, floorplan and fullchip timing databases of the Itanium microprocessor. Search on Bibsonomy ISPD The full citation details ... 2000 DBLP  DOI  BibTeX  RDF RC delay, routing, timing, estimation, microprocessors, floorplan, repeaters
32De-Yu Liu, Wai-Kei Mak, Ting-Chi Wang Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2010 DBLP  DOI  BibTeX  RDF wire bonding, floorplanning, system-in-package
32Yuchun Ma, Xiang Qiu, Xiangqing He, Xianlong Hong Incremental power optimization for multiple supply voltage design. Search on Bibsonomy ISQED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
32Song Chen 0001, Zheng Xu, Takeshi Yoshimura A generalized V-shaped multilevel method for large scale floorplanning. Search on Bibsonomy ISQED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
32Chaomin Luo, Miguel F. Anjos, Anthony Vannelli A nonlinear optimization methodology for VLSI fixed-outline floorplanning. Search on Bibsonomy J. Comb. Optim. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Circuit layout design, VLSI floorplanning, Facility layout, Combinatorial optimization, Global optimization, Convex programming
32Sami Habib, Maytham Safar Sensitivity Study of Sensors' Coverage within Wireless Sensor Networks. Search on Bibsonomy ICCCN The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
32Vijay Sundaresan, Ranga Vemuri A Novel Approach to Performance-Oriented Datapath Allocation and Floorplanning. Search on Bibsonomy ISVLSI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
32Ryan Kastner, Wenrui Gong, Xin Hao, Forrest Brewer, Adam Kaplan, Philip Brisk, Majid Sarrafzadeh Layout driven data communication optimization for high level synthesis. Search on Bibsonomy DATE The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
32Rung-Bin Lin, Meng-Chiou Wu, Wei-Chiu Tseng, Ming-Hsine Kuo, Tsai-Ying Lin, Shr-Cheng Tsai Design space exploration for minimizing multi-project wafer production cost. Search on Bibsonomy ASP-DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
32Takashi Sato, Junji Ichimiya, Nobuto Ono, Koutaro Hachiya, Masanori Hashimoto On-chip thermal gradient analysis and temperature flattening for SoC design. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
32Jill H. Y. Law, Evangeline F. Y. Young Multi-bend bus driven floorplanning. Search on Bibsonomy ISPD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF bus planning, floorplanning, VLSI CAD
32Hua Xiang 0001, Xiaoping Tang, Martin D. F. Wong Bus-driven floorplanning. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
32Yan Feng, Dinesh P. Mehta, Hannah Honghua Yang Constrained floorplanning using network flows. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
32Hai Zhou 0001, Jia Wang 0003 ACG-Adjacent Constraint Graph for General Floorplans. Search on Bibsonomy ICCD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
32Yan Feng, Dinesh P. Mehta, Hannah Honghua Yang Constrained "Modern" Floorplanning. Search on Bibsonomy ISPD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF floorplanning, network flow, rectilinear polygons
32Hua Xiang 0001, Xiaoping Tang, Martin D. F. Wong Bus-Driven Floorplanning. Search on Bibsonomy ICCAD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
32Shiyou Zhao, Kaushik Roy 0001, Cheng-Kok Koh Decoupling capacitance allocation and its application topower-supply noise-aware floorplanning. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
32Parthasarathi Dasgupta, Peichen Pan, Subhas C. Nandy, Bhargab B. Bhattacharya Monotone bipartitioning problem in a planar point set with applications to VLSI. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Complexity of algorithms, routing, very large scale integration (VLSI), partitioning, floorplanning
32Shiyou Zhao, Kaushik Roy 0001, Cheng-Kok Koh Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement. Search on Bibsonomy ASP-DAC/VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
32Abhishek Ranjan, Kia Bazargan, Seda Ogrenci, Majid Sarrafzadeh Fast floorplanning for effective prediction and construction. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
32Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu VLSI floorplanning with boundary constraints based on corner block list. Search on Bibsonomy ASP-DAC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
32Kia Bazargan, Samjung Kim, Majid Sarrafzadeh Nostradamus: a floorplanner of uncertain designs. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
32Parthasarathi Dasgupta, Susmita Sur-Kolay, Bhargab B. Bhattacharya A unified approach to topology generation and optimal sizing of floorplans. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
32Israel Koren, Zahava Koren Yield and Routing Objectives in Floorplanning. Search on Bibsonomy DFT The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
32Kazuhiko Eguchi, Junya Suzuki, Satoshi Yamane, Kenji Oshima An Application of Genetic Algorithms to Floorplanning of VLSI. Search on Bibsonomy Rough Sets and Current Trends in Computing The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
31Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee Noise-Direct: A Technique for Power Supply Noise Aware Floorplanning Using Microarchitecture Profiling. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF wire-length driven floorplan, noise-direct, power supply noise aware floorplanning, microarchitecture profiling, aggressive power saving techniques, power delivery network, power consumption reduction, self weighting, correlation weighting, force-directed floorplanning algorithm, power pin affinity, current consumption, di/dt control, supply-noise margin violations, clock-gating, microprocessor designers, power constraints, inductive noise, decoupling capacitances
31Zhenyu (Peter) Gu, Jia Wang 0003, Robert P. Dick, Hai Zhou 0001 Incremental exploration of the combined physical and behavioral design space. Search on Bibsonomy DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF high-level synthesis, floorplan, incremental
29Toshihiko Takahashi, Ryo Fujimaki, Youhei Inoue A (4n - 4)-Bit Representation of a Rectangular Drawing or Floorplan. Search on Bibsonomy COCOON The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
29Sarah E. Murphy, Erik DeBenedictis, Peter M. Kogge General floorplan for reversible quantum-dot cellular automata. Search on Bibsonomy Conf. Computing Frontiers The full citation details ... 2007 DBLP  DOI  BibTeX  RDF reversible computing, quantum-dot cellular automata
29Kristofer Vorwerk, Andrew A. Kennings, Doris T. Chen, Laleh Behjat Floorplan repair using dynamic whitespace management. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF VLSI, placement, floorplanning, legalization
29Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane FABSYN: floorplan-aware bus architecture synthesis. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
29Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hsien-Hsin S. Lee A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design. Search on Bibsonomy MICRO The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
29Jill H. Y. Law, Evangeline F. Y. Young, Royce L. S. Ching Block alignment in 3D floorplan using layered TCG. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF 3D floorplanning, block alignment
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