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Publication years (Num. hits)
1989-1998 (17) 1999-2000 (18) 2001-2003 (25) 2004 (15) 2005-2006 (36) 2007 (23) 2008-2009 (21) 2010-2013 (15) 2014-2018 (17) 2019-2023 (20)
Publication types (Num. hits)
article(55) incollection(1) inproceedings(151)
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The graphs summarize 104 occurrences of 82 keywords

Results
Found 207 publication records. Showing 207 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
132Ki-Seok Chung, Taewhan Kim, C. L. Liu 0001 G-vector: A New Model for Glitch Analysis in Logic Circuits. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF synthesis, power estimation, logic circuits, glitches
104Wieland Fischer, Berndt M. Gammel Masking at Gate Level in the Presence of Glitches. Search on Bibsonomy CHES The full citation details ... 2005 DBLP  DOI  BibTeX  RDF random masking, masked logic circuits, Cryptanalysis, side-channel attacks, DPA, power analysis, logic circuits, digital circuits, masking, glitches
80Stefan Mangard, Kai Schramm Pinpointing the Side-Channel Leakage of Masked AES Hardware Implementations. Search on Bibsonomy CHES The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Zero-Offset DPA, Zero-Input DPA, Delay Chains, AES, DPA, Masking, Glitches
78Anand Raghunathan, Sujit Dey, Niraj K. Jha Register transfer level power optimization with emphasis on glitch analysis and reduction. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
78Svetla Nikova, Vincent Rijmen, Martin Schläffer Secure Hardware Implementation of Non-linear Functions in the Presence of Glitches. Search on Bibsonomy ICISC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF non-linear functions, Noekeon, DPA, sharing, S-box, masking, glitches
76Xun Liu, Marios C. Papaefthymiou Incorporation of input glitches into power macromodeling. Search on Bibsonomy ISCAS (4) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
63Quang Dinh, Deming Chen, Martin D. F. Wong A routing approach to reduce glitches in low power FPGAs. Search on Bibsonomy ISPD The full citation details ... 2009 DBLP  DOI  BibTeX  RDF glitch reduction, path balancing, fpgas, routing, low power
50Lei Cheng 0001, Deming Chen, Martin D. F. Wong GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches. Search on Bibsonomy DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
50Svetla Nikova, Christian Rechberger, Vincent Rijmen Threshold Implementations Against Side-Channel Attacks and Glitches. Search on Bibsonomy ICICS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF side-channel attacks, secret sharing, Masking
41Katherine Shu-Min Li, Chung-Len Lee 0001, Chauchin Su, Jwu E. Chen IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection. Search on Bibsonomy J. Electron. Test. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF oscillation ring (OR) test scheme, open faults, crosstalk glitches, IEEE P1500, wrapper cell design, stuck-at faults, delay faults, SOC testing, interconnect test
39Zhimin Chen 0002, Syed Haider, Patrick Schaumont Side-Channel Leakage in Masked Circuits Caused by Higher-Order Circuit Effects. Search on Bibsonomy ISA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
39Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
39Tomasz S. Czajkowski, Stephen Dean Brown Using Negative Edge Triggered FFs to Reduce Glitching Power in FPGA Circuits. Search on Bibsonomy DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
39Jien-Chung Lo, Yu-Lun Wan, Eiji Fujiwara Transient Behavior of the Encoding/Decoding Circuits of Error Correcting Codes. Search on Bibsonomy DFT The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
39Stefan Mangard, Thomas Popp, Berndt M. Gammel Side-Channel Leakage of Masked CMOS Gates. Search on Bibsonomy CT-RSA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
39Michele Favalli "Victim Gate" Crosstalk Fault Model. Search on Bibsonomy DFT The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
39Anand Raghunathan, Sujit Dey, Niraj K. Jha High-level macro-modeling and estimation techniques for switching activity and power consumption. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
39Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi Glitch power minimization by selective gate freezing. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
37Flavio Carbognani, Felix Bürgin, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner Transmission Gates Combined With Level-Restoring CMOS Gates Reduce Glitches in Low-Power Low-Frequency Multipliers. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
37Benoit Catteau, Pieter Rombouts, Ludo Weyten A Digital Calibration Technique for the Correction of Glitches in High-Speed DAC's. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
27Ricardo Ferreira, Anne-Marie Trullemans, José C. Costa, José Monteiro 0001 Probabilistic Bottom-Up RTL Power Estimation. Search on Bibsonomy ISQED The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Register Tranfers Level, Power Estimation, Glitches, ZBDD
26Ahmad Al Zahrani, Andrew Bailey, Guoyuan Fu, Jia Di Glitch-free design for multi-threshold CMOS NCL circuits. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF asynchronous circuit, mtcmos, glitch, threshold gate, null convention logic
26Denis Réal, Cécile Canovas, Jessy Clédière, M'hamed Drissi, Frédéric Valette Defeating classical Hardware Countermeasures: a new processing for Side Channel Analysis. Search on Bibsonomy DATE The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
26Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal Graphical IDDQ Signatures Reduce Defect Level and Yield Loss. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
26Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton GlitchLess: an active glitch minimization technique for FPGAs. Search on Bibsonomy FPGA The full citation details ... 2007 DBLP  DOI  BibTeX  RDF field-programmable gate arrays, power minimization
26Hanif Fatemi, Shahin Nazarian, Massoud Pedram A Current-based Method for Short Circuit Power Calculation under Noisy Input Waveforms. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
26Kathi Fisler Two-Dimensional Regular Expressions for Compositional Bus Protocols. Search on Bibsonomy FMCAD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
26Natasa Miskov-Zivanov, Diana Marculescu Circuit Reliability Analysis Using Symbolic Techniques. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
26Fei Hu, Vishwani D. Agrawal Input-specific dynamic power optimization for VLSI circuits. Search on Bibsonomy ISLPED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF dynamic power optimization, glitch reduction, input specific
26Zhimin Chen, Yujie Zhou Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage. Search on Bibsonomy CHES The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Gate Level Masking, DRSL, Dual-Rail, Pre-charge, Side Channel Attacks, DPA
26Natasa Miskov-Zivanov, Diana Marculescu MARS-C: modeling and reduction of soft errors in combinational circuits. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF reliability symbolic techniques, SER
26Fei Hu, Vishwani D. Agrawal Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis. Search on Bibsonomy ICCD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
26Alex Gyure, Alireza Kasnavi, Sam C. Lo, Peivand F. Tehrani, William Shu, Mahmoud Shahram, Joddy W. Wang, Jindrich Zejda Noise Library Characterization for Large Capacity Static Noise Analysis Tools. Search on Bibsonomy ISQED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
26Stefan Mangard, Norbert Pramstaller, Elisabeth Oswald Successfully Attacking Masked AES Hardware Implementations. Search on Bibsonomy CHES The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
26Kai Chirca, Michael J. Schulte, John Glossner, Haoran Wang, Suman Mamidi, Pablo I. Balzola, Stamatis Vassiliadis A Static Low-Power, High-Performance 32-bit Carry Skip Adder. Search on Bibsonomy DSD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
26Katherine Shu-Min Li, Chung-Len Lee 0001, Chauchin Su, Jwu E. Chen A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI. Search on Bibsonomy Asian Test Symposium The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
26Michael J. Schulte, Kai Chirca, John Glossner, Haoran Wang, Suman Mamidi, Pablo I. Balzola, Stamatis Vassiliadis A Low-Power Carry Skip Adder with Fast Saturation. Search on Bibsonomy ASAP The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
26Carmen Baena Oliva, Jorge Juan-Chico, Manuel J. Bellido, Paulino Ruiz-de-Clavijo, Carlos Jesús Jiménez-Fernández, Manuel Valencia 0001 Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level. Search on Bibsonomy PATMOS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
26Henrik Eriksson, Per Larsson-Edefors Impact of Voltage Scaling on Glitch Power Consumption. Search on Bibsonomy PATMOS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
26Luca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi Glitch Power Minimization by Gate Freezing. Search on Bibsonomy DATE The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
26Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis Robust Sequential Fault Testing of Iterative Logic Arrays. Search on Bibsonomy VTS The full citation details ... 1997 DBLP  DOI  BibTeX  RDF Sequential Faults, Linear-testability, Fault Modeling, Automatic Test Generation, C-testability, Iterative Logic Arrays
26Rochit Rajsuman, Anura P. Jayasumana, Yashwant K. Malaiya CMOS Stuck-open Fault Detection Using Single Test Patterns. Search on Bibsonomy DAC The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
24Bingbin Liu, Jordan T. Ash, Surbhi Goel, Akshay Krishnamurthy, Cyril Zhang Exposing Attention Glitches with Flip-Flop Language Modeling. Search on Bibsonomy CoRR The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
24Elena Simona Apostol, Ciprian-Octavian Truica Efficient Machine Learning Ensemble Methods for Detecting Gravitational Wave Glitches in LIGO Time Series. Search on Bibsonomy CoRR The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
24Tiago S. Fernandes, Samuel J. Vieira, António Onofre, Juan Calderón Bustillo, Alejandro Torres-Forné, José A. Font Convolutional Neural Networks for the classification of glitches in gravitational-wave data streams. Search on Bibsonomy CoRR The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
24Mohammad Reza Taesiri, Tianjun Feng, Cor-Paul Bezemer, Anh Nguyen 0002 GlitchBench: Can large multimodal models detect video game glitches? Search on Bibsonomy CoRR The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
24Ahmad Faza, John Leth, Arnfinn Aas Eielsen Criterion for Sufficiently Large Dither Amplitude to Mitigate Non-linear Glitches. Search on Bibsonomy CCTA The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
24Ahmad Faza, John Leth, Arnfinn Aas Eielsen Mitigating Non-linear DAC Glitches Using Dither in Closed-loop Nano-positioning Applications. Search on Bibsonomy ACC The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
24Stanislav Lyakhov, Vincent Immler Analysis of Arbitrary Waveform Generation for Voltage Glitches. Search on Bibsonomy FDTC The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
24Bingbin Liu, Jordan T. Ash, Surbhi Goel, Akshay Krishnamurthy, Cyril Zhang Exposing Attention Glitches with Flip-Flop Language Modeling. Search on Bibsonomy NeurIPS The full citation details ... 2023 DBLP  BibTeX  RDF
24Elena Simona Apostol, Ciprian-Octavian Truica Efficient Machine Learning Ensemble Methods for Detecting Gravitational Wave Glitches in LIGO Time Series. Search on Bibsonomy ICCP The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
24Sivaramakrishnan Sankarapandian, Brian Kulis $β$-Annealed Variational Autoencoder for glitches. Search on Bibsonomy CoRR The full citation details ... 2021 DBLP  BibTeX  RDF
24Oscar Morales Chacon, J. Jacob Wikner, Atila Alvandpour, Liter Siek A digital switching scheme to reduce DAC glitches using code-dependent randomization. Search on Bibsonomy NorCAS The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
24Yanbin Li, Ming Tang 0002, Yuguang Li, Huanguo Zhang A pre-silicon logic level security verification flow for higher-order masking schemes against glitches on FPGAs. Search on Bibsonomy Integr. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
24Shlomo Engelberg, Osnat Keren Constructive Bounds on the Capacity of Parallel Asynchronous Skew-Free Channels With Glitches. Search on Bibsonomy IEEE Trans. Inf. Theory The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
24Arnfinn Aas Eielsen, John Leth, Andrew J. Fleming, Adrian G. Wills, Brett Ninness Large-Amplitude Dithering Mitigates Glitches in Digital-to-Analogue Converters. Search on Bibsonomy IEEE Trans. Signal Process. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
24Vittorio Zaccaria An F-algebra for analysing information leaks in the presence of glitches. Search on Bibsonomy IACR Cryptol. ePrint Arch. The full citation details ... 2020 DBLP  BibTeX  RDF
24Corey Brian Jackson, Carsten S. Østerlund, Kevin Crowston, Mahboobeh Harandi, Sarah Allen, Sara Bahaadini, Scotty Coughlin, Vicky Kalogera, Aggelos K. Katsaggelos, Shane L. Larson, Neda Rohani, Joshua R. Smith 0003, Laura Trouille, Michael Zevin Teaching citizen scientists to categorize glitches using machine learning guided training. Search on Bibsonomy Comput. Hum. Behav. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
24Tadahiro Nishiguchi Transcriptional Characteristics of Quadrant Glitches on Machined Surface - Influence of Tool Diameter and Feed Rate -. Search on Bibsonomy Int. J. Autom. Technol. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
24Carlos García Ling, Konrad Tollmar, Linus Gisslén Using Deep Convolutional Neural Networks to Detect Rendered Glitches in Video Games. Search on Bibsonomy AIIDE The full citation details ... 2020 DBLP  BibTeX  RDF
24Stefano Gualeni On the de-familiarizing and re-ontologizing effects of glitches and glitch-alikes. Search on Bibsonomy DiGRA Conference The full citation details ... 2019 DBLP  BibTeX  RDF
24Raphael Kim, Roland van Dierendonck, Stefan Poslad Moldy Ghosts and Yeasty Invasions: Glitches in Hybrid Bio-Digital Games. Search on Bibsonomy CHI Extended Abstracts The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
24Antti Tenhiälä, Manus Johnny Rungtusanatham, Jason W. Miller ERP System versus Stand-Alone Enterprise Applications in the Mitigation of Operational Glitches. Search on Bibsonomy Decis. Sci. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
24Rafael Nogueras, Carlos Cotta Analyzing Resilience to Computational Glitches in Island-Based Evolutionary Algorithms. Search on Bibsonomy PPSN (1) The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
24Roderick Bloem, Hannes Groß, Rinat Iusupov, Bettina Könighofer, Stefan Mangard, Johannes Winter Formal Verification of Masked Hardware Implementations in the Presence of Glitches. Search on Bibsonomy EUROCRYPT (2) The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
24Roderick Bloem, Hannes Groß, Rinat Iusupov, Bettina Könighofer, Stefan Mangard, Johannes Winter Formal Verification of Masked Hardware Implementations in the Presence of Glitches. Search on Bibsonomy IACR Cryptol. ePrint Arch. The full citation details ... 2017 DBLP  BibTeX  RDF
24Michael Meixner, Tobias G. Noll Accurate Estimation of CMOS Power Consumption Considering Glitches by Using Waveform Lookup. Search on Bibsonomy IEEE Trans. Circuits Syst. II Express Briefs The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
24Jungwoo Joh, Yezee Seo, Hoon-Kyu Kim, Taekyoung Kwon 0002 Glitch Recall: A Hardware Trojan Exploiting Natural Glitches in Logic Circuits. Search on Bibsonomy WISA The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
24Shlomo Engelberg, Osnat Keren Reliable Communication Across Parallel Asynchronous Channels with Glitches. Search on Bibsonomy ICMCTA The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
24Ciro D'Urso EXPERIENCE: Glitches in Databases, How to Ensure Data Quality by Outlier Detection Techniques. Search on Bibsonomy ACM J. Data Inf. Qual. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
24Herwig Wendt, Nicolas Dobigeon, Jean-Yves Tourneret, Mathieu Albinet, Christophe Goldstein, Nadia Karouche Detection and Correction of Glitches in a Multiplexed Multichannel Data Stream - Application to the MADRAS Instrument. Search on Bibsonomy IEEE Trans. Geosci. Remote. Sens. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
24Abdul Majeed Kottampara Kuppalath, Binsu J. Kailath Nonlinear PFD free of glitches and blind zone for a fast locking PLL with reduced reference spur. Search on Bibsonomy IEICE Electron. Express The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
24Charlotte A. L. Haley Mathematical physics: Glitches in time. Search on Bibsonomy Nat. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
24Yan Peng, Ian W. Jones, Mark R. Greenstreet Finding Glitches Using Formal Methods. Search on Bibsonomy ASYNC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
24Laure Berti-Équille, Ji Meng Loh, Tamraparni Dasu A masking index for quantifying hidden glitches. Search on Bibsonomy Knowl. Inf. Syst. The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
24Honorio Martín, Thomas Korak, Enrique San Millán, Michael Hutter Fault Attacks on STRNGs: Impact of Glitches, Temperature, and Underpowering on Randomness. Search on Bibsonomy IEEE Trans. Inf. Forensics Secur. The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
24Stephen Longfield Jr., Brittany Nkounkou, Rajit Manohar, Ross Tate Preventing glitches and short circuits in high-level self-timed chip specifications. Search on Bibsonomy PLDI The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
24Loïc Zussa, Jean-Max Dutertre, Jessy Clédière, Bruno Robisson Analysis of the fault injection mechanism related to negative and positive power supply glitches using an on-chip voltmeter. Search on Bibsonomy HOST The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
24Michael Meixner, Tobias G. Noll Limits of gate-level power estimation considering real delay effects and glitches. Search on Bibsonomy ISSoC The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
24Ji Meng Loh, Tamraparni Dasu Auditing data streams for correlated glitches. Search on Bibsonomy Int. J. Inf. Qual. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
24Tamraparni Dasu Data Glitches: Monsters in Your Data. Search on Bibsonomy Handbook of Data Quality The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
24Laure Berti-Équille, Ji Meng Loh, Tamraparni Dasu A Masking Index for Quantifying Hidden Glitches. Search on Bibsonomy ICDM The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
24Koichi Shimizu, Daisuke Suzuki, Tomomi Kasuya Glitch PUF: Extracting Information from Usually Unwanted Glitches. Search on Bibsonomy IEICE Trans. Fundam. Electron. Commun. Comput. Sci. The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
24Ryuta Sato Generation Mechanism of Quadrant Glitches and Compensation for it in Feed Drive Systems of NC Machine Tools. Search on Bibsonomy Int. J. Autom. Technol. The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
24Svetla Nikova, Vincent Rijmen, Martin Schläffer Secure Hardware Implementation of Nonlinear Functions in the Presence of Glitches. Search on Bibsonomy J. Cryptol. The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
24Emmanuel Prouff, Thomas Roche Higher-Order Glitches Free Implementation of the AES using Secure Multi-Party Computation. Search on Bibsonomy IACR Cryptol. ePrint Arch. The full citation details ... 2011 DBLP  BibTeX  RDF
24Ji Meng Loh, Tamraparni Dasu Auditing data streams for correlated glitches. Search on Bibsonomy ICIQ The full citation details ... 2011 DBLP  BibTeX  RDF
24Josep Balasch, Benedikt Gierlichs, Ingrid Verbauwhede An In-depth and Black-box Characterization of the Effects of Clock Glitches on 8-bit MCUs. Search on Bibsonomy FDTC The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
24Emmanuel Prouff, Thomas Roche Higher-Order Glitches Free Implementation of the AES Using Secure Multi-party Computation Protocols. Search on Bibsonomy CHES The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
24Da-Cheng Juan, Yu-Ting Chen, Ming-Chao Lee, Shih-Chieh Chang An Efficient Wake-Up Strategy Considering Spurious Glitches Phenomenon for Power Gating Designs. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
24Quang Dinh, Deming Chen, Martin D. F. Wong A Routing Approach to Reduce Glitches in Low Power FPGAs. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
24Xenophon Koufteros, Greg Rawski, Rupak Rauniar Organizational Integration for Product Development: The Effects on Glitches, On-Time Execution of Engineering Change Orders, and Market Success. Search on Bibsonomy Decis. Sci. The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
24Shehzad Hasan, Ajoy Kumar Palit, Walter Anheier Fault diagnosis of crosstalk induced glitches and delay faults. Search on Bibsonomy DDECS The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
24Shehzad Hasan, Ajoy Kumar Palit, Walter Anheier Test Pattern Generation and Compaction for Crosstalk Induced Glitches and Delay Faults. Search on Bibsonomy VLSI Design The full citation details ... 2010 DBLP  DOI  BibTeX  RDF Switching Windows, Test Set Compaction, Automatic Test Pattern Generation, Crosstalk Faults
24Monjur Alam, Santosh Ghosh, M. J. Mohan, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury, Indranil Sengupta 0001 Effect of glitches against masked AES S-box implementation and countermeasure. Search on Bibsonomy IET Inf. Secur. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
24Jins D. Alexander, Vishwani D. Agrawal Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations. Search on Bibsonomy ISVLSI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
24Amir Moradi 0001, Mahmoud Salmasizadeh, Mohammad Taghi Manzuri Shalmani On the Importance of the Number of Fanouts to Prevent the Glitches in DPA-Resistant Devices. Search on Bibsonomy CSICC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
24Kuan Jen Lin, Shan Chien Fang, Shih Hsien Yang, Cheng Chia Lo Overcoming glitches and dissipation timing skews in design of DPA-resistant cryptographic hardware. Search on Bibsonomy DATE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
24Minjin Zhang, Xiaowei Li 0001 Test Generation for Crosstalk Glitches Considering Multiple Coupling Effects. Search on Bibsonomy ATS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
24Yu-Ting Chen, Da-Cheng Juan, Ming-Chao Lee, Shih-Chieh Chang An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon. Search on Bibsonomy ICCAD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
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