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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 136 occurrences of 102 keywords
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Results
Found 244 publication records. Showing 244 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
144 | Mihai Sima, Sorin Cotofana, Jos T. J. van Eijndhoven, Stamatis Vassiliadis, Kees A. Vissers |
IEEE-Compliant IDCT on FPGA-Augmented TriMedia. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 39(3), pp. 195-212, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
inverse discrete cosine transform, field-programmable gate array, configurable computing, VLIW processor |
136 | Hui-Cheng Hsu, Kun-Bin Lee, Nelson Yen-Chung Chang, Tian-Sheuan Chang |
Architecture Design of Shape-Adaptive Discrete Cosine Transform and Its Inverse for MPEG-4 Video Coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. Video Technol. ![In: IEEE Trans. Circuits Syst. Video Technol. 18(3), pp. 375-386, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
117 | Lijie Liu, Trac D. Tran |
Rate-Distortion Analysis of Multiplierless Lifting-based IDCT Approximations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CISS ![In: Proceedings of the 41st Annual Conference on Information Sciences and Systems, CISS 2007, 14-16 March 2007, Johns Hopkins University, Department of Electrical Engineering, Baltimore, MD, USA, pp. 720-725, 2007, IEEE, 1-4244-1037-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
117 | Jiun-In Guo, Rei-Chin Ju, Jia-Wei Chen |
An efficient 2-D DCT/IDCT core design using cyclic convolution and adder-based realization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. Video Technol. ![In: IEEE Trans. Circuits Syst. Video Technol. 14(4), pp. 416-428, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
113 | Jiun-In Guo, Jui-Cheng Yen |
An Efficient IDCT Processor Design for HDTV Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 33(1-2), pp. 147-155, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
inverse discrete cosine transform (IDCT), adder-based implementation, common sub-expression sharing, HDTV, cyclic convolution |
99 | Tze-Yun Sung, Yaw-Shih Shieh, Chun-Wang Yu, Hsi-Chin Hsin |
High-Efficiency and Low-Power Architectures for 2-D DCT and IDCT Based on CORDIC Rotation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDCAT ![In: Seventh International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT 2006), 4-7 December 2006, Taipei, Taiwan, pp. 191-196, 2006, IEEE Computer Society, 0-7695-2736-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
low-power, DCT, CORDIC, IDCT |
95 | Mihai Sima, Sorin Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers |
A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Embedded Processor Design Challenges ![In: Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation - SAMOS, pp. 224-241, 2002, Springer, 3-540-43322-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
91 | Tze-Yun Sung, Mao-Jen Sun, Yaw-Shih Shieh, Hsi-Chin Hsin |
Memory-Efficiency and High-Speed Architectures for Forward and Inverse DCT with Multiplierless Operation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PSIVT ![In: Advances in Image and Video Technology, First Pacific Rim Symposium, PSIVT 2006, Hsinchu, Taiwan, December 10-13, 2006, Proceedings, pp. 802-811, 2006, Springer, 3-540-68297-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
parallel-pipelined architecture, memory-efficiency, DCT, high-performances, IDCT |
90 | Dae Won Kim, Taek Won Kwon, Jung Min Seo, Jae Kun Yu, Kyu Lee, Jung Hee Suk, Jun Rim Choi |
A compatible DCT/IDCT architecture using hardwired distributed arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 457-460, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
82 | Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin |
Inverse discrete cosine transform architecture exploiting sparseness and symmetry properties. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. Video Technol. ![In: IEEE Trans. Circuits Syst. Video Technol. 16(5), pp. 655-662, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
82 | Mihai Sima, Sorin Dan Cotofana, Stamatis Vassiliadis, Jos T. J. van Eijndhoven, Kees A. Vissers |
Pel reconstruction on FPGA-augmented TriMedia. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 12(6), pp. 622-635, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
82 | Kibum Suh, Seongmo Park, Seongmin Kim, Bontae Koo, Igkyun Kim, Kyungsoo Kim, Hanjin Cho |
An efficient architecture of DCTQ module in MPEG-4 video codec. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 777-780, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
82 | Kibum Suh, Kyung Yuk Min, Kyeounsoo Kim, Jong-Seog Koh, Jong-Wha Chong |
A design of DPCM hybrid coding loop using single 1-D DCT in MPEG-2 video encoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 279-282, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
76 | Yuriy A. Reznik, De Hsu, Prasanjit Panda, Brijesh Pillai |
Low-Drift Fixed-Point 8X8 IDCT Approximationwith 8-Bit Transform Factors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP (6) ![In: Proceedings of the International Conference on Image Processing, ICIP 2007, September 16-19, 2007, San Antonio, Texas, USA, pp. 81-84, 2007, IEEE, 978-1-4244-1436-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
72 | Gustavo A. Ruiz, Juan A. Michell, Angel M. Burón |
High Throughput Parallel-Pipeline 2-D DCT/IDCT Processor Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 45(3), pp. 161-175, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
inverse discrete cosine transform (IDCT), row column decomposition, parallel pipelined architectures, very large scale integration (VLSI), image compression, discrete cosine transform (DCT) |
68 | Honggang Qi, Wen Gao 0001 |
High-Accuracy and Low-Complexity Fixed-Point Inverse Discrete Cosine Transform Based on AAN's Fast Algortihm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 533-536, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
64 | Bret Stott, Dave Johnson 0003, Venkatesh Akella |
Asynchronous 2-D discrete cosine transform core processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 380-385, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
asynchronous 2-D discrete cosine transform core processor, self-timed design, CCITT compatible asynchronous DCT/IDCT processor, two-phase transition signaling, bounded delay approach, Sutherland's micropipeline, custom techniques, 2 /spl mu/ SCMOS technology, delays, discrete cosine transforms, digital signal processing chips, CMOS digital integrated circuits, standard cell, 2 micron |
62 | Lodewijk T. Smit, Gerard K. Rauwerda, Albert Molderink, Pascal T. Wolkotte, Gerard J. M. Smit |
Implementation of a 2-D 8x8 IDCT on the Reconfigurable Montium Core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: FPL 2007, International Conference on Field Programmable Logic and Applications, Amsterdam, The Netherlands, 27-29 August 2007, pp. 562-566, 2007, IEEE, 1-4244-1060-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
62 | João Manuel R. S. Tavares, António Silva, Antonio Navarro 0002 |
H.263 Video Codec Performance with a Fast 8×8 Integer IDCT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICME ![In: Proceedings of the 2006 IEEE International Conference on Multimedia and Expo, ICME 2006, July 9-12 2006, Toronto, Ontario, Canada, pp. 2009-2012, 2006, IEEE Computer Society, 1-4244-0367-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
62 | Kuan-Hung Chen, Jiun-In Guo, Jinn-Shyan Wang, Ching-Wei Yeh, Jia-Wei Chen |
An Energy-Aware IP Core Design for the Variable-Length DCT/IDCT Targeting at MPEG4 Shape-Adaptive Transforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. Video Technol. ![In: IEEE Trans. Circuits Syst. Video Technol. 15(5), pp. 704-715, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
62 | Bo Fang, Guobin Shen, Shipeng Li 0001, Huifang Chen |
Techniques for efficient DCT/IDCT implementation on generic GPU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1126-1129, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
62 | Nathaniel J. August, Dong Sam Ha |
Low power design of DCT and IDCT for low bit rate video codecs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Multim. ![In: IEEE Trans. Multim. 6(3), pp. 414-422, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
62 | Rohini Krishnan, Om Prakash Gangwal, Jos T. J. van Eijndhoven, Anshul Kumar |
Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 16th International Conference on VLSI Design (VLSI Design 2003), 4-8 January 2003, New Delhi, India, pp. 177-182, 2003, IEEE Computer Society, 0-7695-1868-0. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
62 | Hyesook Lim, Changhoon Yim, Earl E. Swartzlander Jr. |
Finite Word-Length Effects Of An Unified Systolic Array For 2-D DCT/IDCT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1996 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '96), August 19-23, 1996, Chicago, IL , USA, pp. 35-, 1996, IEEE Computer Society, 0-8186-7542-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
finite word-length effects, unified systolic array, fixed-point error analysis, inverse discrete cosine transform, fixed-point rounding-errors, minimum word-length, fixed-point error, discrete cosine transforms, discrete cosine transform, systolic arrays, digital simulation, error analysis, simulation results, roundoff errors, closed form expressions, truncation-errors |
62 | Feng Zhou, Peter Kornerup |
High Speed DCT/IDCT Using a Pipelined CORDIC Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 12th Symposium on Computer Arithmetic (ARITH-12 '95), July 19-21, 1995, Bath, England, UK, pp. 180-187, 1995, IEEE Computer Society, 0-8186-7089-4. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
54 | Woong Hwangbo, Jaemoon Kim, Chong-Min Kyung |
A High-Performance 2-D Inverse Transform Architecture for the H.264/AVC Decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1613-1616, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
54 | Qionghai Dai, Xinjian Chen 0002, Chuang Lin 0002 |
Fast algorithms for multidimensional DCT-to-DCT computation between a block and its associated subblocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 53(8-2), pp. 3219-3225, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
49 | M. F. Mansour |
On the odd-DFT and its applications to DCT/IDCT computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 54(7), pp. 2819-2822, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
49 | Shyue-Kung Lu, Ting-Yu Chen, Wei-Yuan Liu |
Efficient Built-In Self-Test Schemes for Video Coding Cores: a Case Study on DCT/IDCT Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 12th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2006), 18-20 December, 2006, University of California, Riverside, USA, pp. 97-104, 2006, IEEE Computer Society, 0-7695-2724-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
49 | Gustavo A. Ruiz, Juan A. Michell, Angel M. Burón |
High throughput 2D DCT/IDCT processor for video coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP (3) ![In: Proceedings of the 2005 International Conference on Image Processing, ICIP 2005, Genoa, Italy, September 11-14, 2005, pp. 1036-1039, 2005, IEEE, 0-7803-9134-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
49 | Yi Yang, Chunyan Wang 0004, M. Omair Ahmad, M. N. S. Swamy |
An FPGA implementation of an on-line radix-4 CORDIC 2-D IDCT core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 763-766, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
49 | Minyi Fu, Vassil S. Dimitrov, Graham A. Jullien |
An efficient technique for error-free algebraic-integer encoding for high performance implementation of the DCT and IDCT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 906-909, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
49 | Dave Johnson 0003, Venkatesh Akella, Bret Stott |
Micropipelined asynchronous discrete cosine transform (DCT/IDCT) processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 6(4), pp. 731-740, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
49 | Claus Schneider, Martin Kayss, Thomas Hollstein, Jürgen Deicke |
From Algorithms to Hardware Architectures: A Comparison of Regular and Irregular Structured IDCT Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 186-190, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
45 | Thomas Tziortzios, Stavros Dokouzyannis |
A Fast 8*8 2D IDCT Architecture, Avoiding Zero Transformed Coefficients. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IIH-MSP ![In: Sixth International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2010), Darmstadt, Germany, 15-17 October, 2010, Proceedings, pp. 216-219, 2010, IEEE Computer Society, 978-1-4244-8378-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
2D IDCT, forward mapping, image processing |
43 | Chaouki Diab, Mohamad Oueidat, Rémy Prost |
A new IDCT-DFT relationship reducing the IDCT computational cost. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Signal Process. ![In: IEEE Trans. Signal Process. 50(7), pp. 1681-1684, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
41 | Yanmei Qu, Shunliang Mei, Yun He |
A Cost-effective VLD Architecture for MPEG-2 and AVS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 52(1), pp. 95-109, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
CA-2D-VLC, VLD, inverse quantisation, MPEG-2, AVS, VLC |
41 | Jiun-In Guo, Jia-Wei Chen, Han-Chen Chen |
A new 2-D 8×8 DCT/IDT core design using group distributed arithmetic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 752-755, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
41 | Jiun-In Guo |
A low cost 2-D inverse discrete cosine transform design for image compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: Proceedings of the 2001 International Symposium on Circuits and Systems, ISCAS 2001, Sydney, Australia, May 6-9, 2001, pp. 658-661, 2001, IEEE, 0-7803-6685-9. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
41 | Yoichi Katayama, Toshiaki Kitsuki, Yasushi Ooi |
A Block Processing Unit in a Single-Chip MPEG-2 Video Encoder LSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 22(1), pp. 59-64, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
37 | Andrew Kinane, Noel E. O'Connor |
Energy-efficient Hardware Accelerators for the SA-DCT and Its Inverse. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 47(2), pp. 127-152, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
shape adaptive DCT/IDCT, low power, MPEG-4, hardware acceleration, video objects |
37 | Armando Sánchez-Peña, Pedro P. Carballo, Luz García 0001, Antonio Núñez |
VIPACES, Verification Interface Primitives for the Development of AXI Compliant Elements and Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 305-312, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
AMBA 3 AXI, VIPACES, Virtual Components, Verification, Test, System-on-Chip (SoC), IP, DCT, Emulation, SystemC, Environment, TLM, IDCT, VIP |
37 | Marco Antonio Dal Poz, Jose Edinson Aedo Cobo, Wilhelmus A. M. Van Noije, Marcelo Knörich Zuffo |
A Simple RISC Microprocessor Core Designed for Digital Set-Top-Box Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 12th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2000), 10-12 July 2000, Boston, MA, USA, pp. 35-, 2000, IEEE Computer Society, 0-7695-0716-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
FPGA, VHDL, Reconfigurable Computing, Microprocessor, MPEG, RISC, Co-Design, Instruction Set, HDTV, Set-Top-Box, iDCT, cable TV |
37 | Yi-Shin Tung, Chia-Chiang Ho, Ja-Ling Wu |
MMX-Based DCT and MC Algorithms for Real-Time Pure Software MPEG Decoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICMCS, Vol. 1 ![In: IEEE International Conference on Multimedia Computing and Systems, ICMCS 1999, Florence, Italy, June 7-11, 1999. Volume I, pp. 357-362, 1999, IEEE Computer Society, 0-7695-0253-9. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Pattern-Based IDCT, MPEG, Video Compression, MMX |
35 | Khan Wahid, Vassil S. Dimitrov, Graham A. Jullien |
Error-Free Computation of 8x8 2-D DCT and IDCT Using Two-Dimensional Algebraic Integer Quantization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 27-29 June 2005, Cape Cod, MA, USA, pp. 214-221, 2005, IEEE Computer Society, 0-7695-2366-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
35 | Peter Lee 0001 |
An evaluation of a hybrid-logarithmic number system DCT/IDCT algorithm [image compression applications]. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 4863-4866, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
35 | Takashi Miyazaki, Takao Nishitani, Masato Edahiro, Ikuko Ono, Kaoru Mitsuhashi |
DCT/IDCT processor for HDTV developed with dsp silicon compiler. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 5(2-3), pp. 151-158, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
27 | Veera Papirla, Aarul Jain, Chaitali Chakrabarti |
Low power robust signal processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 303-306, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
algorithmic noise tolerance, redundant binary arithmetic, soft DSP |
27 | Zhu Chen, Moon Ho Lee, Chang-Joo Kim |
Fast Hybrid DFT/DCT Architecture for OFDM in Cognitive Radio System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FGCN (1) ![In: Future Generation Communication and Networking, FGCN 2007, Ramada Plaza Jeju, Jeju-Island, Korea, December 6-8, 2007, Proceedings, pp. 301-306, 2007, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
27 | Javier D. Bruguera, Roberto R. Osorio |
A Unified Architecture for H.264 Multiple Block-Size DCT with Fast and Low Cost Quantization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August - 1 September 2006, Dubrovnik, Croatia, pp. 407-414, 2006, IEEE Computer Society, 0-7695-2609-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Hanli Wang, Sam Kwong, Chi-Wah Kok |
Fast video coding based on Gaussian model of DCT coefficients. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Alex Ginzburg, Evgeny Kaminsky, Yuri Abramov, Ofer Hadar |
DCT-Domain Coder for Digital Video Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITRE ![In: ITRE 2006 - 4th International Conference on Information Technology: Research and Education, October 17-18, 2006, Tel Aviv, Israel, Proceedings, pp. 110-114, 2006, IEEE, 1-4244-0858-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin |
High Performance Array Processor for Video Decoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), New Frontiers in VLSI Design, 11-12 May 2005, Tampa, FL, USA, pp. 28-33, 2005, IEEE Computer Society, 0-7695-2365-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Stephan Gatzka, Christian Hochberger |
On the Scope of Hardware Acceleration of Reconfigurable Processors in Mobile Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS ![In: 38th Hawaii International Conference on System Sciences (HICSS-38 2005), CD-ROM / Abstracts Proceedings, 3-6 January 2005, Big Island, HI, USA, 2005, IEEE Computer Society, 0-7695-2268-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Jianmin Jiang, Ying Weng |
Video extraction for fast content access to MPEG compressed videos. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. Video Technol. ![In: IEEE Trans. Circuits Syst. Video Technol. 14(5), pp. 595-605, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Danian Gong, Yun He, Zhigang Cao |
New cost-effective VLSI implementation of a 2-D discrete cosine transform and its inverse. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. Video Technol. ![In: IEEE Trans. Circuits Syst. Video Technol. 14(4), pp. 405-415, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Matjaz Verderber, Andrej Zemva, Damjan Lampret |
HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 20238-20243, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Matjaz Verderber, Andrej Zemva, Andrej Trost |
HW/SW Codesign of the MPEG-2 Video Decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 22-26 April 2003, Nice, France, CD-ROM/Abstracts Proceedings, pp. 179, 2003, IEEE Computer Society, 0-7695-1926-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Kunihiro Yamada, Yukihisa Naoe, Masanori Kojima, Tadanori Mizuno |
A New MPEG-2 Solution Using a 2nd ALU in the RISC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KES ![In: Knowledge-Based Intelligent Information and Engineering Systems, 7th International Conference, KES 2003, Oxford, UK, September 3-5, 2003, Proceedings, Part II, pp. 734-740, 2003, Springer, 3-540-40804-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Huesung Kim, Arun K. Somani, Akhilesh Tyagi |
A reconfigurable multi-function computing cache architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2000, Monterey, CA, USA, February 10-11, 2000, pp. 85-94, 2000, ACM, 1-58113-193-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
27 | Kyeounsoo Kim, Peter A. Beerel, Youpyo Hong |
An asynchronous matrix-vector multiplier for discrete cosine transform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000, Rapallo, Italy, July 25-27, 2000, pp. 256-261, 2000, ACM, 1-58113-190-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
asynchronous matrix-vector multiplier, discrete cosine transform |
27 | Jarno K. Tanskanen, Jarkko Niittylahti |
Parallel Memories in Video Encoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Data Compression Conference ![In: Data Compression Conference, DCC 1999, Snowbird, Utah, USA, March 29-31, 1999., pp. 552, 1999, IEEE Computer Society, 0-7695-0096-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
23 | Yifeng Qiu, Wael M. Badawy, Robert D. Turney |
An Architecture for Programmable Multi-core IP Accelerated Platform with an Advanced Application of H.264 Codec Implementation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 57(2), pp. 123-137, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Virtual socket, DCT/Q, IDCT/Q-1, Deblocking, Architecture, Motion estimation, Multi-core, H.264/AVC, Accelerator, Video codec, CAVLC |
23 | Chao-Jang Hwang, Chih-Tung Lin, Shi-Jinn Horng |
Implementation of Different Function Units Using Flexible and Reconfigurable Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITNG ![In: Sixth International Conference on Information Technology: New Generations, ITNG 2009, Las Vegas, Nevada, USA, 27-29 April 2009, pp. 84-89, 2009, IEEE Computer Society, 978-0-7695-3596-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Image Processing, DCT, IDCT |
23 | Zhenyu Wu, Hongyang Yu, Bin Tang, Hong Hu |
Performance Evaluation of Transcoding Algorithms for MPEG-2 to AVS-P2. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IIH-MSP ![In: Second International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2006), Pasadena, California, USA, December 18-20, 2006, Proceedings, pp. 643-646, 2006, IEEE Computer Society, 0-7695-2745-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
AVS-P2(Audio Video Standard Part2: video), re-quantization, IT(integer transform), IIT(inverse integer transform), IDCT(inverse DCT), transcoding, MPEG-2 |
23 | Osvaldo Colavin, Davide Rizzo |
A scalable wide-issue clustered VLIW with a reconfigurable interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, CASES 2003, San Jose, California, USA, October 30 - November 1, 2003, pp. 148-158, 2003, ACM, 1-58113-676-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
clustered VLIW, reconfigurable co-processor (RCP), modulo scheduling, IDCT |
23 | Carla L. Pagliari, Tim J. Dennis |
Stereo disparity computation in the DCT domain using genetic algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP (3) ![In: Proceedings 1997 International Conference on Image Processing, ICIP '97, Santa Barbara, California, USA, October 26-29, 1997, pp. 256-259, 1997, IEEE Computer Society, 0-8186-8183-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
stereo disparity computation, image block, estimated disparity map, AC coefficients, DC component, intensity similarity measure, biologically inspired optimisation, genetic algorithms, discrete cosine transform, camera, stereo image processing, stereo matching, correspondence problem, DCT coefficients, statistical properties, inverse transform, IDCT, DCT domain, image domain |
23 | Marco Mattavelli, Sylvain Brunetton, Daniel Mlynek |
Computational Graceful Degradation for Video Sequence Decoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP (1) ![In: Proceedings 1997 International Conference on Image Processing, ICIP '97, Santa Barbara, California, USA, October 26-29, 1997, pp. 330-333, 1997, IEEE Computer Society, 0-8186-8183-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
computational graceful degradation, video sequence decoding, software based video decoders, dedicated hardware real time systems, video/audio decoders, video compression standards, video/audio bitstreams processing, multimedia processors, compressed video sequences, H.263 video compression standard, video processor platform, interfaces, video coding, simulation results, real-time performance, main memory, IDCT, hardware platform |
22 | Mojtaba Mahdavi 0001 |
Towards Low-Complexity, Fully Parallel and Flexible Hardware Realization of DCT/IDCT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSPCS ![In: 16th International Conference on Signal Processing and Communication System, ICSPCS 2023, Bydgoszcz, Poland, September 6-8, 2023, pp. 1-7, 2023, IEEE, 979-8-3503-3351-0. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
22 | Zhiwei Zhou, Zhongliang Pan |
Effective Hardware Accelerator for 2D DCT/IDCT Using Improved Loeffler Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 10, pp. 11011-11020, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Yadwinder Singh, Lakhwinder Kaur, Nirvair Neeru |
A New Improved Obstacle Detection Framework Using IDCT and CNN to Assist Visually Impaired Persons in an Outdoor Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wirel. Pers. Commun. ![In: Wirel. Pers. Commun. 124(4), pp. 3685-3702, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
22 | Arunachalam Venkatesan, Alex Noel Joseph Raj, Deepika Selvaraj |
Performance Improvement of Vector-Radix Decimation-in-Frequency 3D-DCT/IDCT Using Variable Word Length. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Circuits Syst. Signal Process. ![In: Circuits Syst. Signal Process. 40(4), pp. 1818-1831, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
22 | Yifan Wang, Zhanxuan Mei, Chia-Yang Tsai, Ioannis Katsavounidis, C.-C. Jay Kuo |
A Machine Learning Approach to Optimal Inverse Discrete Cosine Transform (IDCT) Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2102.00502, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP BibTeX RDF |
|
22 | Shensheng Tang, Monali Sinare, Yi Zheng |
Design, optimisation and implementation of a DCT/IDCT-based image processing system on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Comput. Appl. Technol. ![In: Int. J. Comput. Appl. Technol. 67(4), pp. 303-323, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
22 | Barmak Honarvar Shakibaei Asli, Jan Flusser, Yifan Zhao 0001, John Ahmet Erkoyuncu, Kajoli Banerjee Krishnan, Yasin Farrokhi, Rajkumar Roy |
Ultrasound Image Filtering and Reconstruction Using DCT/IDCT Filter Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 8, pp. 141342-141357, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Dezhi An, Shengcai Zhang, Jun Lu, Yan Li |
Efficient and Privacy-Preserving Outsourcing of 2D-DCT and 2D-IDCT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Wirel. Commun. Mob. Comput. ![In: Wirel. Commun. Mob. Comput. 2020, pp. 8892838:1-8892838:9, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Debasish Mukherjee, Susanta Mukhopadhyay |
Hardware Efficient Architecture for 2D DCT and IDCT Using Taylor-Series Expansion of Trigonometric Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. Video Technol. ![In: IEEE Trans. Circuits Syst. Video Technol. 30(8), pp. 2723-2735, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Ahmed Ben Atitallah, Manel Kammoun, Karim M. A. Ali, Rabie Ben Atitallah |
An FPGA comparative study of high-level and low-level combined designs for HEVC intra, inverse quantization, and IDCT/IDST 2D modules. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 48(8), pp. 1274-1290, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Ashish Singhadia, Meghan Mamillapalli, Indrajit Chakrabarti |
Hardware-Efficient 2D-DCT/IDCT Architecture for Portable HEVC-Compliant Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Consumer Electron. ![In: IEEE Trans. Consumer Electron. 66(3), pp. 203-212, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Barmak Honarvar Shakibaei Asli, Jan Flusser, Yifan Zhao 0001, John Ahmet Erkoyuncu, Rajkumar Roy |
DCT/IDCT Filter Design for Ultrasound Image Filtering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPR ![In: 25th International Conference on Pattern Recognition, ICPR 2020, Virtual Event / Milan, Italy, January 10-15, 2021, pp. 1804-1811, 2020, IEEE, 978-1-7281-8808-9. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Martin Johnson, Daniel P. Playne |
A Fast and Concise Parallel Implementation of the 8x8 2D IDCT using Halide. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBAC-PAD ![In: 32nd IEEE International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2020, Porto, Portugal, September 9-11, 2020, pp. 167-174, 2020, IEEE, 978-1-7281-9924-5. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
22 | En-Pei Wu, Trong-An Bui, Kermit Chen, Pei-Jun Lee |
Hardware Implementation of DCT/IDCT sharing for HEVC/MPEG Video Coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCE ![In: 2020 IEEE International Conference on Consumer Electronics (ICCE), Las Vegas, NV, USA, January 4-6, 2020, pp. 1-3, 2020, IEEE, 978-1-7281-5186-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
22 | Jianfeng Zhang, Wei Shi, Li Zhou, Rui Gong, Lei Wang 0011, Hongwei Zhou |
A Low-Power and High-PSNR Unified DCT/IDCT Architecture Based on EARC and Enhanced Scale Factor Approximation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 7, pp. 165684-165691, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Subiman Chatterjee, Kishor Sarawadekar |
WHT and Matrix Decomposition-Based Approximated IDCT Architecture for HEVC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 66-II(6), pp. 1043-1047, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
22 | He Ma, Yi Zuo, Tieshan Li, C. L. Philip Chen, Junxia Liu |
A Euclidean metric based voice feature extraction method using IDCT cepstrum coefficient. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SMC ![In: 2019 IEEE International Conference on Systems, Man and Cybernetics, SMC 2019, Bari, Italy, October 6-9, 2019, pp. 187-192, 2019, IEEE, 978-1-7281-4569-3. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Genwei Tang, Ming-e Jing, Xiaoyang Zeng, Yibo Fan |
A 32-Pixel IDCT-Adapted HEVC Intra Prediction VLSI Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2019, Sapporo, Japan, May 26-29, 2019, pp. 1-5, 2019, IEEE, 978-1-7281-0397-6. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
22 | Mohammad Ali Pourabed, Sajjad Nouri, Jari Nurmi |
Design and Implementation of 2D IDCT/IDST-Specific Accelerator on Heterogeneous Multicore Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NORCAS ![In: 2018 IEEE Nordic Circuits and Systems Conference, NORCAS 2018: NORCHIP and International Symposium of System-on-Chip (SoC), Tallinn, Estonia, October 30-31, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-7656-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
22 | Luciano A. Braatz, Daniel Palomino 0001, Luciano Volcan Agostini, Bruno Zatt, Marcelo Schiavon Porto |
Low-Power HEVC 1-D IDCT Hardware Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: 31st Symposium on Integrated Circuits and Systems Design, SBCCI 2018, Bento Gonçalves, RS, Brazil, August 27-31, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-7431-4. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
22 | Doru-Florin Chiper, Laura-Teodora Cotorobai |
A Unified VLSI architecture for 1D IDCT and IDST based on pseudo-band correlations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECAI ![In: 2018 10th International Conference on Electronics, Computers and Artificial Intelligence (ECAI), Iasi, Romania, June 28-30, 2018, pp. 1-5, 2018, IEEE, 978-1-5386-4901-5. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
22 | Yuan-Ho Chen, Yi-Fan Ko |
High-throughput IDCT architecture for high-efficiency video coding (HEVC). ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Circuit Theory Appl. ![In: Int. J. Circuit Theory Appl. 45(12), pp. 2260-2269, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
22 | Vili Viitamäki, Panu Sjovall, Jarno Vanne, Timo D. Hämäläinen |
High-level synthesized 2-D IDCT/IDST implementation for HEVC codecs on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2017, Baltimore, MD, USA, May 28-31, 2017, pp. 1-4, 2017, IEEE, 978-1-4673-6853-7. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
22 | Mingyu Wang, Fang Wang, Shaojun Wei, Zhaolin Li |
A pipelined area-efficient and high-speed reconfigurable processor for floating-point FFT/IFFT and DCT/IDCT computations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 47, pp. 19-30, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Liang Hong, Wei-Feng He, Guanghui He, Zhigang Mao |
Area-efficient HEVC IDCT/IDST architecture for 8K × 4K video decoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 13(6), pp. 20160019, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Kaili Yao, Ronggang Wang, Zhenyu Wang 0002, Wenmin Wang, Wen Gao 0001 |
A Fast and Lossless IDCT Design for AVS2 Codec. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BigMM ![In: IEEE Second International Conference on Multimedia Big Data, BigMM 2016, Taipei, Taiwan, April 20-22, 2016, pp. 241-245, 2016, IEEE Computer Society, 978-1-5090-2179-6. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Yiliu Feng, Jianfeng Zhang, Hengzhu Liu |
A Novel Low-Power and High-PSNR Architecture Based on ARC for DCT/IDCT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NCCET ![In: Computer Engineering and Technology - 20th CCF Conference, NCCET 2016, Xi'an, China, August 10-12, 2016, Revised Selected Papers, pp. 55-68, 2016, Springer, 978-981-10-3158-8. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
22 | Yibo Fan, Leilei Huang, Yufeng Bai, Xiaoyang Zeng |
A Parallel-Access Mapping Method for the Data Exchange Buffers Around DCT/IDCT in HEVC Encoders Based on Single-Port SRAMs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 62-II(12), pp. 1139-1143, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
22 | Ahmed Kilany, Maher Abdelrasoul, Ahmed Shalaby 0001, Mohammed Sharaf Sayed |
A reconfigurable 2-D IDCT architecture for HEVC encoder/decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICM ![In: 27th International Conference on Microelectronics, ICM 2015, Casablanca, Morocco, December 20-23, 2015, pp. 242-245, 2015, IEEE, 978-1-4673-8759-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
22 | Ruhan A. Conceição, Andrio Araujo, Marcelo Schiavon Porto, Bruno Zatt, Luciano Volcan Agostini |
Hardware design of fast HEVC 2-D IDCT targeting real-time UHD 4K applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LASCAS ![In: IEEE 6th Latin American Symposium on Circuits & Systems, LASCAS 2015, Montevideo, Uruguay, February 24-27, 2015, pp. 1-4, 2015, IEEE, 978-1-4799-8332-2. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
22 | Jianfeng Zhang, Paul Chow, Hengzhu Liu |
FPGA implementation of low-power and high-PSNR DCT/IDCT architecture based on adaptive recoding CORDIC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPT ![In: 2015 International Conference on Field Programmable Technology, FPT 2015, Queenstown, New Zealand, December 7-9, 2015, pp. 128-135, 2015, IEEE, 978-1-4673-9091-0. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
22 | Qing Shang, Yibo Fan, Weiwei Shen, Sha Shen, Xiaoyang Zeng |
Single-Port SRAM-Based Transpose Memory With Diagonal Data Mapping for Large Size 2-D DCT/IDCT. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 22(11), pp. 2422-2426, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
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