Search results for "MTCMOS"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
126	Hyo-Sig Won, Kyo-Sun Kim, Kwang-Ok Jeong, Ki-Tae Park, Kyu-Myung Choi, Jeong-Taek Kong	An MTCMOS design methodology and its application to mobile computing.	ISLPED	2003	DBLP DOI BibTeX RDF	CPFF, low power, leakage current, CCS, MTCMOS
119	Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram	Sizing and placement of charge recycling transistors in MTCMOS circuits.	ICCAD	2007	DBLP DOI BibTeX RDF
110	Chanseok Hwang, Peng Rong, Massoud Pedram	Sleep transistor distribution in row-based MTCMOS designs.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	leakage minimization, placement, MTCMOS
103	Zhiyu Liu, Volkan Kursun	Charge Recycling MTCMOS for Low Energy Active/Sleep Mode Transitions.	ISCAS	2007	DBLP DOI BibTeX RDF
103	Zhiyu Liu, Volkan Kursun	Charge Recycling Between Virtual Power and Ground Lines for Low Energy MTCMOS.	ISQED	2007	DBLP DOI BibTeX RDF	Multi-threshold voltage CMOS, gated power, gated ground, sleep switch, subthreshold leakage, charge recycling
102	Nikhil Jayakumar, Sunil P. Khatri	An ASIC design methodology with predictably low leakage, using leakage-immune standard cells.	ISLPED	2003	DBLP DOI BibTeX RDF	standby current, leakage current, standard cells, MTCMOS
101	Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry	A Timing-Driven Algorithm for Leakage Reduction in MTCMOS FPGAs.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.13 micron, timing-driven algorithm, MTCMOS FPGA, MTCMOS CAD methodology, subthreshold leakage power reduction, nanometer FPGA, circuit timing information, CMOS process
94	Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram	Charge recycling in MTCMOS circuits: concept and analysis.	DAC	2006	DBLP DOI BibTeX RDF	low power design, MTCMOS, charge recycling
88	Charbel J. Akl, Magdy A. Bayoumi	Self-Sleep Buffer for Distributed MTCMOS Design.	VLSI Design	2008	DBLP DOI BibTeX RDF
80	Nikhil Jayakumar, Sunil P. Khatri	A Predictably Low-Leakage ASIC Design Style.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
78	Ang-Chih Hsieh, Tzu-Teng Lin, Tsuang-Wei Chang, TingTing Hwang	A functionality-directed clustering technique for low-power MTCMOS design - computation of simultaneously discharging current.	ACM Trans. Design Autom. Electr. Syst.	2007	DBLP DOI BibTeX RDF	DSTN, low power, MTCMOS, sleep transistor
78	Naoaki Ohkubo, Kimiyoshi Usami	Delay modeling and static timing analysis for MTCMOS circuits.	ASP-DAC	2006	DBLP DOI BibTeX RDF	interpolation., selective-MT, delay, leakage power, static timing analysis, MTCMOS
72	Chanseok Hwang, Chang Woo Kang, Massoud Pedram	Gate Sizing and Replication to Minimize the Effects of Virtual Ground Parasitic Resistances in MTCMOS Designs.	ISQED	2006	DBLP DOI BibTeX RDF
72	Azadeh Davoodi, Ankur Srivastava 0001	Wake-up protocols for controlling current surges in MTCMOS-based technology.	ASP-DAC	2005	DBLP DOI BibTeX RDF
72	Mircea R. Stan, Marco Barcella	MTCMOS with outer feedback (MTOF) flip-flops.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
70	Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif	Approaches to run-time and standby mode leakage reduction in global buses.	ISLPED	2004	DBLP DOI BibTeX RDF	pulsed buses, leakage, repeaters, MTCMOS
64	Chandramouli Gopalakrishnan, Srinivas Katkoori	Resource Allocation and Binding Approach for Low Leakage Power.	VLSI Design	2003	DBLP DOI BibTeX RDF
62	Hanif Fatemi, Behnam Amelifard, Massoud Pedram	Power optimal MTCMOS repeater insertion for global buses.	ISLPED	2007	DBLP DOI BibTeX RDF	MTCMOS circuits, low-power design, buffer insertion
62	Benton H. Calhoun, Frank Honoré, Anantha P. Chandrakasan	Design methodology for fine-grained leakage control in MTCMOS.	ISLPED	2003	DBLP DOI BibTeX RDF	fine-grain sleep regions, sneak leakage, low power, design methodology, leakage, circuit design, sleep mode, MTCMOS
56	Tsuang-Wei Chang, TingTing Hwang, Sheng-Yu Hsu	Functionality directed clustering for low power MTCMOS design.	ASP-DAC	2005	DBLP DOI BibTeX RDF
56	Harmander Deogun, Rahul M. Rao, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka	Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization.	ISQED	2005	DBLP DOI BibTeX RDF
56	Shinichiro Mutoh, Satoshi Shigematsu, Yoshinori Gotoh, Shinsuke Konaka	Design Method of MTCMOS Power Switch for Low-Voltage High-Speed LSIs.	ASP-DAC	1999	DBLP DOI BibTeX RDF
48	Mindaugas Drazdziulis, Per Larsson-Edefors, Lars J. Svensson	Overdrive Power-Gating Techniques for Total Power Minimization.	ISVLSI	2007	DBLP DOI BibTeX RDF
48	Ranganath Gopalan, Chandramouli Gopalakrishnan, Srinivas Katkoori	Leakage Power Driven Behavioral Synthesis of Pipelined Datapaths.	ISVLSI	2005	DBLP DOI BibTeX RDF
48	Chandramouli Gopalakrishnan, Srinivas Katkoori	KnapBind: An Area-Efficient Binding Algorithm for Low-leakage Datapaths.	ICCD	2003	DBLP DOI BibTeX RDF
46	Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii	Low-overhead state-retaining elements for low-leakage MTCMOS design.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	MTCMOS design, state-retention, leakage power
46	Stephen V. Kosonocky, Michael Immediato, Peter E. Cottrell, Terence B. Hook, Randy W. Mann, Jeff Brown	Enchanced multi-threshold (MTCMOS) circuits using variable well bias.	ISLPED	2001	DBLP DOI BibTeX RDF	leakage control, low power digital circuit design, variable well bias, MTCMOS, multi-threshold
40	Saihua Lin, Hongli Gao, Huazhong Yang	Low Clock Swing D Flip-Flops Design by Using Output Control and MTCMOS.	PATMOS	2006	DBLP DOI BibTeX RDF
40	Behnam Amelifard, Farzan Fallah, Massoud Pedram	Low-power fanout optimization using MTCMOS and multi-Vt techniques.	ISLPED	2006	DBLP DOI BibTeX RDF	buffer chain, fanout tree, low-power design, fanout optimization
40	Xin Zhao, Yici Cai, Qiang Zhou 0001, Xianlong Hong	A novel low-power physical design methodology for MTCMOS.	ISCAS	2006	DBLP DOI BibTeX RDF
40	B. Chung, J. B. Kuo	Gate-level dual-threshold static power optimization methodology (GDSPOM) for designing high-speed low-power SOC applications using 90nm MTCMOS technology.	ISCAS	2006	DBLP DOI BibTeX RDF
40	Koushik K. Das, Shih-Hsien Lo, Ching-Te Chuang	High Performance MTCMOS Technique for Leakage Reduction in Hybrid SOI-Epitaxial Technologies with Enhanced-Mobility PFET Header.	VLSI Design	2006	DBLP DOI BibTeX RDF
40	David Levacq, Vincent Dessard, Denis Flandre	Ultra-low power flip-flops for MTCMOS circuits.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
40	Ramaprasath Vilangudipitchai, Poras T. Balsara	Power Switch Network Design for MTCMOS.	VLSI Design	2005	DBLP DOI BibTeX RDF
40	Mohab Anis, Mohamed Mahmoud, Mohamed I. Elmasry, Shawki Areibi	Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique.	DAC	2002	DBLP DOI BibTeX RDF
40	Mohamed W. Allam, Mohab Anis, Mohamed I. Elmasry	High-speed dynamic logic styles for scaled-down CMOS and MTCMOS technologies.	ISLPED	2000	DBLP DOI BibTeX RDF
38	Ahmad Al Zahrani, Andrew Bailey, Guoyuan Fu, Jia Di	Glitch-free design for multi-threshold CMOS NCL circuits.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	asynchronous circuit, mtcmos, glitch, threshold gate, null convention logic
38	Fatih Hamzaoglu, Mircea R. Stan	Circuit-level techniques to control gate leakage for sub-100nm CMOS.	ISLPED	2002	DBLP DOI BibTeX RDF	low power, MTCMOS, gate leakage, domino circuits
32	Vishal Khandelwal, Ankur Srivastava 0001	Leakage Control Through Fine-Grained Placement and Sizing of Sleep Transistors.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
32	Pietro Babighian, Luca Benini, Alberto Macii, Enrico Macii	Enabling fine-grain leakage management by voltage anchor insertion.	DATE	2006	DBLP DOI BibTeX RDF
32	Weiping Liao, Joseph M. Basile, Lei He 0001	Microarchitecture-level leakage reduction with data retention.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
32	Vishal Khandelwal, Ankur Srivastava 0001	Leakage control through fine-grained placement and sizing of sleep transistors.	ICCAD	2004	DBLP DOI BibTeX RDF
32	Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Katsuhiro Seta, Toshiyuki Furusawa	Automated selective multi-threshold design for ultra-low standby applications.	ISLPED	2002	DBLP DOI BibTeX RDF	standby leakage current, automated design, multi-threshold
32	James T. Kao, Anantha P. Chandrakasan, Dimitri A. Antoniadis	Transistor Sizing Issues and Tool For Multi-Threshold CMOS Technology.	DAC	1997	DBLP DOI BibTeX RDF
24	Sherif M. Sharroush	Optimum Sizing of the Sleep Transistor in MTCMOS Technology.	NILES	2020	DBLP DOI BibTeX RDF
24	Sherif M. Sharroush	An MTCMOS Subthreshold-Leakage Reduction Algorithm.	NILES	2020	DBLP DOI BibTeX RDF
24	Seunghan Baek, Sunmean Kim, Youngchang Choi, Seokhyeong Kang	MTCMOS-based Ternary to Binary Converter.	ISOCC	2020	DBLP DOI BibTeX RDF
24	Yuan Cao 0003, Biyin Wang, Xiaofang Pan, Xiaojin Zhao, Zhihuang Wen, Amine Bermak	A Compact 31.47 fJ/Conversion Subthreshold Level Shifter With Wide Conversion Range in 65 nm MTCMOS.	IEEE Access	2018	DBLP DOI BibTeX RDF
24	Indrit Myderrizi, Ali Zeki	A Tunable Swing-Reduced Driver in 0.13-μm MTCMOS Technology.	J. Circuits Syst. Comput.	2017	DBLP DOI BibTeX RDF
24	Hailong Jiao, Volkan Kursun	Mode transition timing and energy overhead analysis in noise-aware MTCMOS circuits.	Microelectron. J.	2014	DBLP DOI BibTeX RDF
24	Ankish Handa, Jitesh Chawla, Geetanjali Sharma	A novel high performance low power CMOS NOR gate using Voltage Scaling and MTCMOS technique.	ICACCI	2014	DBLP DOI BibTeX RDF
24	Chen-Bo Hsu, James B. Kuo	Power consumption optimization methodology (PCOM) for low-power/ low-voltage 32-bit microprocessor circuit design via MTCMOS.	MWSCAS	2014	DBLP DOI BibTeX RDF
24	Chen-Bo Hsu, Young Sik Hong, James B. Kuo	MTCMOS low-power optimization technique (LPOT) for 1V pipelined RISC CPU circuit.	ICECS	2014	DBLP DOI BibTeX RDF
24	Yi-Ming Wang, Mango Chia-Tso Chao, Shi-Hao Chen, Hung-Chun Li	Power-switch routing for reducing dynamic IR drop in multi-domain MTCMOS designs.	VLSI-DAT	2014	DBLP DOI BibTeX RDF
24	Chen-Bo Hsu, James B. Kuo	MTCMOS low-power design technique (LPDT) for low-voltage pipelined microprocessor circuits.	ISIC	2014	DBLP DOI BibTeX RDF
24	Hailong Jiao, Volkan Kursun	Reactivation Noise Suppression With Sleep Signal Slew Rate Modulation in MTCMOS Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2013	DBLP DOI BibTeX RDF
24	Shi-Hao Chen, Youn-Long Lin, Mango Chia-Tso Chao	Power-Up Sequence Control for MTCMOS Designs.	IEEE Trans. Very Large Scale Integr. Syst.	2013	DBLP DOI BibTeX RDF
24	Hailong Jiao, Volkan Kursun	Characterization of mode transition timing overhead for net energy savings in low-noise MTCMOS circuits.	VLSI-SoC	2013	DBLP DOI BibTeX RDF
24	Hailong Jiao, Volkan Kursun	Threshold Voltage Tuning for Faster Activation With Lower Noise in Tri-Mode MTCMOS Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2012	DBLP DOI BibTeX RDF
24	Yi-Ming Wang, Shi-Hao Chen, Mango Chia-Tso Chao	An Efficient Hamiltonian-cycle power-switch routing for MTCMOS designs.	ASP-DAC	2012	DBLP DOI BibTeX RDF
24	Hailong Jiao, Volkan Kursun	Multi-phase sleep signal modulation for mode transition noise mitigation in MTCMOS circuits.	ISOCC	2012	DBLP DOI BibTeX RDF
24	Shyam Akashe, Rajeev Sharma, Nitesh Tiwari, Jayram Shrivas	Implementation of 2: 4 DECODER for low leakage Using MTCMOS Technique in 45 Nanometre Regime.	BIC-TA (2)	2012	DBLP DOI BibTeX RDF
24	Richa Saraswat, Shyam Akashe, Shyam Babu	Analysis and Simulation of Full Adder Design Using MTCMOS Technique.	BIC-TA (2)	2012	DBLP DOI BibTeX RDF
24	Hailong Jiao, Volkan Kursun	Ground Bouncing Noise Suppression Techniques for Data Preserving Sequential MTCMOS Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2011	DBLP DOI BibTeX RDF
24	Hailong Jiao, Volkan Kursun	Noise-Aware Data Preserving Sequential MTCMOS Circuits with Dynamic Forward Body Bias.	J. Circuits Syst. Comput.	2011	DBLP DOI BibTeX RDF
24	Henry X. F. Huang, Steven R. S. Shen, James B. Kuo	Cell-Based Leakage Power Reduction Priority (CBLPRP) Optimization Methodology for Designing SOC Applications Using MTCMOS Technique.	PATMOS	2011	DBLP DOI BibTeX RDF
24	Harmander Singh, Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown	Dynamically Pulsed MTCMOS With Bus Encoding for Reduction of Total Power and Crosstalk Noise.	IEEE Trans. Very Large Scale Integr. Syst.	2010	DBLP DOI BibTeX RDF
24	Hailong Jiao, Volkan Kursun	Ground-Bouncing-Noise-Aware Combinational MTCMOS Circuits.	IEEE Trans. Circuits Syst. I Regul. Pap.	2010	DBLP DOI BibTeX RDF
24	Hailong Jiao, Volkan Kursun	Reactivation noise suppression with threshold voltage tuning in sequential MTCMOS circuits.	VLSI-SoC	2010	DBLP DOI BibTeX RDF
24	Szu-Pang Mu, Yi-Ming Wang, Hao-Yu Yang, Mango Chia-Tso Chao, Shi-Hao Chen, Chih-Mou Tseng, Tsung-Ying Tsai	Testing methods for detecting stuck-open power switches in coarse-grain MTCMOS designs.	ICCAD	2010	DBLP DOI BibTeX RDF
24	Hailong Jiao, Volkan Kursun	Smooth awakenings: Reactivation noise suppressed low-leakage and robust MTCMOS flip-flops.	ISCAS	2010	DBLP DOI BibTeX RDF
24	Chih-Hsiang Lin, James B. Kuo	Low-voltage SOI CMOS DTMOS/MTCMOS circuit technique for design optimization of low-power SOC applications.	ISCAS	2010	DBLP DOI BibTeX RDF
24	Qiang Zhou 0001, Xin Zhao, Yici Cai, Xianlong Hong	An MTCMOS technology for low-power physical design.	Integr.	2009	DBLP DOI BibTeX RDF
24	Chih-Hsiang Lin, James B. Kuo	Design Optimization of Low-Power 90nm CMOS SOC Application Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS): BP-DTMOS-DT Technique.	PATMOS	2009	DBLP DOI BibTeX RDF
24	Tsun-Ming Tseng, Mango Chia-Tso Chao, Chien Pang Lu, Chen Hsing Lo	Power-switch routing for coarse-grain MTCMOS technologies.	ICCAD	2009	DBLP DOI BibTeX RDF
24	Javid Jaffari, Mohab Anis	Thermal Driven Placement for Island-style MTCMOS FPGAs.	J. Comput.	2008	DBLP BibTeX RDF
24	Ehsan Pakbaznia, Massoud Pedram	Coarse-Grain MTCMOS Sleep Transistor Sizing Using Delay Budgeting.	DATE	2008	DBLP DOI BibTeX RDF
24	Andrea Calimera, Luca Benini, Enrico Macii	Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints.	DATE	2008	DBLP DOI BibTeX RDF
24	Charbel J. Akl, Magdy A. Bayoumi	Reducing wakeup latency and energy of MTCMOS circuits via keeper insertion.	ISLPED	2008	DBLP DOI BibTeX RDF
24	Afshin Abdollahi, Farzan Fallah, Massoud Pedram	A Robust Power Gating Structure and Power Mode Transition Strategy for MTCMOS Design.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
24	Anand Ramalingam, Anirudh Devgan, David Z. Pan	Wakeup Scheduling in MTCMOS Circuits Using Successive Relaxation to Minimize Ground Bounce.	J. Low Power Electron.	2007	DBLP DOI BibTeX RDF
24	Akira Tada, Hiromi Notani, Genichi Tanaka, Takashi Ipposhi, Masaaki Iijima, Masahiro Numa	Charge recycling in MTCMOS circuits with block dividing.	IEICE Electron. Express	2007	DBLP DOI BibTeX RDF
24	Zhiyu Liu, Volkan Kursun	New MTCMOS Flip-Flops with Simple Control Circuitry and Low Leakage Data Retention Capability.	ICECS	2007	DBLP DOI BibTeX RDF
24	Sachin Idgunji	Case study of a low power MTCMOS based ARM926 SoC : Design, analysis and test challenges.	ITC	2007	DBLP DOI BibTeX RDF
24	Nobutaro Shibata, Hiroshi Kiya, Shigehiro Kurita, Hidetaka Okamoto, Masa'aki Tan'no, Takakuni Douseki	A 0.5-V 25-MHz 1-mW 256-kb MTCMOS/SOI SRAM for solar-power-operated portable personal digital equipment - sure write operation by using step-down negatively overdriven bitline scheme.	IEEE J. Solid State Circuits	2006	DBLP DOI BibTeX RDF
24	Naoaki Ohkubo, Kimiyoshi Usami	Delay Modeling and Critical-Path Delay Calculation for MTCMOS Circuits.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2006	DBLP DOI BibTeX RDF
24	Bong Hyun Lee, Young Hwan Kim, Kwang-Ok Jeong	Clock-Free MTCMOS Flip-Flops with High Speed and Low Power.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2005	DBLP DOI BibTeX RDF
24	Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry	A leakage-aware CAD flow for MTCMOS FPGA architectures (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
24	Harmander Singh Deogun, Dennis Sylvester, Rahul M. Rao, Kevin J. Nowka	Adaptive MTCMOS for dynamic leakage and frequency control using variable footer strength.	SoCC	2005	DBLP DOI BibTeX RDF
24	Afshin Abdollahi, Farzan Fallah, Massoud Pedram	An effective power mode transition technique in MTCMOS circuits.	DAC	2005	DBLP DOI BibTeX RDF
24	Benton H. Calhoun, Frank Honoré, Anantha P. Chandrakasan	A leakage reduction methodology for distributed MTCMOS.	IEEE J. Solid State Circuits	2004	DBLP DOI BibTeX RDF
24	Wenxin Wang, Mohab Anis, Shawki Areibi	Fast techniques for standby leakage reduction in MTCMOS circuits.	SoCC	2004	DBLP DOI BibTeX RDF
24	Rahul M. Rao, Jeffrey L. Burns, Richard B. Brown	Analysis and Optimization of Enhanced MTCMOS Scheme.	VLSI Design	2004	DBLP DOI BibTeX RDF
24	Mohab Anis, Shawki Areibi, Mohamed I. Elmasry	Design and optimization of multithreshold CMOS (MTCMOS) circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
24	Takakuni Douseki, Tsuneo Tsukahara, Yoshifumi Yoshida, Fumiyasu Utsunomiya, Norio Hama	A batteryless wireless system with MTCMOS/SOI circuit technology.	CICC	2003	DBLP DOI BibTeX RDF
24	Mohab Anis, Mohamed W. Allam, Mohamed I. Elmasry	Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
24	Nobutaro Shibata, Hiroki Morimura, Mitsuru Harada	1-V 100-MHz embedded SRAM techniques for battery-operated MTCMOS/SIMOX ASICs.	IEEE J. Solid State Circuits	2000	DBLP DOI BibTeX RDF
24	Nobutaro Shibata, Hiroki Morimura, Mayumi Watanabe	A 1-V, 10-MHz, 3.5-mW, 1-Mb MTCMOS SRAM: with charge-recycling input/output buffers.	IEEE J. Solid State Circuits	1999	DBLP DOI BibTeX RDF
24	James T. Kao, Siva G. Narendra, Anantha P. Chandrakasan	MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns.	DAC	1998	DBLP DOI BibTeX RDF	low power, synthesis, placement, flip-flops, voltage scaling, codec, MPEG4, level converters, design automatian
24	Satoshi Shigematsu, Shin'ichiro Mutoh, Yasuyuki Matsuya, Yasuyuki Tanabe, Junzo Yamada	A 1-V high-speed MTCMOS circuit scheme for power-down application circuits.	IEEE J. Solid State Circuits	1997	DBLP DOI BibTeX RDF